1#ifndef _ASM_PARISC_ROPES_H_ 2#define _ASM_PARISC_ROPES_H_ 3 4#include <asm/parisc-device.h> 5 6#ifdef CONFIG_64BIT 7/* "low end" PA8800 machines use ZX1 chipset: PAT PDC and only run 64-bit */ 8#define ZX1_SUPPORT 9#endif 10 11#ifdef CONFIG_PROC_FS 12/* depends on proc fs support. But costs CPU performance */ 13#undef SBA_COLLECT_STATS 14#endif 15 16/* 17** The number of pdir entries to "free" before issuing 18** a read to PCOM register to flush out PCOM writes. 19** Interacts with allocation granularity (ie 4 or 8 entries 20** allocated and free'd/purged at a time might make this 21** less interesting). 22*/ 23#define DELAYED_RESOURCE_CNT 16 24 25#define MAX_IOC 2 /* per Ike. Pluto/Astro only have 1. */ 26#define ROPES_PER_IOC 8 /* per Ike half or Pluto/Astro */ 27 28struct ioc { 29 void __iomem *ioc_hpa; /* I/O MMU base address */ 30 char *res_map; /* resource map, bit == pdir entry */ 31 u64 *pdir_base; /* physical base address */ 32 unsigned long ibase; /* pdir IOV Space base - shared w/lba_pci */ 33 unsigned long imask; /* pdir IOV Space mask - shared w/lba_pci */ 34#ifdef ZX1_SUPPORT 35 unsigned long iovp_mask; /* help convert IOVA to IOVP */ 36#endif 37 unsigned long *res_hint; /* next avail IOVP - circular search */ 38 spinlock_t res_lock; 39 unsigned int res_bitshift; /* from the LEFT! */ 40 unsigned int res_size; /* size of resource map in bytes */ 41#ifdef SBA_HINT_SUPPORT 42 unsigned long hint_mask_pdir; /* bits used for DMA hints */ 43 unsigned int hint_shift_pdir; 44#endif 45#if DELAYED_RESOURCE_CNT > 0 46 int saved_cnt; 47 struct sba_dma_pair { 48 dma_addr_t iova; 49 size_t size; 50 } saved[DELAYED_RESOURCE_CNT]; 51#endif 52 53#ifdef SBA_COLLECT_STATS 54#define SBA_SEARCH_SAMPLE 0x100 55 unsigned long avg_search[SBA_SEARCH_SAMPLE]; 56 unsigned long avg_idx; /* current index into avg_search */ 57 unsigned long used_pages; 58 unsigned long msingle_calls; 59 unsigned long msingle_pages; 60 unsigned long msg_calls; 61 unsigned long msg_pages; 62 unsigned long usingle_calls; 63 unsigned long usingle_pages; 64 unsigned long usg_calls; 65 unsigned long usg_pages; 66#endif 67 /* STUFF We don't need in performance path */ 68 unsigned int pdir_size; /* in bytes, determined by IOV Space size */ 69}; 70 71struct sba_device { 72 struct sba_device *next; /* list of SBA's in system */ 73 struct parisc_device *dev; /* dev found in bus walk */ 74 const char *name; 75 void __iomem *sba_hpa; /* base address */ 76 spinlock_t sba_lock; 77 unsigned int flags; /* state/functionality enabled */ 78 unsigned int hw_rev; /* HW revision of chip */ 79 80 struct resource chip_resv; /* MMIO reserved for chip */ 81 struct resource iommu_resv; /* MMIO reserved for iommu */ 82 83 unsigned int num_ioc; /* number of on-board IOC's */ 84 struct ioc ioc[MAX_IOC]; 85}; 86 87#define ASTRO_RUNWAY_PORT 0x582 88#define IKE_MERCED_PORT 0x803 89#define REO_MERCED_PORT 0x804 90#define REOG_MERCED_PORT 0x805 91#define PLUTO_MCKINLEY_PORT 0x880 92 93static inline int IS_ASTRO(struct parisc_device *d) { 94 return d->id.hversion == ASTRO_RUNWAY_PORT; 95} 96 97static inline int IS_IKE(struct parisc_device *d) { 98 return d->id.hversion == IKE_MERCED_PORT; 99} 100 101static inline int IS_PLUTO(struct parisc_device *d) { 102 return d->id.hversion == PLUTO_MCKINLEY_PORT; 103} 104 105#define PLUTO_IOVA_BASE (1UL*1024*1024*1024) /* 1GB */ 106#define PLUTO_IOVA_SIZE (1UL*1024*1024*1024) /* 1GB */ 107#define PLUTO_GART_SIZE (PLUTO_IOVA_SIZE / 2) 108 109#define SBA_PDIR_VALID_BIT 0x8000000000000000ULL 110 111#define SBA_AGPGART_COOKIE 0x0000badbadc0ffeeULL 112 113#define SBA_FUNC_ID 0x0000 /* function id */ 114#define SBA_FCLASS 0x0008 /* function class, bist, header, rev... */ 115 116#define SBA_FUNC_SIZE 4096 /* SBA configuration function reg set */ 117 118#define ASTRO_IOC_OFFSET (32 * SBA_FUNC_SIZE) 119#define PLUTO_IOC_OFFSET (1 * SBA_FUNC_SIZE) 120/* Ike's IOC's occupy functions 2 and 3 */ 121#define IKE_IOC_OFFSET(p) ((p+2) * SBA_FUNC_SIZE) 122 123#define IOC_CTRL 0x8 /* IOC_CTRL offset */ 124#define IOC_CTRL_TC (1 << 0) /* TOC Enable */ 125#define IOC_CTRL_CE (1 << 1) /* Coalesce Enable */ 126#define IOC_CTRL_DE (1 << 2) /* Dillon Enable */ 127#define IOC_CTRL_RM (1 << 8) /* Real Mode */ 128#define IOC_CTRL_NC (1 << 9) /* Non Coherent Mode */ 129#define IOC_CTRL_D4 (1 << 11) /* Disable 4-byte coalescing */ 130#define IOC_CTRL_DD (1 << 13) /* Disable distr. LMMIO range coalescing */ 131 132/* 133** Offsets into MBIB (Function 0 on Ike and hopefully Astro) 134** Firmware programs this stuff. Don't touch it. 135*/ 136#define LMMIO_DIRECT0_BASE 0x300 137#define LMMIO_DIRECT0_MASK 0x308 138#define LMMIO_DIRECT0_ROUTE 0x310 139 140#define LMMIO_DIST_BASE 0x360 141#define LMMIO_DIST_MASK 0x368 142#define LMMIO_DIST_ROUTE 0x370 143 144#define IOS_DIST_BASE 0x390 145#define IOS_DIST_MASK 0x398 146#define IOS_DIST_ROUTE 0x3A0 147 148#define IOS_DIRECT_BASE 0x3C0 149#define IOS_DIRECT_MASK 0x3C8 150#define IOS_DIRECT_ROUTE 0x3D0 151 152/* 153** Offsets into I/O TLB (Function 2 and 3 on Ike) 154*/ 155#define ROPE0_CTL 0x200 /* "regbus pci0" */ 156#define ROPE1_CTL 0x208 157#define ROPE2_CTL 0x210 158#define ROPE3_CTL 0x218 159#define ROPE4_CTL 0x220 160#define ROPE5_CTL 0x228 161#define ROPE6_CTL 0x230 162#define ROPE7_CTL 0x238 163 164#define IOC_ROPE0_CFG 0x500 /* pluto only */ 165#define IOC_ROPE_AO 0x10 /* Allow "Relaxed Ordering" */ 166 167#define HF_ENABLE 0x40 168 169#define IOC_IBASE 0x300 /* IO TLB */ 170#define IOC_IMASK 0x308 171#define IOC_PCOM 0x310 172#define IOC_TCNFG 0x318 173#define IOC_PDIR_BASE 0x320 174 175/* 176** IOC supports 4/8/16/64KB page sizes (see TCNFG register) 177** It's safer (avoid memory corruption) to keep DMA page mappings 178** equivalently sized to VM PAGE_SIZE. 179** 180** We really can't avoid generating a new mapping for each 181** page since the Virtual Coherence Index has to be generated 182** and updated for each page. 183** 184** PAGE_SIZE could be greater than IOVP_SIZE. But not the inverse. 185*/ 186#define IOVP_SIZE PAGE_SIZE 187#define IOVP_SHIFT PAGE_SHIFT 188#define IOVP_MASK PAGE_MASK 189 190#define SBA_PERF_CFG 0x708 /* Performance Counter stuff */ 191#define SBA_PERF_MASK1 0x718 192#define SBA_PERF_MASK2 0x730 193 194/* 195** Offsets into PCI Performance Counters (functions 12 and 13) 196** Controlled by PERF registers in function 2 & 3 respectively. 197*/ 198#define SBA_PERF_CNT1 0x200 199#define SBA_PERF_CNT2 0x208 200#define SBA_PERF_CNT3 0x210 201 202/* 203** lba_device: Per instance Elroy data structure 204*/ 205struct lba_device { 206 struct pci_hba_data hba; 207 208 spinlock_t lba_lock; 209 void *iosapic_obj; 210 211#ifdef CONFIG_64BIT 212 void __iomem *iop_base; /* PA_VIEW - for IO port accessor funcs */ 213#endif 214 215 int flags; /* state/functionality enabled */ 216 int hw_rev; /* HW revision of chip */ 217}; 218 219#define ELROY_HVERS 0x782 220#define MERCURY_HVERS 0x783 221#define QUICKSILVER_HVERS 0x784 222 223static inline int IS_ELROY(struct parisc_device *d) { 224 return (d->id.hversion == ELROY_HVERS); 225} 226 227static inline int IS_MERCURY(struct parisc_device *d) { 228 return (d->id.hversion == MERCURY_HVERS); 229} 230 231static inline int IS_QUICKSILVER(struct parisc_device *d) { 232 return (d->id.hversion == QUICKSILVER_HVERS); 233} 234 235static inline int agp_mode_mercury(void __iomem *hpa) { 236 u64 bus_mode; 237 238 bus_mode = readl(hpa + 0x0620); 239 if (bus_mode & 1) 240 return 1; 241 242 return 0; 243} 244 245/* 246** I/O SAPIC init function 247** Caller knows where an I/O SAPIC is. LBA has an integrated I/O SAPIC. 248** Call setup as part of per instance initialization. 249** (ie *not* init_module() function unless only one is present.) 250** fixup_irq is to initialize PCI IRQ line support and 251** virtualize pcidev->irq value. To be called by pci_fixup_bus(). 252*/ 253extern void *iosapic_register(unsigned long hpa); 254extern int iosapic_fixup_irq(void *obj, struct pci_dev *pcidev); 255 256#define LBA_FUNC_ID 0x0000 /* function id */ 257#define LBA_FCLASS 0x0008 /* function class, bist, header, rev... */ 258#define LBA_CAPABLE 0x0030 /* capabilities register */ 259 260#define LBA_PCI_CFG_ADDR 0x0040 /* poke CFG address here */ 261#define LBA_PCI_CFG_DATA 0x0048 /* read or write data here */ 262 263#define LBA_PMC_MTLT 0x0050 /* Firmware sets this - read only. */ 264#define LBA_FW_SCRATCH 0x0058 /* Firmware writes the PCI bus number here. */ 265#define LBA_ERROR_ADDR 0x0070 /* On error, address gets logged here */ 266 267#define LBA_ARB_MASK 0x0080 /* bit 0 enable arbitration. PAT/PDC enables */ 268#define LBA_ARB_PRI 0x0088 /* firmware sets this. */ 269#define LBA_ARB_MODE 0x0090 /* firmware sets this. */ 270#define LBA_ARB_MTLT 0x0098 /* firmware sets this. */ 271 272#define LBA_MOD_ID 0x0100 /* Module ID. PDC_PAT_CELL reports 4 */ 273 274#define LBA_STAT_CTL 0x0108 /* Status & Control */ 275#define LBA_BUS_RESET 0x01 /* Deassert PCI Bus Reset Signal */ 276#define CLEAR_ERRLOG 0x10 /* "Clear Error Log" cmd */ 277#define CLEAR_ERRLOG_ENABLE 0x20 /* "Clear Error Log" Enable */ 278#define HF_ENABLE 0x40 /* enable HF mode (default is -1 mode) */ 279 280#define LBA_LMMIO_BASE 0x0200 /* < 4GB I/O address range */ 281#define LBA_LMMIO_MASK 0x0208 282 283#define LBA_GMMIO_BASE 0x0210 /* > 4GB I/O address range */ 284#define LBA_GMMIO_MASK 0x0218 285 286#define LBA_WLMMIO_BASE 0x0220 /* All < 4GB ranges under the same *SBA* */ 287#define LBA_WLMMIO_MASK 0x0228 288 289#define LBA_WGMMIO_BASE 0x0230 /* All > 4GB ranges under the same *SBA* */ 290#define LBA_WGMMIO_MASK 0x0238 291 292#define LBA_IOS_BASE 0x0240 /* I/O port space for this LBA */ 293#define LBA_IOS_MASK 0x0248 294 295#define LBA_ELMMIO_BASE 0x0250 /* Extra LMMIO range */ 296#define LBA_ELMMIO_MASK 0x0258 297 298#define LBA_EIOS_BASE 0x0260 /* Extra I/O port space */ 299#define LBA_EIOS_MASK 0x0268 300 301#define LBA_GLOBAL_MASK 0x0270 /* Mercury only: Global Address Mask */ 302#define LBA_DMA_CTL 0x0278 /* firmware sets this */ 303 304#define LBA_IBASE 0x0300 /* SBA DMA support */ 305#define LBA_IMASK 0x0308 306 307#define LBA_HINT_CFG 0x0310 308#define LBA_HINT_BASE 0x0380 /* 14 registers at every 8 bytes. */ 309 310#define LBA_BUS_MODE 0x0620 311 312/* ERROR regs are needed for config cycle kluges */ 313#define LBA_ERROR_CONFIG 0x0680 314#define LBA_SMART_MODE 0x20 315#define LBA_ERROR_STATUS 0x0688 316#define LBA_ROPE_CTL 0x06A0 317 318#define LBA_IOSAPIC_BASE 0x800 /* Offset of IRQ logic */ 319 320#endif /*_ASM_PARISC_ROPES_H_*/ 321