1/* 2 * This program is free software; you can redistribute it and/or 3 * modify it under the terms of the GNU General Public License 4 * as published by the Free Software Foundation; either version 2 5 * of the License, or (at your option) any later version. 6 * 7 * This program is distributed in the hope that it will be useful, 8 * but WITHOUT ANY WARRANTY; without even the implied warranty of 9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 10 * GNU General Public License for more details. 11 * 12 * You should have received a copy of the GNU General Public License 13 * along with this program; if not, write to the Free Software 14 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. 15 * 16 * Copyright (C) 2001, 2002, 2003 Broadcom Corporation 17 * Copyright (C) 2007 Ralf Baechle <ralf@linux-mips.org> 18 * Copyright (C) 2007 MIPS Technologies, Inc. 19 * written by Ralf Baechle <ralf@linux-mips.org> 20 */ 21 22#undef DEBUG 23 24#include <linux/device.h> 25#include <linux/module.h> 26#include <linux/kernel.h> 27#include <linux/types.h> 28#include <linux/init.h> 29#include <linux/interrupt.h> 30#include <linux/vmalloc.h> 31#include <linux/fs.h> 32#include <linux/errno.h> 33#include <linux/wait.h> 34#include <asm/io.h> 35#include <asm/sibyte/sb1250.h> 36 37#if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80) 38#include <asm/sibyte/bcm1480_regs.h> 39#include <asm/sibyte/bcm1480_scd.h> 40#include <asm/sibyte/bcm1480_int.h> 41#elif defined(CONFIG_SIBYTE_SB1250) || defined(CONFIG_SIBYTE_BCM112X) 42#include <asm/sibyte/sb1250_regs.h> 43#include <asm/sibyte/sb1250_scd.h> 44#include <asm/sibyte/sb1250_int.h> 45#else 46#error invalid SiByte UART configuation 47#endif 48 49#if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80) 50#undef K_INT_TRACE_FREEZE 51#define K_INT_TRACE_FREEZE K_BCM1480_INT_TRACE_FREEZE 52#undef K_INT_PERF_CNT 53#define K_INT_PERF_CNT K_BCM1480_INT_PERF_CNT 54#endif 55 56#include <asm/system.h> 57#include <asm/uaccess.h> 58 59#define SBPROF_TB_MAJOR 240 60 61typedef u64 tb_sample_t[6*256]; 62 63enum open_status { 64 SB_CLOSED, 65 SB_OPENING, 66 SB_OPEN 67}; 68 69struct sbprof_tb { 70 wait_queue_head_t tb_sync; 71 wait_queue_head_t tb_read; 72 struct mutex lock; 73 enum open_status open; 74 tb_sample_t *sbprof_tbbuf; 75 int next_tb_sample; 76 77 volatile int tb_enable; 78 volatile int tb_armed; 79 80}; 81 82static struct sbprof_tb sbp; 83 84#define MAX_SAMPLE_BYTES (24*1024*1024) 85#define MAX_TBSAMPLE_BYTES (12*1024*1024) 86 87#define MAX_SAMPLES (MAX_SAMPLE_BYTES/sizeof(u_int32_t)) 88#define TB_SAMPLE_SIZE (sizeof(tb_sample_t)) 89#define MAX_TB_SAMPLES (MAX_TBSAMPLE_BYTES/TB_SAMPLE_SIZE) 90 91/* ioctls */ 92#define SBPROF_ZBSTART _IOW('s', 0, int) 93#define SBPROF_ZBSTOP _IOW('s', 1, int) 94#define SBPROF_ZBWAITFULL _IOW('s', 2, int) 95 96/* 97 * Routines for using 40-bit SCD cycle counter 98 * 99 * Client responsible for either handling interrupts or making sure 100 * the cycles counter never saturates, e.g., by doing 101 * zclk_timer_init(0) at least every 2^40 - 1 ZCLKs. 102 */ 103 104/* 105 * Configures SCD counter 0 to count ZCLKs starting from val; 106 * Configures SCD counters1,2,3 to count nothing. 107 * Must not be called while gathering ZBbus profiles. 108 */ 109 110#define zclk_timer_init(val) \ 111 __asm__ __volatile__ (".set push;" \ 112 ".set mips64;" \ 113 "la $8, 0xb00204c0;" /* SCD perf_cnt_cfg */ \ 114 "sd %0, 0x10($8);" /* write val to counter0 */ \ 115 "sd %1, 0($8);" /* config counter0 for zclks*/ \ 116 ".set pop" \ 117 : /* no outputs */ \ 118 /* enable, counter0 */ \ 119 : /* inputs */ "r"(val), "r" ((1ULL << 33) | 1ULL) \ 120 : /* modifies */ "$8" ) 121 122 123/* Reads SCD counter 0 and puts result in value 124 unsigned long long val; */ 125#define zclk_get(val) \ 126 __asm__ __volatile__ (".set push;" \ 127 ".set mips64;" \ 128 "la $8, 0xb00204c0;" /* SCD perf_cnt_cfg */ \ 129 "ld %0, 0x10($8);" /* write val to counter0 */ \ 130 ".set pop" \ 131 : /* outputs */ "=r"(val) \ 132 : /* inputs */ \ 133 : /* modifies */ "$8" ) 134 135#define DEVNAME "sb_tbprof" 136 137#define TB_FULL (sbp.next_tb_sample == MAX_TB_SAMPLES) 138 139/* 140 * Support for ZBbus sampling using the trace buffer 141 * 142 * We use the SCD performance counter interrupt, caused by a Zclk counter 143 * overflow, to trigger the start of tracing. 144 * 145 * We set the trace buffer to sample everything and freeze on 146 * overflow. 147 * 148 * We map the interrupt for trace_buffer_freeze to handle it on CPU 0. 149 * 150 */ 151 152static u64 tb_period; 153 154static void arm_tb(void) 155{ 156 u64 scdperfcnt; 157 u64 next = (1ULL << 40) - tb_period; 158 u64 tb_options = M_SCD_TRACE_CFG_FREEZE_FULL; 159 160 __raw_writeq(0, IOADDR(A_SCD_PERF_CNT_1)); 161 scdperfcnt = __raw_readq(IOADDR(A_SCD_PERF_CNT_CFG)); 162 163 /* 164 * Unfortunately, in Pass 2 we must clear all counters to knock down 165 * a previous interrupt request. This means that bus profiling 166 * requires ALL of the SCD perf counters. 167 */ 168#if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80) 169 __raw_writeq((scdperfcnt & ~M_SPC_CFG_SRC1) | 170 /* keep counters 0,2,3,4,5,6,7 as is */ 171 V_SPC_CFG_SRC1(1), /* counter 1 counts cycles */ 172 IOADDR(A_BCM1480_SCD_PERF_CNT_CFG0)); 173 __raw_writeq( 174 M_SPC_CFG_ENABLE | /* enable counting */ 175 M_SPC_CFG_CLEAR | /* clear all counters */ 176 V_SPC_CFG_SRC1(1), /* counter 1 counts cycles */ 177 IOADDR(A_BCM1480_SCD_PERF_CNT_CFG1)); 178#else 179 __raw_writeq((scdperfcnt & ~M_SPC_CFG_SRC1) | 180 /* keep counters 0,2,3 as is */ 181 M_SPC_CFG_ENABLE | /* enable counting */ 182 M_SPC_CFG_CLEAR | /* clear all counters */ 183 V_SPC_CFG_SRC1(1), /* counter 1 counts cycles */ 184 IOADDR(A_SCD_PERF_CNT_CFG)); 185#endif 186 __raw_writeq(next, IOADDR(A_SCD_PERF_CNT_1)); 187 /* Reset the trace buffer */ 188 __raw_writeq(M_SCD_TRACE_CFG_RESET, IOADDR(A_SCD_TRACE_CFG)); 189 __raw_writeq(tb_options, IOADDR(A_SCD_TRACE_CFG)); 190 sbp.tb_armed = 1; 191} 192 193static irqreturn_t sbprof_tb_intr(int irq, void *dev_id) 194{ 195 int i; 196 197 pr_debug(DEVNAME ": tb_intr\n"); 198 199 if (sbp.next_tb_sample < MAX_TB_SAMPLES) { 200 u64 *p = sbp.sbprof_tbbuf[sbp.next_tb_sample++]; 201 /* Read out trace */ 202 __raw_writeq(M_SCD_TRACE_CFG_START_READ, 203 IOADDR(A_SCD_TRACE_CFG)); 204 __asm__ __volatile__ ("sync" : : : "memory"); 205 /* Loop runs backwards because bundles are read out in reverse order */ 206 for (i = 256 * 6; i > 0; i -= 6) { 207 /* Subscripts decrease to put bundle in the order */ 208 /* t0 lo, t0 hi, t1 lo, t1 hi, t2 lo, t2 hi */ 209 p[i - 1] = __raw_readq(IOADDR(A_SCD_TRACE_READ)); 210 /* read t2 hi */ 211 p[i - 2] = __raw_readq(IOADDR(A_SCD_TRACE_READ)); 212 /* read t2 lo */ 213 p[i - 3] = __raw_readq(IOADDR(A_SCD_TRACE_READ)); 214 /* read t1 hi */ 215 p[i - 4] = __raw_readq(IOADDR(A_SCD_TRACE_READ)); 216 /* read t1 lo */ 217 p[i - 5] = __raw_readq(IOADDR(A_SCD_TRACE_READ)); 218 /* read t0 hi */ 219 p[i - 6] = __raw_readq(IOADDR(A_SCD_TRACE_READ)); 220 /* read t0 lo */ 221 } 222 if (!sbp.tb_enable) { 223 pr_debug(DEVNAME ": tb_intr shutdown\n"); 224 __raw_writeq(M_SCD_TRACE_CFG_RESET, 225 IOADDR(A_SCD_TRACE_CFG)); 226 sbp.tb_armed = 0; 227 wake_up_interruptible(&sbp.tb_sync); 228 } else { 229 /* knock down current interrupt and get another one later */ 230 arm_tb(); 231 } 232 } else { 233 /* No more trace buffer samples */ 234 pr_debug(DEVNAME ": tb_intr full\n"); 235 __raw_writeq(M_SCD_TRACE_CFG_RESET, IOADDR(A_SCD_TRACE_CFG)); 236 sbp.tb_armed = 0; 237 if (!sbp.tb_enable) 238 wake_up_interruptible(&sbp.tb_sync); 239 wake_up_interruptible(&sbp.tb_read); 240 } 241 return IRQ_HANDLED; 242} 243 244static irqreturn_t sbprof_pc_intr(int irq, void *dev_id) 245{ 246 printk(DEVNAME ": unexpected pc_intr"); 247 return IRQ_NONE; 248} 249 250/* 251 * Requires: Already called zclk_timer_init with a value that won't 252 * saturate 40 bits. No subsequent use of SCD performance counters 253 * or trace buffer. 254 */ 255 256static int sbprof_zbprof_start(struct file *filp) 257{ 258 u64 scdperfcnt; 259 int err; 260 261 if (xchg(&sbp.tb_enable, 1)) 262 return -EBUSY; 263 264 pr_debug(DEVNAME ": starting\n"); 265 266 sbp.next_tb_sample = 0; 267 filp->f_pos = 0; 268 269 err = request_irq(K_INT_TRACE_FREEZE, sbprof_tb_intr, 0, 270 DEVNAME " trace freeze", &sbp); 271 if (err) 272 return -EBUSY; 273 274 /* Make sure there isn't a perf-cnt interrupt waiting */ 275 scdperfcnt = __raw_readq(IOADDR(A_SCD_PERF_CNT_CFG)); 276 /* Disable and clear counters, override SRC_1 */ 277 __raw_writeq((scdperfcnt & ~(M_SPC_CFG_SRC1 | M_SPC_CFG_ENABLE)) | 278 M_SPC_CFG_ENABLE | M_SPC_CFG_CLEAR | V_SPC_CFG_SRC1(1), 279 IOADDR(A_SCD_PERF_CNT_CFG)); 280 281 /* 282 * We grab this interrupt to prevent others from trying to use 283 * it, even though we don't want to service the interrupts 284 * (they only feed into the trace-on-interrupt mechanism) 285 */ 286 if (request_irq(K_INT_PERF_CNT, sbprof_pc_intr, 0, DEVNAME " scd perfcnt", &sbp)) { 287 free_irq(K_INT_TRACE_FREEZE, &sbp); 288 return -EBUSY; 289 } 290 291 /* 292 * I need the core to mask these, but the interrupt mapper to 293 * pass them through. I am exploiting my knowledge that 294 * cp0_status masks out IP[5]. krw 295 */ 296#if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80) 297 __raw_writeq(K_BCM1480_INT_MAP_I3, 298 IOADDR(A_BCM1480_IMR_REGISTER(0, R_BCM1480_IMR_INTERRUPT_MAP_BASE_L) + 299 ((K_BCM1480_INT_PERF_CNT & 0x3f) << 3))); 300#else 301 __raw_writeq(K_INT_MAP_I3, 302 IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_MAP_BASE) + 303 (K_INT_PERF_CNT << 3))); 304#endif 305 306 /* Initialize address traps */ 307 __raw_writeq(0, IOADDR(A_ADDR_TRAP_UP_0)); 308 __raw_writeq(0, IOADDR(A_ADDR_TRAP_UP_1)); 309 __raw_writeq(0, IOADDR(A_ADDR_TRAP_UP_2)); 310 __raw_writeq(0, IOADDR(A_ADDR_TRAP_UP_3)); 311 312 __raw_writeq(0, IOADDR(A_ADDR_TRAP_DOWN_0)); 313 __raw_writeq(0, IOADDR(A_ADDR_TRAP_DOWN_1)); 314 __raw_writeq(0, IOADDR(A_ADDR_TRAP_DOWN_2)); 315 __raw_writeq(0, IOADDR(A_ADDR_TRAP_DOWN_3)); 316 317 __raw_writeq(0, IOADDR(A_ADDR_TRAP_CFG_0)); 318 __raw_writeq(0, IOADDR(A_ADDR_TRAP_CFG_1)); 319 __raw_writeq(0, IOADDR(A_ADDR_TRAP_CFG_2)); 320 __raw_writeq(0, IOADDR(A_ADDR_TRAP_CFG_3)); 321 322 /* Initialize Trace Event 0-7 */ 323 /* when interrupt */ 324 __raw_writeq(M_SCD_TREVT_INTERRUPT, IOADDR(A_SCD_TRACE_EVENT_0)); 325 __raw_writeq(0, IOADDR(A_SCD_TRACE_EVENT_1)); 326 __raw_writeq(0, IOADDR(A_SCD_TRACE_EVENT_2)); 327 __raw_writeq(0, IOADDR(A_SCD_TRACE_EVENT_3)); 328 __raw_writeq(0, IOADDR(A_SCD_TRACE_EVENT_4)); 329 __raw_writeq(0, IOADDR(A_SCD_TRACE_EVENT_5)); 330 __raw_writeq(0, IOADDR(A_SCD_TRACE_EVENT_6)); 331 __raw_writeq(0, IOADDR(A_SCD_TRACE_EVENT_7)); 332 333 /* Initialize Trace Sequence 0-7 */ 334 /* Start on event 0 (interrupt) */ 335 __raw_writeq(V_SCD_TRSEQ_FUNC_START | 0x0fff, 336 IOADDR(A_SCD_TRACE_SEQUENCE_0)); 337 /* dsamp when d used | asamp when a used */ 338 __raw_writeq(M_SCD_TRSEQ_ASAMPLE | M_SCD_TRSEQ_DSAMPLE | 339 K_SCD_TRSEQ_TRIGGER_ALL, 340 IOADDR(A_SCD_TRACE_SEQUENCE_1)); 341 __raw_writeq(0, IOADDR(A_SCD_TRACE_SEQUENCE_2)); 342 __raw_writeq(0, IOADDR(A_SCD_TRACE_SEQUENCE_3)); 343 __raw_writeq(0, IOADDR(A_SCD_TRACE_SEQUENCE_4)); 344 __raw_writeq(0, IOADDR(A_SCD_TRACE_SEQUENCE_5)); 345 __raw_writeq(0, IOADDR(A_SCD_TRACE_SEQUENCE_6)); 346 __raw_writeq(0, IOADDR(A_SCD_TRACE_SEQUENCE_7)); 347 348 /* Now indicate the PERF_CNT interrupt as a trace-relevant interrupt */ 349#if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80) 350 __raw_writeq(1ULL << (K_BCM1480_INT_PERF_CNT & 0x3f), 351 IOADDR(A_BCM1480_IMR_REGISTER(0, R_BCM1480_IMR_INTERRUPT_TRACE_L))); 352#else 353 __raw_writeq(1ULL << K_INT_PERF_CNT, 354 IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_TRACE))); 355#endif 356 arm_tb(); 357 358 pr_debug(DEVNAME ": done starting\n"); 359 360 return 0; 361} 362 363static int sbprof_zbprof_stop(void) 364{ 365 int err = 0; 366 367 pr_debug(DEVNAME ": stopping\n"); 368 369 if (sbp.tb_enable) { 370 /* 371 * XXXKW there is a window here where the intr handler may run, 372 * see the disable, and do the wake_up before this sleep 373 * happens. 374 */ 375 pr_debug(DEVNAME ": wait for disarm\n"); 376 err = wait_event_interruptible(sbp.tb_sync, !sbp.tb_armed); 377 pr_debug(DEVNAME ": disarm complete, stat %d\n", err); 378 379 if (err) 380 return err; 381 382 sbp.tb_enable = 0; 383 free_irq(K_INT_TRACE_FREEZE, &sbp); 384 free_irq(K_INT_PERF_CNT, &sbp); 385 } 386 387 pr_debug(DEVNAME ": done stopping\n"); 388 389 return err; 390} 391 392static int sbprof_tb_open(struct inode *inode, struct file *filp) 393{ 394 int minor; 395 396 minor = iminor(inode); 397 if (minor != 0) 398 return -ENODEV; 399 400 if (xchg(&sbp.open, SB_OPENING) != SB_CLOSED) 401 return -EBUSY; 402 403 memset(&sbp, 0, sizeof(struct sbprof_tb)); 404 sbp.sbprof_tbbuf = vmalloc(MAX_TBSAMPLE_BYTES); 405 if (!sbp.sbprof_tbbuf) { 406 sbp.open = SB_CLOSED; 407 wmb(); 408 return -ENOMEM; 409 } 410 411 memset(sbp.sbprof_tbbuf, 0, MAX_TBSAMPLE_BYTES); 412 init_waitqueue_head(&sbp.tb_sync); 413 init_waitqueue_head(&sbp.tb_read); 414 mutex_init(&sbp.lock); 415 416 sbp.open = SB_OPEN; 417 wmb(); 418 419 return 0; 420} 421 422static int sbprof_tb_release(struct inode *inode, struct file *filp) 423{ 424 int minor; 425 426 minor = iminor(inode); 427 if (minor != 0 || sbp.open != SB_CLOSED) 428 return -ENODEV; 429 430 mutex_lock(&sbp.lock); 431 432 if (sbp.tb_armed || sbp.tb_enable) 433 sbprof_zbprof_stop(); 434 435 vfree(sbp.sbprof_tbbuf); 436 sbp.open = SB_CLOSED; 437 wmb(); 438 439 mutex_unlock(&sbp.lock); 440 441 return 0; 442} 443 444static ssize_t sbprof_tb_read(struct file *filp, char *buf, 445 size_t size, loff_t *offp) 446{ 447 int cur_sample, sample_off, cur_count, sample_left; 448 char *src; 449 int count = 0; 450 char *dest = buf; 451 long cur_off = *offp; 452 453 if (!access_ok(VERIFY_WRITE, buf, size)) 454 return -EFAULT; 455 456 mutex_lock(&sbp.lock); 457 458 count = 0; 459 cur_sample = cur_off / TB_SAMPLE_SIZE; 460 sample_off = cur_off % TB_SAMPLE_SIZE; 461 sample_left = TB_SAMPLE_SIZE - sample_off; 462 463 while (size && (cur_sample < sbp.next_tb_sample)) { 464 int err; 465 466 cur_count = size < sample_left ? size : sample_left; 467 src = (char *)(((long)sbp.sbprof_tbbuf[cur_sample])+sample_off); 468 err = __copy_to_user(dest, src, cur_count); 469 if (err) { 470 *offp = cur_off + cur_count - err; 471 mutex_unlock(&sbp.lock); 472 return err; 473 } 474 pr_debug(DEVNAME ": read from sample %d, %d bytes\n", 475 cur_sample, cur_count); 476 size -= cur_count; 477 sample_left -= cur_count; 478 if (!sample_left) { 479 cur_sample++; 480 sample_off = 0; 481 sample_left = TB_SAMPLE_SIZE; 482 } else { 483 sample_off += cur_count; 484 } 485 cur_off += cur_count; 486 dest += cur_count; 487 count += cur_count; 488 } 489 *offp = cur_off; 490 mutex_unlock(&sbp.lock); 491 492 return count; 493} 494 495static long sbprof_tb_ioctl(struct file *filp, 496 unsigned int command, 497 unsigned long arg) 498{ 499 int err = 0; 500 501 switch (command) { 502 case SBPROF_ZBSTART: 503 mutex_lock(&sbp.lock); 504 err = sbprof_zbprof_start(filp); 505 mutex_unlock(&sbp.lock); 506 break; 507 508 case SBPROF_ZBSTOP: 509 mutex_lock(&sbp.lock); 510 err = sbprof_zbprof_stop(); 511 mutex_unlock(&sbp.lock); 512 break; 513 514 case SBPROF_ZBWAITFULL: { 515 err = wait_event_interruptible(sbp.tb_read, TB_FULL); 516 if (err) 517 break; 518 519 err = put_user(TB_FULL, (int *) arg); 520 break; 521 } 522 523 default: 524 err = -EINVAL; 525 break; 526 } 527 528 return err; 529} 530 531static const struct file_operations sbprof_tb_fops = { 532 .owner = THIS_MODULE, 533 .open = sbprof_tb_open, 534 .release = sbprof_tb_release, 535 .read = sbprof_tb_read, 536 .unlocked_ioctl = sbprof_tb_ioctl, 537 .compat_ioctl = sbprof_tb_ioctl, 538 .mmap = NULL, 539}; 540 541static struct class *tb_class; 542static struct device *tb_dev; 543 544static int __init sbprof_tb_init(void) 545{ 546 struct device *dev; 547 struct class *tbc; 548 int err; 549 550 if (register_chrdev(SBPROF_TB_MAJOR, DEVNAME, &sbprof_tb_fops)) { 551 printk(KERN_WARNING DEVNAME ": initialization failed (dev %d)\n", 552 SBPROF_TB_MAJOR); 553 return -EIO; 554 } 555 556 tbc = class_create(THIS_MODULE, "sb_tracebuffer"); 557 if (IS_ERR(tbc)) { 558 err = PTR_ERR(tbc); 559 goto out_chrdev; 560 } 561 562 tb_class = tbc; 563 564 dev = device_create(tbc, NULL, MKDEV(SBPROF_TB_MAJOR, 0), NULL, "tb"); 565 if (IS_ERR(dev)) { 566 err = PTR_ERR(dev); 567 goto out_class; 568 } 569 tb_dev = dev; 570 571 sbp.open = SB_CLOSED; 572 wmb(); 573 tb_period = zbbus_mhz * 10000LL; 574 pr_info(DEVNAME ": initialized - tb_period = %lld\n", 575 (long long) tb_period); 576 return 0; 577 578out_class: 579 class_destroy(tb_class); 580out_chrdev: 581 unregister_chrdev(SBPROF_TB_MAJOR, DEVNAME); 582 583 return err; 584} 585 586static void __exit sbprof_tb_cleanup(void) 587{ 588 device_destroy(tb_class, MKDEV(SBPROF_TB_MAJOR, 0)); 589 unregister_chrdev(SBPROF_TB_MAJOR, DEVNAME); 590 class_destroy(tb_class); 591} 592 593module_init(sbprof_tb_init); 594module_exit(sbprof_tb_cleanup); 595 596MODULE_ALIAS_CHARDEV_MAJOR(SBPROF_TB_MAJOR); 597MODULE_AUTHOR("Ralf Baechle <ralf@linux-mips.org>"); 598MODULE_LICENSE("GPL"); 599