1#include <linux/compiler.h> 2#include <linux/mm.h> 3#include <linux/signal.h> 4#include <linux/smp.h> 5 6#include <asm/asm.h> 7#include <asm/bootinfo.h> 8#include <asm/byteorder.h> 9#include <asm/cpu.h> 10#include <asm/inst.h> 11#include <asm/processor.h> 12#include <asm/uaccess.h> 13#include <asm/branch.h> 14#include <asm/mipsregs.h> 15#include <asm/system.h> 16#include <asm/cacheflush.h> 17 18#include <asm/fpu_emulator.h> 19 20#include "ieee754.h" 21 22/* Strap kernel emulator for full MIPS IV emulation */ 23 24#ifdef __mips 25#undef __mips 26#endif 27#define __mips 4 28 29/* 30 * Emulate the arbritrary instruction ir at xcp->cp0_epc. Required when 31 * we have to emulate the instruction in a COP1 branch delay slot. Do 32 * not change cp0_epc due to the instruction 33 * 34 * According to the spec: 35 * 1) it shouldnt be a branch :-) 36 * 2) it can be a COP instruction :-( 37 * 3) if we are tring to run a protected memory space we must take 38 * special care on memory access instructions :-( 39 */ 40 41/* 42 * "Trampoline" return routine to catch exception following 43 * execution of delay-slot instruction execution. 44 */ 45 46struct emuframe { 47 mips_instruction emul; 48 mips_instruction badinst; 49 mips_instruction cookie; 50 unsigned long epc; 51}; 52 53int mips_dsemul(struct pt_regs *regs, mips_instruction ir, unsigned long cpc) 54{ 55 extern asmlinkage void handle_dsemulret(void); 56 struct emuframe __user *fr; 57 int err; 58 int nop = 0; 59 60 if (regs->cp0_epc & 1) { 61 if ((ir >> 16) == MM_NOP16) 62 nop = 1; 63 } else if (ir == 0) 64 nop = 1; 65 66 if (nop == 1) { /* a nop is easy */ 67 regs->cp0_epc = cpc; 68 regs->cp0_cause &= ~CAUSEF_BD; 69 return 0; 70 } 71#ifdef DSEMUL_TRACE 72 printk("dsemul %lx %lx\n", regs->cp0_epc, cpc); 73 74#endif 75 76 /* 77 * The strategy is to push the instruction onto the user stack 78 * and put a trap after it which we can catch and jump to 79 * the required address any alternative apart from full 80 * instruction emulation!!. 81 * 82 * Algorithmics used a system call instruction, and 83 * borrowed that vector. MIPS/Linux version is a bit 84 * more heavyweight in the interests of portability and 85 * multiprocessor support. For Linux we generate a 86 * an unaligned access and force an address error exception. 87 * 88 * For embedded systems (stand-alone) we prefer to use a 89 * non-existing CP1 instruction. This prevents us from emulating 90 * branches, but gives us a cleaner interface to the exception 91 * handler (single entry point). 92 */ 93 94 /* Ensure that the two instructions are in the same cache line */ 95 fr = (struct emuframe __user *) 96 ((regs->regs[29] - sizeof(struct emuframe)) & ~0x7); 97 98 /* Verify that the stack pointer is not competely insane */ 99 if (unlikely(!access_ok(VERIFY_WRITE, fr, sizeof(struct emuframe)))) 100 return SIGBUS; 101 102 if (regs->cp0_epc & 1) { 103 err = __put_user(ir >> 16, (u16 __user *)(&fr->emul)); 104 err |= __put_user(ir & 0xffff, (u16 __user *)((long)(&fr->emul) + 2)); 105 err |= __put_user(MM_BREAK_MATH >> 16, (u16 __user *)(&fr->badinst)); 106 err |= __put_user(MM_BREAK_MATH & 0xffff, (u16 __user *)((long)(&fr->badinst) + 2)); 107 } else { 108 err = __put_user(ir, &fr->emul); 109 err |= __put_user((mips_instruction)BREAK_MATH, &fr->badinst); 110 } 111 112 /* NOTE: assume the 2nd instn is never executed => can leave as mips32 instr */ 113 err |= __put_user((mips_instruction)BD_COOKIE, &fr->cookie); 114 err |= __put_user(cpc, &fr->epc); 115 116 if (unlikely(err)) { 117 MIPS_FPU_EMU_INC_STATS(errors); 118 return SIGBUS; 119 } 120 121 regs->cp0_epc = ((unsigned long) &fr->emul) | (regs->cp0_epc & 1); 122 123 flush_cache_sigtramp((unsigned long)&fr->badinst); 124 125 return SIGILL; /* force out of emulation loop */ 126} 127 128int do_dsemulret(struct pt_regs *xcp) 129{ 130 struct emuframe __user *fr; 131 unsigned long epc; 132 u32 insn, cookie; 133 int err = 0; 134 u32 break_math = BREAK_MATH; 135 u16 instr[2]; 136 137 if (xcp->cp0_epc & 1) 138 break_math = MM_BREAK_MATH; 139 140 fr = (struct emuframe __user *) 141 ((xcp->cp0_epc & (~1)) - sizeof(mips_instruction)); 142 143 /* 144 * If we can't even access the area, something is very wrong, but we'll 145 * leave that to the default handling 146 */ 147 if (!access_ok(VERIFY_READ, fr, sizeof(struct emuframe))) 148 return 0; 149 150 /* 151 * Do some sanity checking on the stackframe: 152 * 153 * - Is the instruction pointed to by the EPC an BREAK_MATH? 154 * - Is the following memory word the BD_COOKIE? 155 */ 156 if (xcp->cp0_epc & 1) { 157 err = __get_user(instr[0], (u16 __user *)(&fr->badinst)); 158 err |= __get_user(instr[1], (u16 __user *)((long)(&fr->badinst) + 2)); 159 insn = (instr[0] << 16) | instr[1]; 160 } else 161 err = __get_user(insn, &fr->badinst); 162 err |= __get_user(cookie, &fr->cookie); 163 164 if (unlikely(err || (insn != break_math) || (cookie != BD_COOKIE))) { 165 MIPS_FPU_EMU_INC_STATS(errors); 166 return 0; 167 } 168 169 /* 170 * At this point, we are satisfied that it's a BD emulation trap. Yes, 171 * a user might have deliberately put two malformed and useless 172 * instructions in a row in his program, in which case he's in for a 173 * nasty surprise - the next instruction will be treated as a 174 * continuation address! Alas, this seems to be the only way that we 175 * can handle signals, recursion, and longjmps() in the context of 176 * emulating the branch delay instruction. 177 */ 178 179#ifdef DSEMUL_TRACE 180 printk("dsemulret\n"); 181#endif 182 if (__get_user(epc, &fr->epc)) { /* Saved EPC */ 183 /* This is not a good situation to be in */ 184 force_sig(SIGBUS, current); 185 186 return 0; 187 } 188 189 /* Set EPC to return to post-branch instruction */ 190 xcp->cp0_epc = epc; 191 192 return 1; 193} 194