1 2#include <linux/init.h> 3#include <linux/kernel.h> 4#include <linux/ptrace.h> 5#include <linux/smp.h> 6#include <linux/stddef.h> 7#include <linux/module.h> 8 9#include <asm/bugs.h> 10#include <asm/cpu.h> 11#include <asm/fpu.h> 12#include <asm/mipsregs.h> 13#include <asm/system.h> 14#include <asm/watch.h> 15#include <asm/spram.h> 16/* 17 * Not all of the MIPS CPUs have the "wait" instruction available. Moreover, 18 * the implementation of the "wait" feature differs between CPU families. This 19 * points to the function that implements CPU specific wait. 20 * The wait instruction stops the pipeline and reduces the power consumption of 21 * the CPU very much. 22 */ 23void (*cpu_wait)(void); 24EXPORT_SYMBOL(cpu_wait); 25 26static void r3081_wait(void) 27{ 28 unsigned long cfg = read_c0_conf(); 29 write_c0_conf(cfg | R30XX_CONF_HALT); 30} 31 32static void r39xx_wait(void) 33{ 34 local_irq_disable(); 35 if (!need_resched()) 36 write_c0_conf(read_c0_conf() | TX39_CONF_HALT); 37 local_irq_enable(); 38} 39 40extern void r4k_wait(void); 41 42/* 43 * This variant is preferable as it allows testing need_resched and going to 44 * sleep depending on the outcome atomically. Unfortunately the "It is 45 * implementation-dependent whether the pipeline restarts when a non-enabled 46 * interrupt is requested" restriction in the MIPS32/MIPS64 architecture makes 47 * using this version a gamble. 48 */ 49void r4k_wait_irqoff(void) 50{ 51 local_irq_disable(); 52 if (!need_resched()) 53 __asm__(" .set push \n" 54 " .set mips3 \n" 55 " wait \n" 56 " .set pop \n"); 57 local_irq_enable(); 58 __asm__(" .globl __pastwait \n" 59 "__pastwait: \n"); 60 return; 61} 62 63static void rm7k_wait_irqoff(void) 64{ 65 local_irq_disable(); 66 if (!need_resched()) 67 __asm__( 68 " .set push \n" 69 " .set mips3 \n" 70 " .set noat \n" 71 " mfc0 $1, $12 \n" 72 " sync \n" 73 " mtc0 $1, $12 # stalls until W stage \n" 74 " wait \n" 75 " mtc0 $1, $12 # stalls until W stage \n" 76 " .set pop \n"); 77 local_irq_enable(); 78} 79 80/* 81 * The Au1xxx wait is available only if using 32khz counter or 82 * external timer source, but specifically not CP0 Counter. 83 * alchemy/common/time.c may override cpu_wait! 84 */ 85static void au1k_wait(void) 86{ 87 __asm__(" .set mips3 \n" 88 " cache 0x14, 0(%0) \n" 89 " cache 0x14, 32(%0) \n" 90 " sync \n" 91 " nop \n" 92 " wait \n" 93 " nop \n" 94 " nop \n" 95 " nop \n" 96 " nop \n" 97 " .set mips0 \n" 98 : : "r" (au1k_wait)); 99} 100 101static int __initdata nowait; 102 103static int __init wait_disable(char *s) 104{ 105 nowait = 1; 106 107 return 1; 108} 109 110__setup("nowait", wait_disable); 111 112static int __cpuinitdata mips_fpu_disabled; 113 114static int __init fpu_disable(char *s) 115{ 116 cpu_data[0].options &= ~MIPS_CPU_FPU; 117 mips_fpu_disabled = 1; 118 119 return 1; 120} 121 122__setup("nofpu", fpu_disable); 123 124int __cpuinitdata mips_dsp_disabled; 125 126static int __init dsp_disable(char *s) 127{ 128 cpu_data[0].ases &= ~MIPS_ASE_DSP; 129 mips_dsp_disabled = 1; 130 131 return 1; 132} 133 134__setup("nodsp", dsp_disable); 135 136void __init check_wait(void) 137{ 138 struct cpuinfo_mips *c = ¤t_cpu_data; 139 140 if (nowait) { 141 printk("Wait instruction disabled.\n"); 142 return; 143 } 144 145 switch (c->cputype) { 146 case CPU_R3081: 147 case CPU_R3081E: 148 cpu_wait = r3081_wait; 149 break; 150 case CPU_TX3927: 151 cpu_wait = r39xx_wait; 152 break; 153 case CPU_R4200: 154/* case CPU_R4300: */ 155 case CPU_R4600: 156 case CPU_R4640: 157 case CPU_R4650: 158 case CPU_R4700: 159 case CPU_R5000: 160 case CPU_R5500: 161 case CPU_NEVADA: 162 case CPU_4KC: 163 case CPU_4KEC: 164 case CPU_4KSC: 165 case CPU_5KC: 166 case CPU_25KF: 167 case CPU_PR4450: 168 case CPU_BCM3302: 169 case CPU_BCM6338: 170 case CPU_BCM6348: 171 case CPU_BCM6358: 172 case CPU_CAVIUM_OCTEON: 173 case CPU_CAVIUM_OCTEON_PLUS: 174 case CPU_JZRISC: 175 cpu_wait = r4k_wait; 176 break; 177 178 case CPU_RM7000: 179 cpu_wait = rm7k_wait_irqoff; 180 break; 181 182 case CPU_14K: 183 case CPU_14KE: 184 case CPU_24K: 185 case CPU_34K: 186 case CPU_1004K: 187 cpu_wait = r4k_wait; 188 if (read_c0_config7() & MIPS_CONF7_WII) 189 cpu_wait = r4k_wait_irqoff; 190 break; 191 192 case CPU_1074K: 193 case CPU_74K: 194 cpu_wait = r4k_wait; 195 if ((c->processor_id & 0xff) >= PRID_REV_ENCODE_332(2, 1, 0)) 196 cpu_wait = r4k_wait_irqoff; 197 break; 198 199 case CPU_TX49XX: 200 cpu_wait = r4k_wait_irqoff; 201 break; 202 case CPU_ALCHEMY: 203 cpu_wait = au1k_wait; 204 break; 205 case CPU_20KC: 206 /* 207 * WAIT on Rev1.0 has E1, E2, E3 and E16. 208 * WAIT on Rev2.0 and Rev3.0 has E16. 209 * Rev3.1 WAIT is nop, why bother 210 */ 211 if ((c->processor_id & 0xff) <= 0x64) 212 break; 213 214 /* 215 * Another rev is incremeting c0_count at a reduced clock 216 * rate while in WAIT mode. So we basically have the choice 217 * between using the cp0 timer as clocksource or avoiding 218 * the WAIT instruction. Until more details are known, 219 * disable the use of WAIT for 20Kc entirely. 220 cpu_wait = r4k_wait; 221 */ 222 break; 223 case CPU_RM9000: 224 if ((c->processor_id & 0x00ff) >= 0x40) 225 cpu_wait = r4k_wait; 226 break; 227 default: 228 break; 229 } 230} 231 232static inline void check_errata(void) 233{ 234 struct cpuinfo_mips *c = ¤t_cpu_data; 235 236 switch (c->cputype) { 237 case CPU_34K: 238 /* 239 * Erratum "RPS May Cause Incorrect Instruction Execution" 240 * This code only handles VPE0, any SMP/SMTC/RTOS code 241 * making use of VPE1 will be responsable for that VPE. 242 */ 243 if ((c->processor_id & PRID_REV_MASK) <= PRID_REV_34K_V1_0_2) 244 write_c0_config7(read_c0_config7() | MIPS_CONF7_RPS); 245 break; 246 default: 247 break; 248 } 249} 250 251void __init check_bugs32(void) 252{ 253 check_errata(); 254} 255 256/* 257 * Probe whether cpu has config register by trying to play with 258 * alternate cache bit and see whether it matters. 259 * It's used by cpu_probe to distinguish between R3000A and R3081. 260 */ 261static inline int cpu_has_confreg(void) 262{ 263#ifdef CONFIG_CPU_R3000 264 extern unsigned long r3k_cache_size(unsigned long); 265 unsigned long size1, size2; 266 unsigned long cfg = read_c0_conf(); 267 268 size1 = r3k_cache_size(ST0_ISC); 269 write_c0_conf(cfg ^ R30XX_CONF_AC); 270 size2 = r3k_cache_size(ST0_ISC); 271 write_c0_conf(cfg); 272 return size1 != size2; 273#else 274 return 0; 275#endif 276} 277 278/* 279 * Get the FPU Implementation/Revision. 280 */ 281static inline unsigned long cpu_get_fpu_id(void) 282{ 283 unsigned long tmp, fpu_id; 284 285 tmp = read_c0_status(); 286 __enable_fpu(); 287 fpu_id = read_32bit_cp1_register(CP1_REVISION); 288 write_c0_status(tmp); 289 return fpu_id; 290} 291 292/* 293 * Check the CPU has an FPU the official way. 294 */ 295static inline int __cpu_has_fpu(void) 296{ 297 return ((cpu_get_fpu_id() & 0xff00) != FPIR_IMP_NONE); 298} 299 300static inline void cpu_probe_vmbits(struct cpuinfo_mips *c) 301{ 302#ifdef __NEED_VMBITS_PROBE 303 write_c0_entryhi(0x3fffffffffffe000ULL); 304 back_to_back_c0_hazard(); 305 c->vmbits = fls64(read_c0_entryhi() & 0x3fffffffffffe000ULL); 306#endif 307} 308 309#define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \ 310 | MIPS_CPU_COUNTER) 311 312static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu) 313{ 314 switch (c->processor_id & 0xff00) { 315 case PRID_IMP_R2000: 316 c->cputype = CPU_R2000; 317 __cpu_name[cpu] = "R2000"; 318 c->isa_level = MIPS_CPU_ISA_I; 319 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE | 320 MIPS_CPU_NOFPUEX; 321 if (__cpu_has_fpu()) 322 c->options |= MIPS_CPU_FPU; 323 c->tlbsize = 64; 324 break; 325 case PRID_IMP_R3000: 326 if ((c->processor_id & 0xff) == PRID_REV_R3000A) { 327 if (cpu_has_confreg()) { 328 c->cputype = CPU_R3081E; 329 __cpu_name[cpu] = "R3081"; 330 } else { 331 c->cputype = CPU_R3000A; 332 __cpu_name[cpu] = "R3000A"; 333 } 334 break; 335 } else { 336 c->cputype = CPU_R3000; 337 __cpu_name[cpu] = "R3000"; 338 } 339 c->isa_level = MIPS_CPU_ISA_I; 340 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE | 341 MIPS_CPU_NOFPUEX; 342 if (__cpu_has_fpu()) 343 c->options |= MIPS_CPU_FPU; 344 c->tlbsize = 64; 345 break; 346 case PRID_IMP_R4000: 347 if (read_c0_config() & CONF_SC) { 348 if ((c->processor_id & 0xff) >= PRID_REV_R4400) { 349 c->cputype = CPU_R4400PC; 350 __cpu_name[cpu] = "R4400PC"; 351 } else { 352 c->cputype = CPU_R4000PC; 353 __cpu_name[cpu] = "R4000PC"; 354 } 355 } else { 356 if ((c->processor_id & 0xff) >= PRID_REV_R4400) { 357 c->cputype = CPU_R4400SC; 358 __cpu_name[cpu] = "R4400SC"; 359 } else { 360 c->cputype = CPU_R4000SC; 361 __cpu_name[cpu] = "R4000SC"; 362 } 363 } 364 365 c->isa_level = MIPS_CPU_ISA_III; 366 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 367 MIPS_CPU_WATCH | MIPS_CPU_VCE | 368 MIPS_CPU_LLSC; 369 c->tlbsize = 48; 370 break; 371 case PRID_IMP_VR41XX: 372 switch (c->processor_id & 0xf0) { 373 case PRID_REV_VR4111: 374 c->cputype = CPU_VR4111; 375 __cpu_name[cpu] = "NEC VR4111"; 376 break; 377 case PRID_REV_VR4121: 378 c->cputype = CPU_VR4121; 379 __cpu_name[cpu] = "NEC VR4121"; 380 break; 381 case PRID_REV_VR4122: 382 if ((c->processor_id & 0xf) < 0x3) { 383 c->cputype = CPU_VR4122; 384 __cpu_name[cpu] = "NEC VR4122"; 385 } else { 386 c->cputype = CPU_VR4181A; 387 __cpu_name[cpu] = "NEC VR4181A"; 388 } 389 break; 390 case PRID_REV_VR4130: 391 if ((c->processor_id & 0xf) < 0x4) { 392 c->cputype = CPU_VR4131; 393 __cpu_name[cpu] = "NEC VR4131"; 394 } else { 395 c->cputype = CPU_VR4133; 396 __cpu_name[cpu] = "NEC VR4133"; 397 } 398 break; 399 default: 400 printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n"); 401 c->cputype = CPU_VR41XX; 402 __cpu_name[cpu] = "NEC Vr41xx"; 403 break; 404 } 405 c->isa_level = MIPS_CPU_ISA_III; 406 c->options = R4K_OPTS; 407 c->tlbsize = 32; 408 break; 409 case PRID_IMP_R4300: 410 c->cputype = CPU_R4300; 411 __cpu_name[cpu] = "R4300"; 412 c->isa_level = MIPS_CPU_ISA_III; 413 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 414 MIPS_CPU_LLSC; 415 c->tlbsize = 32; 416 break; 417 case PRID_IMP_R4600: 418 c->cputype = CPU_R4600; 419 __cpu_name[cpu] = "R4600"; 420 c->isa_level = MIPS_CPU_ISA_III; 421 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 422 MIPS_CPU_LLSC; 423 c->tlbsize = 48; 424 break; 425 case PRID_IMP_TX39: 426 c->isa_level = MIPS_CPU_ISA_I; 427 c->options = MIPS_CPU_TLB | MIPS_CPU_TX39_CACHE; 428 429 if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) { 430 c->cputype = CPU_TX3927; 431 __cpu_name[cpu] = "TX3927"; 432 c->tlbsize = 64; 433 } else { 434 switch (c->processor_id & 0xff) { 435 case PRID_REV_TX3912: 436 c->cputype = CPU_TX3912; 437 __cpu_name[cpu] = "TX3912"; 438 c->tlbsize = 32; 439 break; 440 case PRID_REV_TX3922: 441 c->cputype = CPU_TX3922; 442 __cpu_name[cpu] = "TX3922"; 443 c->tlbsize = 64; 444 break; 445 } 446 } 447 break; 448 case PRID_IMP_R4700: 449 c->cputype = CPU_R4700; 450 __cpu_name[cpu] = "R4700"; 451 c->isa_level = MIPS_CPU_ISA_III; 452 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 453 MIPS_CPU_LLSC; 454 c->tlbsize = 48; 455 break; 456 case PRID_IMP_TX49: 457 c->cputype = CPU_TX49XX; 458 __cpu_name[cpu] = "R49XX"; 459 c->isa_level = MIPS_CPU_ISA_III; 460 c->options = R4K_OPTS | MIPS_CPU_LLSC; 461 if (!(c->processor_id & 0x08)) 462 c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR; 463 c->tlbsize = 48; 464 break; 465 case PRID_IMP_R5000: 466 c->cputype = CPU_R5000; 467 __cpu_name[cpu] = "R5000"; 468 c->isa_level = MIPS_CPU_ISA_IV; 469 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 470 MIPS_CPU_LLSC; 471 c->tlbsize = 48; 472 break; 473 case PRID_IMP_R5432: 474 c->cputype = CPU_R5432; 475 __cpu_name[cpu] = "R5432"; 476 c->isa_level = MIPS_CPU_ISA_IV; 477 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 478 MIPS_CPU_WATCH | MIPS_CPU_LLSC; 479 c->tlbsize = 48; 480 break; 481 case PRID_IMP_R5500: 482 c->cputype = CPU_R5500; 483 __cpu_name[cpu] = "R5500"; 484 c->isa_level = MIPS_CPU_ISA_IV; 485 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 486 MIPS_CPU_WATCH | MIPS_CPU_LLSC; 487 c->tlbsize = 48; 488 break; 489 case PRID_IMP_NEVADA: 490 c->cputype = CPU_NEVADA; 491 __cpu_name[cpu] = "Nevada"; 492 c->isa_level = MIPS_CPU_ISA_IV; 493 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 494 MIPS_CPU_DIVEC | MIPS_CPU_LLSC; 495 c->tlbsize = 48; 496 break; 497 case PRID_IMP_R6000: 498 c->cputype = CPU_R6000; 499 __cpu_name[cpu] = "R6000"; 500 c->isa_level = MIPS_CPU_ISA_II; 501 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU | 502 MIPS_CPU_LLSC; 503 c->tlbsize = 32; 504 break; 505 case PRID_IMP_R6000A: 506 c->cputype = CPU_R6000A; 507 __cpu_name[cpu] = "R6000A"; 508 c->isa_level = MIPS_CPU_ISA_II; 509 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU | 510 MIPS_CPU_LLSC; 511 c->tlbsize = 32; 512 break; 513 case PRID_IMP_RM7000: 514 c->cputype = CPU_RM7000; 515 __cpu_name[cpu] = "RM7000"; 516 c->isa_level = MIPS_CPU_ISA_IV; 517 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 518 MIPS_CPU_LLSC; 519 /* 520 * Undocumented RM7000: Bit 29 in the info register of 521 * the RM7000 v2.0 indicates if the TLB has 48 or 64 522 * entries. 523 * 524 * 29 1 => 64 entry JTLB 525 * 0 => 48 entry JTLB 526 */ 527 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48; 528 break; 529 case PRID_IMP_RM9000: 530 c->cputype = CPU_RM9000; 531 __cpu_name[cpu] = "RM9000"; 532 c->isa_level = MIPS_CPU_ISA_IV; 533 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 534 MIPS_CPU_LLSC; 535 /* 536 * Bit 29 in the info register of the RM9000 537 * indicates if the TLB has 48 or 64 entries. 538 * 539 * 29 1 => 64 entry JTLB 540 * 0 => 48 entry JTLB 541 */ 542 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48; 543 break; 544 case PRID_IMP_R8000: 545 c->cputype = CPU_R8000; 546 __cpu_name[cpu] = "RM8000"; 547 c->isa_level = MIPS_CPU_ISA_IV; 548 c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX | 549 MIPS_CPU_FPU | MIPS_CPU_32FPR | 550 MIPS_CPU_LLSC; 551 c->tlbsize = 384; /* has weird TLB: 3-way x 128 */ 552 break; 553 case PRID_IMP_R10000: 554 c->cputype = CPU_R10000; 555 __cpu_name[cpu] = "R10000"; 556 c->isa_level = MIPS_CPU_ISA_IV; 557 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX | 558 MIPS_CPU_FPU | MIPS_CPU_32FPR | 559 MIPS_CPU_COUNTER | MIPS_CPU_WATCH | 560 MIPS_CPU_LLSC; 561 c->tlbsize = 64; 562 break; 563 case PRID_IMP_R12000: 564 c->cputype = CPU_R12000; 565 __cpu_name[cpu] = "R12000"; 566 c->isa_level = MIPS_CPU_ISA_IV; 567 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX | 568 MIPS_CPU_FPU | MIPS_CPU_32FPR | 569 MIPS_CPU_COUNTER | MIPS_CPU_WATCH | 570 MIPS_CPU_LLSC; 571 c->tlbsize = 64; 572 break; 573 case PRID_IMP_R14000: 574 c->cputype = CPU_R14000; 575 __cpu_name[cpu] = "R14000"; 576 c->isa_level = MIPS_CPU_ISA_IV; 577 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX | 578 MIPS_CPU_FPU | MIPS_CPU_32FPR | 579 MIPS_CPU_COUNTER | MIPS_CPU_WATCH | 580 MIPS_CPU_LLSC; 581 c->tlbsize = 64; 582 break; 583 case PRID_IMP_LOONGSON2: 584 c->cputype = CPU_LOONGSON2; 585 __cpu_name[cpu] = "ICT Loongson-2"; 586 c->isa_level = MIPS_CPU_ISA_III; 587 c->options = R4K_OPTS | 588 MIPS_CPU_FPU | MIPS_CPU_LLSC | 589 MIPS_CPU_32FPR; 590 c->tlbsize = 64; 591 break; 592 } 593} 594 595static char unknown_isa[] __cpuinitdata = KERN_ERR \ 596 "Unsupported ISA type, c0.config0: %d."; 597 598static inline unsigned int decode_config0(struct cpuinfo_mips *c) 599{ 600 unsigned int config0; 601 int isa; 602 603 config0 = read_c0_config(); 604 605 if (((config0 & MIPS_CONF_MT) >> 7) == 1) 606 c->options |= MIPS_CPU_TLB; 607 isa = (config0 & MIPS_CONF_AT) >> 13; 608 switch (isa) { 609 case 0: 610 switch ((config0 & MIPS_CONF_AR) >> 10) { 611 case 0: 612 c->isa_level = MIPS_CPU_ISA_M32R1; 613 break; 614 case 1: 615 c->isa_level = MIPS_CPU_ISA_M32R2; 616 break; 617 default: 618 goto unknown; 619 } 620 break; 621 case 2: 622 switch ((config0 & MIPS_CONF_AR) >> 10) { 623 case 0: 624 c->isa_level = MIPS_CPU_ISA_M64R1; 625 break; 626 case 1: 627 c->isa_level = MIPS_CPU_ISA_M64R2; 628 break; 629 default: 630 goto unknown; 631 } 632 break; 633 default: 634 goto unknown; 635 } 636 637 return config0 & MIPS_CONF_M; 638 639unknown: 640 panic(unknown_isa, config0); 641} 642 643static inline unsigned int decode_config1(struct cpuinfo_mips *c) 644{ 645 unsigned int config1; 646 647 config1 = read_c0_config1(); 648 649 if (config1 & MIPS_CONF1_MD) 650 c->ases |= MIPS_ASE_MDMX; 651 if (config1 & MIPS_CONF1_WR) 652 c->options |= MIPS_CPU_WATCH; 653 if (config1 & MIPS_CONF1_CA) 654 c->ases |= MIPS_ASE_MIPS16; 655 if (config1 & MIPS_CONF1_EP) 656 c->options |= MIPS_CPU_EJTAG; 657 if (config1 & MIPS_CONF1_FP) { 658 c->options |= MIPS_CPU_FPU; 659 c->options |= MIPS_CPU_32FPR; 660 } 661 if (cpu_has_tlb) 662 c->tlbsize = ((config1 & MIPS_CONF1_TLBS) >> 25) + 1; 663 664 return config1 & MIPS_CONF_M; 665} 666 667static inline unsigned int decode_config2(struct cpuinfo_mips *c) 668{ 669 unsigned int config2; 670 671 config2 = read_c0_config2(); 672 673 if (config2 & MIPS_CONF2_SL) 674 c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT; 675 676 return config2 & MIPS_CONF_M; 677} 678 679static inline unsigned int decode_config3(struct cpuinfo_mips *c) 680{ 681 unsigned int config3; 682 683 config3 = read_c0_config3(); 684 685 if (config3 & MIPS_CONF3_SM) 686 c->ases |= MIPS_ASE_SMARTMIPS; 687 if (config3 & MIPS_CONF3_DSP) 688 c->ases |= MIPS_ASE_DSP; 689 if (config3 & MIPS_CONF3_VINT) 690 c->options |= MIPS_CPU_VINT; 691 if (config3 & MIPS_CONF3_VEIC) 692 c->options |= MIPS_CPU_VEIC; 693 if (config3 & MIPS_CONF3_MT) 694 c->ases |= MIPS_ASE_MIPSMT; 695 if (config3 & MIPS_CONF3_ULRI) 696 c->options |= MIPS_CPU_ULRI; 697 if (config3 & MIPS_CONF3_CTXTC) 698 c->options |= MIPS_CPU_CTXTC; 699 if (config3 & MIPS_CONF3_ISA) 700 c->options |= MIPS_CPU_MICROMIPS; 701 702 return config3 & MIPS_CONF_M; 703} 704 705static inline unsigned int decode_config4(struct cpuinfo_mips *c) 706{ 707 unsigned int config4; 708 709 config4 = read_c0_config4(); 710 711 if ((config4 & MIPS_CONF4_MMUEXTDEF) == MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT 712 && cpu_has_tlb) 713 c->tlbsize += (config4 & MIPS_CONF4_MMUSIZEEXT) * 0x40; 714 715 c->kscratch_mask = (config4 >> 16) & 0xff; 716 717 return config4 & MIPS_CONF_M; 718} 719 720static void __cpuinit decode_configs(struct cpuinfo_mips *c) 721{ 722 int ok; 723 724 /* MIPS32 or MIPS64 compliant CPU. */ 725 c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER | 726 MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK; 727 728 c->scache.flags = MIPS_CACHE_NOT_PRESENT; 729 730 ok = decode_config0(c); /* Read Config registers. */ 731 BUG_ON(!ok); /* Arch spec violation! */ 732 if (ok) 733 ok = decode_config1(c); 734 if (ok) 735 ok = decode_config2(c); 736 if (ok) 737 ok = decode_config3(c); 738 if (ok) 739 ok = decode_config4(c); 740 741 mips_probe_watch_registers(c); 742 743 if (cpu_has_mips_r2) 744 c->core = read_c0_ebase() & 0x3ff; 745} 746 747static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu) 748{ 749 decode_configs(c); 750 switch (c->processor_id & 0xff00) { 751 case PRID_IMP_4KC: 752 c->cputype = CPU_4KC; 753 __cpu_name[cpu] = "MIPS 4Kc"; 754 break; 755 case PRID_IMP_4KEC: 756 case PRID_IMP_4KECR2: 757 c->cputype = CPU_4KEC; 758 __cpu_name[cpu] = "MIPS 4KEc"; 759 break; 760 case PRID_IMP_4KSC: 761 case PRID_IMP_4KSD: 762 c->cputype = CPU_4KSC; 763 __cpu_name[cpu] = "MIPS 4KSc"; 764 break; 765 case PRID_IMP_5KC: 766 c->cputype = CPU_5KC; 767 __cpu_name[cpu] = "MIPS 5Kc"; 768 break; 769 case PRID_IMP_5KE: 770 c->cputype = CPU_5KE; 771 __cpu_name[cpu] = "MIPS 5KE"; 772 break; 773 case PRID_IMP_20KC: 774 c->cputype = CPU_20KC; 775 __cpu_name[cpu] = "MIPS 20Kc"; 776 break; 777 case PRID_IMP_24K: 778 case PRID_IMP_24KE: 779 c->cputype = CPU_24K; 780 __cpu_name[cpu] = "MIPS 24Kc"; 781 break; 782 case PRID_IMP_25KF: 783 c->cputype = CPU_25KF; 784 __cpu_name[cpu] = "MIPS 25Kc"; 785 break; 786 case PRID_IMP_34K: 787 c->cputype = CPU_34K; 788 __cpu_name[cpu] = "MIPS 34Kc"; 789 break; 790 case PRID_IMP_74K: 791 c->cputype = CPU_74K; 792 __cpu_name[cpu] = "MIPS 74Kc"; 793 break; 794 case PRID_IMP_14K: 795 c->cputype = CPU_14K; 796 __cpu_name[cpu] = "MIPS 14Kc"; 797 break; 798 case PRID_IMP_14KE: 799 c->cputype = CPU_14KE; 800 __cpu_name[cpu] = "MIPS 14KEc"; 801 break; 802 case PRID_IMP_1004K: 803 c->cputype = CPU_1004K; 804 __cpu_name[cpu] = "MIPS 1004Kc"; 805 break; 806 case PRID_IMP_1074K: 807 c->cputype = CPU_1074K; 808 __cpu_name[cpu] = "MIPS 1074Kc"; 809 break; 810 } 811 812 spram_config(); 813} 814 815static inline void cpu_probe_alchemy(struct cpuinfo_mips *c, unsigned int cpu) 816{ 817 decode_configs(c); 818 switch (c->processor_id & 0xff00) { 819 case PRID_IMP_AU1_REV1: 820 case PRID_IMP_AU1_REV2: 821 c->cputype = CPU_ALCHEMY; 822 switch ((c->processor_id >> 24) & 0xff) { 823 case 0: 824 __cpu_name[cpu] = "Au1000"; 825 break; 826 case 1: 827 __cpu_name[cpu] = "Au1500"; 828 break; 829 case 2: 830 __cpu_name[cpu] = "Au1100"; 831 break; 832 case 3: 833 __cpu_name[cpu] = "Au1550"; 834 break; 835 case 4: 836 __cpu_name[cpu] = "Au1200"; 837 if ((c->processor_id & 0xff) == 2) 838 __cpu_name[cpu] = "Au1250"; 839 break; 840 case 5: 841 __cpu_name[cpu] = "Au1210"; 842 break; 843 default: 844 __cpu_name[cpu] = "Au1xxx"; 845 break; 846 } 847 break; 848 } 849} 850 851static inline void cpu_probe_sibyte(struct cpuinfo_mips *c, unsigned int cpu) 852{ 853 decode_configs(c); 854 855 switch (c->processor_id & 0xff00) { 856 case PRID_IMP_SB1: 857 c->cputype = CPU_SB1; 858 __cpu_name[cpu] = "SiByte SB1"; 859 /* FPU in pass1 is known to have issues. */ 860 if ((c->processor_id & 0xff) < 0x02) 861 c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR); 862 break; 863 case PRID_IMP_SB1A: 864 c->cputype = CPU_SB1A; 865 __cpu_name[cpu] = "SiByte SB1A"; 866 break; 867 } 868} 869 870static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c, unsigned int cpu) 871{ 872 decode_configs(c); 873 switch (c->processor_id & 0xff00) { 874 case PRID_IMP_SR71000: 875 c->cputype = CPU_SR71000; 876 __cpu_name[cpu] = "Sandcraft SR71000"; 877 c->scache.ways = 8; 878 c->tlbsize = 64; 879 break; 880 } 881} 882 883static inline void cpu_probe_nxp(struct cpuinfo_mips *c, unsigned int cpu) 884{ 885 decode_configs(c); 886 switch (c->processor_id & 0xff00) { 887 case PRID_IMP_PR4450: 888 c->cputype = CPU_PR4450; 889 __cpu_name[cpu] = "Philips PR4450"; 890 c->isa_level = MIPS_CPU_ISA_M32R1; 891 break; 892 } 893} 894 895static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu) 896{ 897 decode_configs(c); 898 switch (c->processor_id & 0xff00) { 899 case PRID_IMP_BCM3302: 900 /* same as PRID_IMP_BCM6338 */ 901 c->cputype = CPU_BCM3302; 902 __cpu_name[cpu] = "Broadcom BCM3302"; 903 break; 904 case PRID_IMP_BCM4710: 905 c->cputype = CPU_BCM4710; 906 __cpu_name[cpu] = "Broadcom BCM4710"; 907 break; 908 case PRID_IMP_BCM6345: 909 c->cputype = CPU_BCM6345; 910 __cpu_name[cpu] = "Broadcom BCM6345"; 911 break; 912 case PRID_IMP_BCM6348: 913 c->cputype = CPU_BCM6348; 914 __cpu_name[cpu] = "Broadcom BCM6348"; 915 break; 916 case PRID_IMP_BCM4350: 917 switch (c->processor_id & 0xf0) { 918 case PRID_REV_BCM6358: 919 c->cputype = CPU_BCM6358; 920 __cpu_name[cpu] = "Broadcom BCM6358"; 921 break; 922 default: 923 c->cputype = CPU_UNKNOWN; 924 break; 925 } 926 break; 927 } 928} 929 930static inline void cpu_probe_cavium(struct cpuinfo_mips *c, unsigned int cpu) 931{ 932 decode_configs(c); 933 switch (c->processor_id & 0xff00) { 934 case PRID_IMP_CAVIUM_CN38XX: 935 case PRID_IMP_CAVIUM_CN31XX: 936 case PRID_IMP_CAVIUM_CN30XX: 937 c->cputype = CPU_CAVIUM_OCTEON; 938 __cpu_name[cpu] = "Cavium Octeon"; 939 goto platform; 940 case PRID_IMP_CAVIUM_CN58XX: 941 case PRID_IMP_CAVIUM_CN56XX: 942 case PRID_IMP_CAVIUM_CN50XX: 943 case PRID_IMP_CAVIUM_CN52XX: 944 c->cputype = CPU_CAVIUM_OCTEON_PLUS; 945 __cpu_name[cpu] = "Cavium Octeon+"; 946platform: 947 if (cpu == 0) 948 __elf_platform = "octeon"; 949 break; 950 default: 951 printk(KERN_INFO "Unknown Octeon chip!\n"); 952 c->cputype = CPU_UNKNOWN; 953 break; 954 } 955} 956 957static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu) 958{ 959 decode_configs(c); 960 /* JZRISC does not implement the CP0 counter. */ 961 c->options &= ~MIPS_CPU_COUNTER; 962 switch (c->processor_id & 0xff00) { 963 case PRID_IMP_JZRISC: 964 c->cputype = CPU_JZRISC; 965 __cpu_name[cpu] = "Ingenic JZRISC"; 966 break; 967 default: 968 panic("Unknown Ingenic Processor ID!"); 969 break; 970 } 971} 972 973const char *__cpu_name[NR_CPUS]; 974const char *__elf_platform; 975 976__cpuinit void cpu_probe(void) 977{ 978 struct cpuinfo_mips *c = ¤t_cpu_data; 979 unsigned int cpu = smp_processor_id(); 980 981 c->processor_id = PRID_IMP_UNKNOWN; 982 c->fpu_id = FPIR_IMP_NONE; 983 c->cputype = CPU_UNKNOWN; 984 985 c->processor_id = read_c0_prid(); 986 switch (c->processor_id & 0xff0000) { 987 case PRID_COMP_LEGACY: 988 cpu_probe_legacy(c, cpu); 989 break; 990 case PRID_COMP_MIPS: 991 cpu_probe_mips(c, cpu); 992 break; 993 case PRID_COMP_ALCHEMY: 994 cpu_probe_alchemy(c, cpu); 995 break; 996 case PRID_COMP_SIBYTE: 997 cpu_probe_sibyte(c, cpu); 998 break; 999 case PRID_COMP_BROADCOM: 1000 cpu_probe_broadcom(c, cpu); 1001 break; 1002 case PRID_COMP_SANDCRAFT: 1003 cpu_probe_sandcraft(c, cpu); 1004 break; 1005 case PRID_COMP_NXP: 1006 cpu_probe_nxp(c, cpu); 1007 break; 1008 case PRID_COMP_CAVIUM: 1009 cpu_probe_cavium(c, cpu); 1010 break; 1011 case PRID_COMP_INGENIC: 1012 cpu_probe_ingenic(c, cpu); 1013 break; 1014 } 1015 1016 BUG_ON(!__cpu_name[cpu]); 1017 BUG_ON(c->cputype == CPU_UNKNOWN); 1018 1019 /* 1020 * Platform code can force the cpu type to optimize code 1021 * generation. In that case be sure the cpu type is correctly 1022 * manually setup otherwise it could trigger some nasty bugs. 1023 */ 1024 BUG_ON(current_cpu_type() != c->cputype); 1025 1026 if (mips_fpu_disabled) 1027 c->options &= ~MIPS_CPU_FPU; 1028 1029 if (mips_dsp_disabled) 1030 c->ases &= ~MIPS_ASE_DSP; 1031 1032 if (c->options & MIPS_CPU_FPU) { 1033 c->fpu_id = cpu_get_fpu_id(); 1034 1035 if (c->isa_level == MIPS_CPU_ISA_M32R1 || 1036 c->isa_level == MIPS_CPU_ISA_M32R2 || 1037 c->isa_level == MIPS_CPU_ISA_M64R1 || 1038 c->isa_level == MIPS_CPU_ISA_M64R2) { 1039 if (c->fpu_id & MIPS_FPIR_3D) 1040 c->ases |= MIPS_ASE_MIPS3D; 1041 } 1042 } 1043 1044 if (cpu_has_mips_r2) 1045 c->srsets = ((read_c0_srsctl() >> 26) & 0x0f) + 1; 1046 else 1047 c->srsets = 1; 1048 1049 cpu_probe_vmbits(c); 1050} 1051 1052__cpuinit void cpu_report(void) 1053{ 1054 struct cpuinfo_mips *c = ¤t_cpu_data; 1055 1056 printk(KERN_INFO "CPU revision is: %08x (%s)\n", 1057 c->processor_id, cpu_name_string()); 1058 if (c->options & MIPS_CPU_FPU) 1059 printk(KERN_INFO "FPU revision is: %08x\n", c->fpu_id); 1060} 1061