1/* 2 * Copyright (C) 2000,2001,2004 Broadcom Corporation 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License 6 * as published by the Free Software Foundation; either version 2 7 * of the License, or (at your option) any later version. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, write to the Free Software 16 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. 17 */ 18#include <linux/clockchips.h> 19#include <linux/interrupt.h> 20#include <linux/percpu.h> 21#include <linux/smp.h> 22 23#include <asm/addrspace.h> 24#include <asm/io.h> 25#include <asm/time.h> 26 27#include <asm/sibyte/bcm1480_regs.h> 28#include <asm/sibyte/sb1250_regs.h> 29#include <asm/sibyte/bcm1480_int.h> 30#include <asm/sibyte/bcm1480_scd.h> 31 32#include <asm/sibyte/sb1250.h> 33 34#define IMR_IP2_VAL K_BCM1480_INT_MAP_I0 35#define IMR_IP3_VAL K_BCM1480_INT_MAP_I1 36#define IMR_IP4_VAL K_BCM1480_INT_MAP_I2 37 38/* 39 * The general purpose timer ticks at 1MHz independent if 40 * the rest of the system 41 */ 42static void sibyte_set_mode(enum clock_event_mode mode, 43 struct clock_event_device *evt) 44{ 45 unsigned int cpu = smp_processor_id(); 46 void __iomem *cfg, *init; 47 48 cfg = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG)); 49 init = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_INIT)); 50 51 switch (mode) { 52 case CLOCK_EVT_MODE_PERIODIC: 53 __raw_writeq(0, cfg); 54 __raw_writeq((V_SCD_TIMER_FREQ / HZ) - 1, init); 55 __raw_writeq(M_SCD_TIMER_ENABLE | M_SCD_TIMER_MODE_CONTINUOUS, 56 cfg); 57 break; 58 59 case CLOCK_EVT_MODE_ONESHOT: 60 /* Stop the timer until we actually program a shot */ 61 case CLOCK_EVT_MODE_SHUTDOWN: 62 __raw_writeq(0, cfg); 63 break; 64 65 case CLOCK_EVT_MODE_UNUSED: /* shuddup gcc */ 66 case CLOCK_EVT_MODE_RESUME: 67 ; 68 } 69} 70 71static int sibyte_next_event(unsigned long delta, struct clock_event_device *cd) 72{ 73 unsigned int cpu = smp_processor_id(); 74 void __iomem *cfg, *init; 75 76 cfg = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG)); 77 init = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_INIT)); 78 79 __raw_writeq(0, cfg); 80 __raw_writeq(delta - 1, init); 81 __raw_writeq(M_SCD_TIMER_ENABLE, cfg); 82 83 return 0; 84} 85 86static irqreturn_t sibyte_counter_handler(int irq, void *dev_id) 87{ 88 unsigned int cpu = smp_processor_id(); 89 struct clock_event_device *cd = dev_id; 90 void __iomem *cfg; 91 unsigned long tmode; 92 93 if (cd->mode == CLOCK_EVT_MODE_PERIODIC) 94 tmode = M_SCD_TIMER_ENABLE | M_SCD_TIMER_MODE_CONTINUOUS; 95 else 96 tmode = 0; 97 98 /* ACK interrupt */ 99 cfg = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG)); 100 ____raw_writeq(tmode, cfg); 101 102 cd->event_handler(cd); 103 104 return IRQ_HANDLED; 105} 106 107static DEFINE_PER_CPU(struct clock_event_device, sibyte_hpt_clockevent); 108static DEFINE_PER_CPU(struct irqaction, sibyte_hpt_irqaction); 109static DEFINE_PER_CPU(char [18], sibyte_hpt_name); 110 111void __cpuinit sb1480_clockevent_init(void) 112{ 113 unsigned int cpu = smp_processor_id(); 114 unsigned int irq = K_BCM1480_INT_TIMER_0 + cpu; 115 struct irqaction *action = &per_cpu(sibyte_hpt_irqaction, cpu); 116 struct clock_event_device *cd = &per_cpu(sibyte_hpt_clockevent, cpu); 117 unsigned char *name = per_cpu(sibyte_hpt_name, cpu); 118 119 BUG_ON(cpu > 3); /* Only have 4 general purpose timers */ 120 121 sprintf(name, "bcm1480-counter-%d", cpu); 122 cd->name = name; 123 cd->features = CLOCK_EVT_FEAT_PERIODIC | 124 CLOCK_EVT_FEAT_ONESHOT; 125 clockevent_set_clock(cd, V_SCD_TIMER_FREQ); 126 cd->max_delta_ns = clockevent_delta2ns(0x7fffff, cd); 127 cd->min_delta_ns = clockevent_delta2ns(2, cd); 128 cd->rating = 200; 129 cd->irq = irq; 130 cd->cpumask = cpumask_of(cpu); 131 cd->set_next_event = sibyte_next_event; 132 cd->set_mode = sibyte_set_mode; 133 clockevents_register_device(cd); 134 135 bcm1480_mask_irq(cpu, irq); 136 137 /* 138 * Map the timer interrupt to IP[4] of this cpu 139 */ 140 __raw_writeq(IMR_IP4_VAL, 141 IOADDR(A_BCM1480_IMR_REGISTER(cpu, 142 R_BCM1480_IMR_INTERRUPT_MAP_BASE_H) + (irq << 3))); 143 144 bcm1480_unmask_irq(cpu, irq); 145 146 action->handler = sibyte_counter_handler; 147 action->flags = IRQF_DISABLED | IRQF_PERCPU | IRQF_TIMER; 148 action->name = name; 149 action->dev_id = cd; 150 151 irq_set_affinity(irq, cpumask_of(cpu)); 152 setup_irq(irq, action); 153} 154