1/* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Copyright (C) 1994, 95, 96, 99, 2001 Ralf Baechle 7 * Copyright (C) 1994, 1995, 1996 Paul M. Antoine. 8 * Copyright (C) 1999 Silicon Graphics, Inc. 9 * Copyright (C) 2007 Maciej W. Rozycki 10 */ 11#ifndef _ASM_STACKFRAME_H 12#define _ASM_STACKFRAME_H 13 14#include <linux/threads.h> 15 16#include <asm/asm.h> 17#include <asm/asmmacro.h> 18#include <asm/mipsregs.h> 19#include <asm/asm-offsets.h> 20 21/* 22 * For SMTC kernel, global IE should be left set, and interrupts 23 * controlled exclusively via IXMT. 24 */ 25#ifdef CONFIG_MIPS_MT_SMTC 26#define STATMASK 0x1e 27#elif defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX) 28#define STATMASK 0x3f 29#else 30#define STATMASK 0x1f 31#endif 32 33#ifdef CONFIG_MIPS_MT_SMTC 34#include <asm/mipsmtregs.h> 35#endif /* CONFIG_MIPS_MT_SMTC */ 36 37 .macro SAVE_AT 38 .set push 39 .set noat 40 LONG_S $1, PT_R1(sp) 41 .set pop 42 .endm 43 44 .macro SAVE_TEMP 45#ifdef CONFIG_CPU_HAS_SMARTMIPS 46 mflhxu v1 47 LONG_S v1, PT_LO(sp) 48 mflhxu v1 49 LONG_S v1, PT_HI(sp) 50 mflhxu v1 51 LONG_S v1, PT_ACX(sp) 52#else 53 mfhi v1 54#endif 55#ifdef CONFIG_32BIT 56 LONG_S $8, PT_R8(sp) 57 LONG_S $9, PT_R9(sp) 58#endif 59 LONG_S $10, PT_R10(sp) 60 LONG_S $11, PT_R11(sp) 61 LONG_S $12, PT_R12(sp) 62#ifndef CONFIG_CPU_HAS_SMARTMIPS 63 LONG_S v1, PT_HI(sp) 64 mflo v1 65#endif 66 LONG_S $13, PT_R13(sp) 67 LONG_S $14, PT_R14(sp) 68 LONG_S $15, PT_R15(sp) 69 LONG_S $24, PT_R24(sp) 70#ifndef CONFIG_CPU_HAS_SMARTMIPS 71 LONG_S v1, PT_LO(sp) 72#endif 73 .endm 74 75 .macro SAVE_STATIC 76 LONG_S $16, PT_R16(sp) 77 LONG_S $17, PT_R17(sp) 78 LONG_S $18, PT_R18(sp) 79 LONG_S $19, PT_R19(sp) 80 LONG_S $20, PT_R20(sp) 81 LONG_S $21, PT_R21(sp) 82 LONG_S $22, PT_R22(sp) 83 LONG_S $23, PT_R23(sp) 84 LONG_S $30, PT_R30(sp) 85 .endm 86 87#ifdef CONFIG_SMP 88#ifdef CONFIG_MIPS_MT_SMTC 89#define PTEBASE_SHIFT 19 /* TCBIND */ 90#define CPU_ID_REG CP0_TCBIND 91#define CPU_ID_MFC0 mfc0 92#elif defined(CONFIG_MIPS_PGD_C0_CONTEXT) 93#define PTEBASE_SHIFT 48 /* XCONTEXT */ 94#define CPU_ID_REG CP0_XCONTEXT 95#define CPU_ID_MFC0 MFC0 96#else 97#define PTEBASE_SHIFT 23 /* CONTEXT */ 98#define CPU_ID_REG CP0_CONTEXT 99#define CPU_ID_MFC0 MFC0 100#endif 101 .macro get_saved_sp /* SMP variation */ 102 CPU_ID_MFC0 k0, CPU_ID_REG 103#if defined(CONFIG_32BIT) || defined(KBUILD_64BIT_SYM32) 104 lui k1, %hi(kernelsp) 105#else 106 lui k1, %highest(kernelsp) 107 daddiu k1, %higher(kernelsp) 108 dsll k1, 16 109 daddiu k1, %hi(kernelsp) 110 dsll k1, 16 111#endif 112 LONG_SRL k0, PTEBASE_SHIFT 113 LONG_ADDU k1, k0 114 LONG_L k1, %lo(kernelsp)(k1) 115 .endm 116 117 .macro set_saved_sp stackp temp temp2 118 CPU_ID_MFC0 \temp, CPU_ID_REG 119 LONG_SRL \temp, PTEBASE_SHIFT 120 LONG_S \stackp, kernelsp(\temp) 121 .endm 122#else 123 .macro get_saved_sp /* Uniprocessor variation */ 124#ifdef CONFIG_CPU_JUMP_WORKAROUNDS 125 move k0, ra 126 jal 1f 127 nop 1281: jal 1f 129 nop 1301: jal 1f 131 nop 1321: jal 1f 133 nop 1341: move ra, k0 135 li k0, 3 136 mtc0 k0, $22 137#endif /* CONFIG_CPU_JUMP_WORKAROUNDS */ 138#if defined(CONFIG_32BIT) || defined(KBUILD_64BIT_SYM32) 139 lui k1, %hi(kernelsp) 140#else 141 lui k1, %highest(kernelsp) 142 daddiu k1, %higher(kernelsp) 143 dsll k1, k1, 16 144 daddiu k1, %hi(kernelsp) 145 dsll k1, k1, 16 146#endif 147 LONG_L k1, %lo(kernelsp)(k1) 148 .endm 149 150 .macro set_saved_sp stackp temp temp2 151 LONG_S \stackp, kernelsp 152 .endm 153#endif 154 155 .macro SAVE_SOME 156 .set push 157 .set noat 158 .set reorder 159 mfc0 k0, CP0_STATUS 160 sll k0, 3 /* extract cu0 bit */ 161 .set noreorder 162 bltz k0, 8f 163 move k1, sp 164 .set reorder 165 /* Called from user mode, new stack. */ 166 get_saved_sp 167#ifndef CONFIG_CPU_DADDI_WORKAROUNDS 1688: move k0, sp 169 PTR_SUBU sp, k1, PT_SIZE 170#else 171 .set at=k0 1728: PTR_SUBU k1, PT_SIZE 173 .set noat 174 move k0, sp 175 move sp, k1 176#endif 177 LONG_S k0, PT_R29(sp) 178 LONG_S $3, PT_R3(sp) 179 /* 180 * You might think that you don't need to save $0, 181 * but the FPU emulator and gdb remote debug stub 182 * need it to operate correctly 183 */ 184 LONG_S $0, PT_R0(sp) 185 mfc0 v1, CP0_STATUS 186 LONG_S $2, PT_R2(sp) 187 LONG_S v1, PT_STATUS(sp) 188#ifdef CONFIG_MIPS_MT_SMTC 189 /* 190 * Ideally, these instructions would be shuffled in 191 * to cover the pipeline delay. 192 */ 193 .set mips32 194 mfc0 v1, CP0_TCSTATUS 195 .set mips0 196 LONG_S v1, PT_TCSTATUS(sp) 197#endif /* CONFIG_MIPS_MT_SMTC */ 198 LONG_S $4, PT_R4(sp) 199 mfc0 v1, CP0_CAUSE 200 LONG_S $5, PT_R5(sp) 201 LONG_S v1, PT_CAUSE(sp) 202 LONG_S $6, PT_R6(sp) 203 MFC0 v1, CP0_EPC 204 LONG_S $7, PT_R7(sp) 205#ifdef CONFIG_64BIT 206 LONG_S $8, PT_R8(sp) 207 LONG_S $9, PT_R9(sp) 208#endif 209 LONG_S v1, PT_EPC(sp) 210 LONG_S $25, PT_R25(sp) 211 LONG_S $28, PT_R28(sp) 212 LONG_S $31, PT_R31(sp) 213 ori $28, sp, _THREAD_MASK 214 xori $28, _THREAD_MASK 215#ifdef CONFIG_CPU_CAVIUM_OCTEON 216 .set mips64 217 pref 0, 0($28) /* Prefetch the current pointer */ 218 pref 0, PT_R31(sp) /* Prefetch the $31(ra) */ 219 /* The Octeon multiplier state is affected by general multiply 220 instructions. It must be saved before and kernel code might 221 corrupt it */ 222 jal octeon_mult_save 223 LONG_L v1, 0($28) /* Load the current pointer */ 224 /* Restore $31(ra) that was changed by the jal */ 225 LONG_L ra, PT_R31(sp) 226 pref 0, 0(v1) /* Prefetch the current thread */ 227#endif 228 .set pop 229 .endm 230 231 .macro SAVE_ALL 232 SAVE_SOME 233 SAVE_AT 234 SAVE_TEMP 235 SAVE_STATIC 236 .endm 237 238 .macro RESTORE_AT 239 .set push 240 .set noat 241 LONG_L $1, PT_R1(sp) 242 .set pop 243 .endm 244 245 .macro RESTORE_TEMP 246#ifdef CONFIG_CPU_HAS_SMARTMIPS 247 LONG_L $24, PT_ACX(sp) 248 mtlhx $24 249 LONG_L $24, PT_HI(sp) 250 mtlhx $24 251 LONG_L $24, PT_LO(sp) 252 mtlhx $24 253#else 254 LONG_L $24, PT_LO(sp) 255 mtlo $24 256 LONG_L $24, PT_HI(sp) 257 mthi $24 258#endif 259#ifdef CONFIG_32BIT 260 LONG_L $8, PT_R8(sp) 261 LONG_L $9, PT_R9(sp) 262#endif 263 LONG_L $10, PT_R10(sp) 264 LONG_L $11, PT_R11(sp) 265 LONG_L $12, PT_R12(sp) 266 LONG_L $13, PT_R13(sp) 267 LONG_L $14, PT_R14(sp) 268 LONG_L $15, PT_R15(sp) 269 LONG_L $24, PT_R24(sp) 270 .endm 271 272 .macro RESTORE_STATIC 273 LONG_L $16, PT_R16(sp) 274 LONG_L $17, PT_R17(sp) 275 LONG_L $18, PT_R18(sp) 276 LONG_L $19, PT_R19(sp) 277 LONG_L $20, PT_R20(sp) 278 LONG_L $21, PT_R21(sp) 279 LONG_L $22, PT_R22(sp) 280 LONG_L $23, PT_R23(sp) 281 LONG_L $30, PT_R30(sp) 282 .endm 283 284#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX) 285 286 .macro RESTORE_SOME 287 .set push 288 .set reorder 289 .set noat 290 mfc0 a0, CP0_STATUS 291 li v1, 0xff00 292 ori a0, STATMASK 293 xori a0, STATMASK 294 mtc0 a0, CP0_STATUS 295 and a0, v1 296 LONG_L v0, PT_STATUS(sp) 297 nor v1, $0, v1 298 and v0, v1 299 or v0, a0 300 mtc0 v0, CP0_STATUS 301 LONG_L $31, PT_R31(sp) 302 LONG_L $28, PT_R28(sp) 303 LONG_L $25, PT_R25(sp) 304 LONG_L $7, PT_R7(sp) 305 LONG_L $6, PT_R6(sp) 306 LONG_L $5, PT_R5(sp) 307 LONG_L $4, PT_R4(sp) 308 LONG_L $3, PT_R3(sp) 309 LONG_L $2, PT_R2(sp) 310 .set pop 311 .endm 312 313 .macro RESTORE_SP_AND_RET 314 .set push 315 .set noreorder 316 LONG_L k0, PT_EPC(sp) 317 LONG_L sp, PT_R29(sp) 318 jr k0 319 rfe 320 .set pop 321 .endm 322 323#else 324 .macro RESTORE_SOME 325 .set push 326 .set reorder 327 .set noat 328#ifdef CONFIG_MIPS_MT_SMTC 329 .set mips32r2 330 /* 331 * We need to make sure the read-modify-write 332 * of Status below isn't perturbed by an interrupt 333 * or cross-TC access, so we need to do at least a DMT, 334 * protected by an interrupt-inhibit. But setting IXMT 335 * also creates a few-cycle window where an IPI could 336 * be queued and not be detected before potentially 337 * returning to a WAIT or user-mode loop. It must be 338 * replayed. 339 * 340 * We're in the middle of a context switch, and 341 * we can't dispatch it directly without trashing 342 * some registers, so we'll try to detect this unlikely 343 * case and program a software interrupt in the VPE, 344 * as would be done for a cross-VPE IPI. To accomodate 345 * the handling of that case, we're doing a DVPE instead 346 * of just a DMT here to protect against other threads. 347 * This is a lot of cruft to cover a tiny window. 348 * If you can find a better design, implement it! 349 * 350 */ 351 mfc0 v0, CP0_TCSTATUS 352 ori v0, TCSTATUS_IXMT 353 mtc0 v0, CP0_TCSTATUS 354 _ehb 355 DVPE 5 # dvpe a1 356 jal mips_ihb 357#endif /* CONFIG_MIPS_MT_SMTC */ 358#ifdef CONFIG_CPU_CAVIUM_OCTEON 359 /* Restore the Octeon multiplier state */ 360 jal octeon_mult_restore 361#endif 362 mfc0 a0, CP0_STATUS 363 ori a0, STATMASK 364 xori a0, STATMASK 365 mtc0 a0, CP0_STATUS 366 li v1, 0xff00 367 and a0, v1 368 LONG_L v0, PT_STATUS(sp) 369 nor v1, $0, v1 370 and v0, v1 371 or v0, a0 372 mtc0 v0, CP0_STATUS 373#ifdef CONFIG_MIPS_MT_SMTC 374/* 375 * Only after EXL/ERL have been restored to status can we 376 * restore TCStatus.IXMT. 377 */ 378 LONG_L v1, PT_TCSTATUS(sp) 379 _ehb 380 mfc0 a0, CP0_TCSTATUS 381 andi v1, TCSTATUS_IXMT 382 bnez v1, 0f 383 384/* 385 * We'd like to detect any IPIs queued in the tiny window 386 * above and request an software interrupt to service them 387 * when we ERET. 388 * 389 * Computing the offset into the IPIQ array of the executing 390 * TC's IPI queue in-line would be tedious. We use part of 391 * the TCContext register to hold 16 bits of offset that we 392 * can add in-line to find the queue head. 393 */ 394 mfc0 v0, CP0_TCCONTEXT 395 la a2, IPIQ 396 srl v0, v0, 16 397 addu a2, a2, v0 398 LONG_L v0, 0(a2) 399 beqz v0, 0f 400/* 401 * If we have a queue, provoke dispatch within the VPE by setting C_SW1 402 */ 403 mfc0 v0, CP0_CAUSE 404 ori v0, v0, C_SW1 405 mtc0 v0, CP0_CAUSE 4060: 407 /* 408 * This test should really never branch but 409 * let's be prudent here. Having atomized 410 * the shared register modifications, we can 411 * now EVPE, and must do so before interrupts 412 * are potentially re-enabled. 413 */ 414 andi a1, a1, MVPCONTROL_EVP 415 beqz a1, 1f 416 evpe 4171: 418 /* We know that TCStatua.IXMT should be set from above */ 419 xori a0, a0, TCSTATUS_IXMT 420 or a0, a0, v1 421 mtc0 a0, CP0_TCSTATUS 422 _ehb 423 424 .set mips0 425#endif /* CONFIG_MIPS_MT_SMTC */ 426 LONG_L v1, PT_EPC(sp) 427 MTC0 v1, CP0_EPC 428 LONG_L $31, PT_R31(sp) 429 LONG_L $28, PT_R28(sp) 430 LONG_L $25, PT_R25(sp) 431#ifdef CONFIG_64BIT 432 LONG_L $8, PT_R8(sp) 433 LONG_L $9, PT_R9(sp) 434#endif 435 LONG_L $7, PT_R7(sp) 436 LONG_L $6, PT_R6(sp) 437 LONG_L $5, PT_R5(sp) 438 LONG_L $4, PT_R4(sp) 439 LONG_L $3, PT_R3(sp) 440 LONG_L $2, PT_R2(sp) 441 .set pop 442 .endm 443 444 .macro RESTORE_SP_AND_RET 445 LONG_L sp, PT_R29(sp) 446 .set mips3 447 eret 448 .set mips0 449 .endm 450 451#endif 452 453 .macro RESTORE_SP 454 LONG_L sp, PT_R29(sp) 455 .endm 456 457 .macro RESTORE_ALL 458 RESTORE_TEMP 459 RESTORE_STATIC 460 RESTORE_AT 461 RESTORE_SOME 462 RESTORE_SP 463 .endm 464 465 .macro RESTORE_ALL_AND_RET 466 RESTORE_TEMP 467 RESTORE_STATIC 468 RESTORE_AT 469 RESTORE_SOME 470 RESTORE_SP_AND_RET 471 .endm 472 473/* 474 * Move to kernel mode and disable interrupts. 475 * Set cp0 enable bit as sign that we're running on the kernel stack 476 */ 477 .macro CLI 478#if !defined(CONFIG_MIPS_MT_SMTC) 479 mfc0 t0, CP0_STATUS 480 li t1, ST0_CU0 | STATMASK 481 or t0, t1 482 xori t0, STATMASK 483 mtc0 t0, CP0_STATUS 484#else /* CONFIG_MIPS_MT_SMTC */ 485 /* 486 * For SMTC, we need to set privilege 487 * and disable interrupts only for the 488 * current TC, using the TCStatus register. 489 */ 490 mfc0 t0, CP0_TCSTATUS 491 /* Fortunately CU 0 is in the same place in both registers */ 492 /* Set TCU0, TMX, TKSU (for later inversion) and IXMT */ 493 li t1, ST0_CU0 | 0x08001c00 494 or t0, t1 495 /* Clear TKSU, leave IXMT */ 496 xori t0, 0x00001800 497 mtc0 t0, CP0_TCSTATUS 498 _ehb 499 /* We need to leave the global IE bit set, but clear EXL...*/ 500 mfc0 t0, CP0_STATUS 501 ori t0, ST0_EXL | ST0_ERL 502 xori t0, ST0_EXL | ST0_ERL 503 mtc0 t0, CP0_STATUS 504#endif /* CONFIG_MIPS_MT_SMTC */ 505 irq_disable_hazard 506 .endm 507 508/* 509 * Move to kernel mode and enable interrupts. 510 * Set cp0 enable bit as sign that we're running on the kernel stack 511 */ 512 .macro STI 513#if !defined(CONFIG_MIPS_MT_SMTC) 514 mfc0 t0, CP0_STATUS 515 li t1, ST0_CU0 | STATMASK 516 or t0, t1 517 xori t0, STATMASK & ~1 518 mtc0 t0, CP0_STATUS 519#else /* CONFIG_MIPS_MT_SMTC */ 520 /* 521 * For SMTC, we need to set privilege 522 * and enable interrupts only for the 523 * current TC, using the TCStatus register. 524 */ 525 _ehb 526 mfc0 t0, CP0_TCSTATUS 527 /* Fortunately CU 0 is in the same place in both registers */ 528 /* Set TCU0, TKSU (for later inversion) and IXMT */ 529 li t1, ST0_CU0 | 0x08001c00 530 or t0, t1 531 /* Clear TKSU *and* IXMT */ 532 xori t0, 0x00001c00 533 mtc0 t0, CP0_TCSTATUS 534 _ehb 535 /* We need to leave the global IE bit set, but clear EXL...*/ 536 mfc0 t0, CP0_STATUS 537 ori t0, ST0_EXL 538 xori t0, ST0_EXL 539 mtc0 t0, CP0_STATUS 540 /* irq_enable_hazard below should expand to EHB for 24K/34K cpus */ 541#endif /* CONFIG_MIPS_MT_SMTC */ 542 irq_enable_hazard 543 .endm 544 545/* 546 * Just move to kernel mode and leave interrupts as they are. Note 547 * for the R3000 this means copying the previous enable from IEp. 548 * Set cp0 enable bit as sign that we're running on the kernel stack 549 */ 550 .macro KMODE 551#ifdef CONFIG_MIPS_MT_SMTC 552 /* 553 * This gets baroque in SMTC. We want to 554 * protect the non-atomic clearing of EXL 555 * with DMT/EMT, but we don't want to take 556 * an interrupt while DMT is still in effect. 557 */ 558 559 /* KMODE gets invoked from both reorder and noreorder code */ 560 .set push 561 .set mips32r2 562 .set noreorder 563 mfc0 v0, CP0_TCSTATUS 564 andi v1, v0, TCSTATUS_IXMT 565 ori v0, TCSTATUS_IXMT 566 mtc0 v0, CP0_TCSTATUS 567 _ehb 568 DMT 2 # dmt v0 569 /* 570 * We don't know a priori if ra is "live" 571 */ 572 move t0, ra 573 jal mips_ihb 574 nop /* delay slot */ 575 move ra, t0 576#endif /* CONFIG_MIPS_MT_SMTC */ 577 mfc0 t0, CP0_STATUS 578 li t1, ST0_CU0 | (STATMASK & ~1) 579#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX) 580 andi t2, t0, ST0_IEP 581 srl t2, 2 582 or t0, t2 583#endif 584 or t0, t1 585 xori t0, STATMASK & ~1 586 mtc0 t0, CP0_STATUS 587#ifdef CONFIG_MIPS_MT_SMTC 588 _ehb 589 andi v0, v0, VPECONTROL_TE 590 beqz v0, 2f 591 nop /* delay slot */ 592 emt 5932: 594 mfc0 v0, CP0_TCSTATUS 595 /* Clear IXMT, then OR in previous value */ 596 ori v0, TCSTATUS_IXMT 597 xori v0, TCSTATUS_IXMT 598 or v0, v1, v0 599 mtc0 v0, CP0_TCSTATUS 600 /* 601 * irq_disable_hazard below should expand to EHB 602 * on 24K/34K CPUS 603 */ 604 .set pop 605#endif /* CONFIG_MIPS_MT_SMTC */ 606 irq_disable_hazard 607 .endm 608 609#endif /* _ASM_STACKFRAME_H */ 610