1#ifndef _ASM_SMTC_MT_H 2#define _ASM_SMTC_MT_H 3 4/* 5 * Definitions for SMTC multitasking on MIPS MT cores 6 */ 7 8#include <asm/mips_mt.h> 9#include <asm/smtc_ipi.h> 10 11/* 12 * System-wide SMTC status information 13 */ 14 15extern unsigned int smtc_status; 16 17#define SMTC_TLB_SHARED 0x00000001 18#define SMTC_MTC_ACTIVE 0x00000002 19 20/* 21 * TLB/ASID Management information 22 */ 23 24#define MAX_SMTC_TLBS 2 25#define MAX_SMTC_ASIDS 256 26#if NR_CPUS <= 8 27typedef char asiduse; 28#else 29#if NR_CPUS <= 16 30typedef short asiduse; 31#else 32typedef long asiduse; 33#endif 34#endif 35 36/* 37 * VPE Management information 38 */ 39 40#define MAX_SMTC_VPES MAX_SMTC_TLBS 41 42extern asiduse smtc_live_asid[MAX_SMTC_TLBS][MAX_SMTC_ASIDS]; 43 44struct mm_struct; 45struct task_struct; 46 47void smtc_get_new_mmu_context(struct mm_struct *mm, unsigned long cpu); 48void self_ipi(struct smtc_ipi *); 49void smtc_flush_tlb_asid(unsigned long asid); 50extern int smtc_build_cpu_map(int startslot); 51extern void smtc_prepare_cpus(int cpus); 52extern void smtc_smp_finish(void); 53extern void smtc_boot_secondary(int cpu, struct task_struct *t); 54extern void smtc_cpus_done(void); 55 56 57/* 58 * Sharing the TLB between multiple VPEs means that the 59 * "random" index selection function is not allowed to 60 * select the current value of the Index register. To 61 * avoid additional TLB pressure, the Index registers 62 * are "parked" with an non-Valid value. 63 */ 64 65#define PARKED_INDEX ((unsigned int)0x80000000) 66 67/* 68 * Define low-level interrupt mask for IPIs, if necessary. 69 * By default, use SW interrupt 1, which requires no external 70 * hardware support, but which works only for single-core 71 * MIPS MT systems. 72 */ 73#ifndef MIPS_CPU_IPI_IRQ 74#define MIPS_CPU_IPI_IRQ 1 75#endif 76 77#endif /* _ASM_SMTC_MT_H */ 78