1/****************************************************************************/ 2 3/* 4 * m532xsim.h -- ColdFire 5329 registers 5 */ 6 7/****************************************************************************/ 8#ifndef m532xsim_h 9#define m532xsim_h 10/****************************************************************************/ 11 12#define MCF_REG32(x) (*(volatile unsigned long *)(x)) 13#define MCF_REG16(x) (*(volatile unsigned short *)(x)) 14#define MCF_REG08(x) (*(volatile unsigned char *)(x)) 15 16#define MCFINT_VECBASE 64 17#define MCFINT_UART0 26 /* Interrupt number for UART0 */ 18#define MCFINT_UART1 27 /* Interrupt number for UART1 */ 19#define MCFINT_UART2 28 /* Interrupt number for UART2 */ 20#define MCFINT_QSPI 31 /* Interrupt number for QSPI */ 21 22#define MCF_WTM_WCR MCF_REG16(0xFC098000) 23 24/* 25 * Define the 532x SIM register set addresses. 26 */ 27#define MCFSIM_IPRL 0xFC048004 28#define MCFSIM_IPRH 0xFC048000 29#define MCFSIM_IPR MCFSIM_IPRL 30#define MCFSIM_IMRL 0xFC04800C 31#define MCFSIM_IMRH 0xFC048008 32#define MCFSIM_IMR MCFSIM_IMRL 33#define MCFSIM_ICR0 0xFC048040 34#define MCFSIM_ICR1 0xFC048041 35#define MCFSIM_ICR2 0xFC048042 36#define MCFSIM_ICR3 0xFC048043 37#define MCFSIM_ICR4 0xFC048044 38#define MCFSIM_ICR5 0xFC048045 39#define MCFSIM_ICR6 0xFC048046 40#define MCFSIM_ICR7 0xFC048047 41#define MCFSIM_ICR8 0xFC048048 42#define MCFSIM_ICR9 0xFC048049 43#define MCFSIM_ICR10 0xFC04804A 44#define MCFSIM_ICR11 0xFC04804B 45 46/* 47 * Some symbol defines for the above... 48 */ 49#define MCFSIM_SWDICR MCFSIM_ICR0 /* Watchdog timer ICR */ 50#define MCFSIM_TIMER1ICR MCFSIM_ICR1 /* Timer 1 ICR */ 51#define MCFSIM_TIMER2ICR MCFSIM_ICR2 /* Timer 2 ICR */ 52#define MCFSIM_UART1ICR MCFSIM_ICR4 /* UART 1 ICR */ 53#define MCFSIM_UART2ICR MCFSIM_ICR5 /* UART 2 ICR */ 54#define MCFSIM_DMA0ICR MCFSIM_ICR6 /* DMA 0 ICR */ 55#define MCFSIM_DMA1ICR MCFSIM_ICR7 /* DMA 1 ICR */ 56#define MCFSIM_DMA2ICR MCFSIM_ICR8 /* DMA 2 ICR */ 57#define MCFSIM_DMA3ICR MCFSIM_ICR9 /* DMA 3 ICR */ 58 59 60#define MCFINTC0_SIMR 0xFC04801C 61#define MCFINTC0_CIMR 0xFC04801D 62#define MCFINTC0_ICR0 0xFC048040 63#define MCFINTC1_SIMR 0xFC04C01C 64#define MCFINTC1_CIMR 0xFC04C01D 65#define MCFINTC1_ICR0 0xFC04C040 66 67#define MCFSIM_ICR_TIMER1 (0xFC048040+32) 68#define MCFSIM_ICR_TIMER2 (0xFC048040+33) 69 70/* 71 * Define system peripheral IRQ usage. 72 */ 73#define MCF_IRQ_TIMER (64 + 32) /* Timer0 */ 74#define MCF_IRQ_PROFILER (64 + 33) /* Timer1 */ 75 76/* 77 * Define the Cache register flags. 78 */ 79#define CACR_EC (1<<31) 80#define CACR_ESB (1<<29) 81#define CACR_DPI (1<<28) 82#define CACR_HLCK (1<<27) 83#define CACR_CINVA (1<<24) 84#define CACR_DNFB (1<<10) 85#define CACR_DCM_WTHRU (0<<8) 86#define CACR_DCM_WBACK (1<<8) 87#define CACR_DCM_OFF_PRE (2<<8) 88#define CACR_DCM_OFF_IMP (3<<8) 89#define CACR_DW (1<<5) 90 91#define ACR_BASE_POS 24 92#define ACR_MASK_POS 16 93#define ACR_ENABLE (1<<15) 94#define ACR_USER (0<<13) 95#define ACR_SUPER (1<<13) 96#define ACR_ANY (2<<13) 97#define ACR_CM_WTHRU (0<<5) 98#define ACR_CM_WBACK (1<<5) 99#define ACR_CM_OFF_PRE (2<<5) 100#define ACR_CM_OFF_IMP (3<<5) 101#define ACR_WPROTECT (1<<2) 102 103/********************************************************************* 104 * 105 * Reset Controller Module 106 * 107 *********************************************************************/ 108 109#define MCF_RCR 0xFC0A0000 110#define MCF_RSR 0xFC0A0001 111 112#define MCF_RCR_SWRESET 0x80 /* Software reset bit */ 113#define MCF_RCR_FRCSTOUT 0x40 /* Force external reset */ 114 115/********************************************************************* 116 * 117 * Inter-IC (I2C) Module 118 * 119 *********************************************************************/ 120 121/* Read/Write access macros for general use */ 122#define MCF532x_I2C_I2ADR (volatile u8 *) (0xFC058000) // Address 123#define MCF532x_I2C_I2FDR (volatile u8 *) (0xFC058004) // Freq Divider 124#define MCF532x_I2C_I2CR (volatile u8 *) (0xFC058008) // Control 125#define MCF532x_I2C_I2SR (volatile u8 *) (0xFC05800C) // Status 126#define MCF532x_I2C_I2DR (volatile u8 *) (0xFC058010) // Data I/O 127 128/* Bit level definitions and macros */ 129#define MCF532x_I2C_I2ADR_ADDR(x) (((x)&0x7F)<<0x01) 130 131#define MCF532x_I2C_I2FDR_IC(x) (((x)&0x3F)) 132 133#define MCF532x_I2C_I2CR_IEN (0x80) // I2C enable 134#define MCF532x_I2C_I2CR_IIEN (0x40) // interrupt enable 135#define MCF532x_I2C_I2CR_MSTA (0x20) // master/slave mode 136#define MCF532x_I2C_I2CR_MTX (0x10) // transmit/receive mode 137#define MCF532x_I2C_I2CR_TXAK (0x08) // transmit acknowledge enable 138#define MCF532x_I2C_I2CR_RSTA (0x04) // repeat start 139 140#define MCF532x_I2C_I2SR_ICF (0x80) // data transfer bit 141#define MCF532x_I2C_I2SR_IAAS (0x40) // I2C addressed as a slave 142#define MCF532x_I2C_I2SR_IBB (0x20) // I2C bus busy 143#define MCF532x_I2C_I2SR_IAL (0x10) // aribitration lost 144#define MCF532x_I2C_I2SR_SRW (0x04) // slave read/write 145#define MCF532x_I2C_I2SR_IIF (0x02) // I2C interrupt 146#define MCF532x_I2C_I2SR_RXAK (0x01) // received acknowledge 147 148#define MCF532x_PAR_FECI2C (volatile u8 *) (0xFC0A4053) 149 150 151/* 152 * The M5329EVB board needs a help getting its devices initialized 153 * at kernel start time if dBUG doesn't set it up (for example 154 * it is not used), so we need to do it manually. 155 */ 156#ifdef __ASSEMBLER__ 157.macro m5329EVB_setup 158 movel #0xFC098000, %a7 159 movel #0x0, (%a7) 160#define CORE_SRAM 0x80000000 161#define CORE_SRAM_SIZE 0x8000 162 movel #CORE_SRAM, %d0 163 addl #0x221, %d0 164 movec %d0,%RAMBAR1 165 movel #CORE_SRAM, %sp 166 addl #CORE_SRAM_SIZE, %sp 167 jsr sysinit 168.endm 169#define PLATFORM_SETUP m5329EVB_setup 170 171#endif /* __ASSEMBLER__ */ 172 173/********************************************************************* 174 * 175 * Chip Configuration Module (CCM) 176 * 177 *********************************************************************/ 178 179/* Register read/write macros */ 180#define MCF_CCM_CCR MCF_REG16(0xFC0A0004) 181#define MCF_CCM_RCON MCF_REG16(0xFC0A0008) 182#define MCF_CCM_CIR MCF_REG16(0xFC0A000A) 183#define MCF_CCM_MISCCR MCF_REG16(0xFC0A0010) 184#define MCF_CCM_CDR MCF_REG16(0xFC0A0012) 185#define MCF_CCM_UHCSR MCF_REG16(0xFC0A0014) 186#define MCF_CCM_UOCSR MCF_REG16(0xFC0A0016) 187 188/* Bit definitions and macros for MCF_CCM_CCR */ 189#define MCF_CCM_CCR_RESERVED (0x0001) 190#define MCF_CCM_CCR_PLL_MODE (0x0003) 191#define MCF_CCM_CCR_OSC_MODE (0x0005) 192#define MCF_CCM_CCR_BOOTPS(x) (((x)&0x0003)<<3|0x0001) 193#define MCF_CCM_CCR_LOAD (0x0021) 194#define MCF_CCM_CCR_LIMP (0x0041) 195#define MCF_CCM_CCR_CSC(x) (((x)&0x0003)<<8|0x0001) 196 197/* Bit definitions and macros for MCF_CCM_RCON */ 198#define MCF_CCM_RCON_RESERVED (0x0001) 199#define MCF_CCM_RCON_PLL_MODE (0x0003) 200#define MCF_CCM_RCON_OSC_MODE (0x0005) 201#define MCF_CCM_RCON_BOOTPS(x) (((x)&0x0003)<<3|0x0001) 202#define MCF_CCM_RCON_LOAD (0x0021) 203#define MCF_CCM_RCON_LIMP (0x0041) 204#define MCF_CCM_RCON_CSC(x) (((x)&0x0003)<<8|0x0001) 205 206/* Bit definitions and macros for MCF_CCM_CIR */ 207#define MCF_CCM_CIR_PRN(x) (((x)&0x003F)<<0) 208#define MCF_CCM_CIR_PIN(x) (((x)&0x03FF)<<6) 209 210/* Bit definitions and macros for MCF_CCM_MISCCR */ 211#define MCF_CCM_MISCCR_USBSRC (0x0001) 212#define MCF_CCM_MISCCR_USBDIV (0x0002) 213#define MCF_CCM_MISCCR_SSI_SRC (0x0010) 214#define MCF_CCM_MISCCR_TIM_DMA (0x0020) 215#define MCF_CCM_MISCCR_SSI_PUS (0x0040) 216#define MCF_CCM_MISCCR_SSI_PUE (0x0080) 217#define MCF_CCM_MISCCR_LCD_CHEN (0x0100) 218#define MCF_CCM_MISCCR_LIMP (0x1000) 219#define MCF_CCM_MISCCR_PLL_LOCK (0x2000) 220 221/* Bit definitions and macros for MCF_CCM_CDR */ 222#define MCF_CCM_CDR_SSIDIV(x) (((x)&0x000F)<<0) 223#define MCF_CCM_CDR_LPDIV(x) (((x)&0x000F)<<8) 224 225/* Bit definitions and macros for MCF_CCM_UHCSR */ 226#define MCF_CCM_UHCSR_XPDE (0x0001) 227#define MCF_CCM_UHCSR_UHMIE (0x0002) 228#define MCF_CCM_UHCSR_WKUP (0x0004) 229#define MCF_CCM_UHCSR_PORTIND(x) (((x)&0x0003)<<14) 230 231/* Bit definitions and macros for MCF_CCM_UOCSR */ 232#define MCF_CCM_UOCSR_XPDE (0x0001) 233#define MCF_CCM_UOCSR_UOMIE (0x0002) 234#define MCF_CCM_UOCSR_WKUP (0x0004) 235#define MCF_CCM_UOCSR_PWRFLT (0x0008) 236#define MCF_CCM_UOCSR_SEND (0x0010) 237#define MCF_CCM_UOCSR_VVLD (0x0020) 238#define MCF_CCM_UOCSR_BVLD (0x0040) 239#define MCF_CCM_UOCSR_AVLD (0x0080) 240#define MCF_CCM_UOCSR_DPPU (0x0100) 241#define MCF_CCM_UOCSR_DCR_VBUS (0x0200) 242#define MCF_CCM_UOCSR_CRG_VBUS (0x0400) 243#define MCF_CCM_UOCSR_DRV_VBUS (0x0800) 244#define MCF_CCM_UOCSR_DMPD (0x1000) 245#define MCF_CCM_UOCSR_DPPD (0x2000) 246#define MCF_CCM_UOCSR_PORTIND(x) (((x)&0x0003)<<14) 247 248/********************************************************************* 249 * 250 * DMA Timers (DTIM) 251 * 252 *********************************************************************/ 253 254/* Register read/write macros */ 255#define MCF_DTIM0_DTMR MCF_REG16(0xFC070000) 256#define MCF_DTIM0_DTXMR MCF_REG08(0xFC070002) 257#define MCF_DTIM0_DTER MCF_REG08(0xFC070003) 258#define MCF_DTIM0_DTRR MCF_REG32(0xFC070004) 259#define MCF_DTIM0_DTCR MCF_REG32(0xFC070008) 260#define MCF_DTIM0_DTCN MCF_REG32(0xFC07000C) 261#define MCF_DTIM1_DTMR MCF_REG16(0xFC074000) 262#define MCF_DTIM1_DTXMR MCF_REG08(0xFC074002) 263#define MCF_DTIM1_DTER MCF_REG08(0xFC074003) 264#define MCF_DTIM1_DTRR MCF_REG32(0xFC074004) 265#define MCF_DTIM1_DTCR MCF_REG32(0xFC074008) 266#define MCF_DTIM1_DTCN MCF_REG32(0xFC07400C) 267#define MCF_DTIM2_DTMR MCF_REG16(0xFC078000) 268#define MCF_DTIM2_DTXMR MCF_REG08(0xFC078002) 269#define MCF_DTIM2_DTER MCF_REG08(0xFC078003) 270#define MCF_DTIM2_DTRR MCF_REG32(0xFC078004) 271#define MCF_DTIM2_DTCR MCF_REG32(0xFC078008) 272#define MCF_DTIM2_DTCN MCF_REG32(0xFC07800C) 273#define MCF_DTIM3_DTMR MCF_REG16(0xFC07C000) 274#define MCF_DTIM3_DTXMR MCF_REG08(0xFC07C002) 275#define MCF_DTIM3_DTER MCF_REG08(0xFC07C003) 276#define MCF_DTIM3_DTRR MCF_REG32(0xFC07C004) 277#define MCF_DTIM3_DTCR MCF_REG32(0xFC07C008) 278#define MCF_DTIM3_DTCN MCF_REG32(0xFC07C00C) 279#define MCF_DTIM_DTMR(x) MCF_REG16(0xFC070000+((x)*0x4000)) 280#define MCF_DTIM_DTXMR(x) MCF_REG08(0xFC070002+((x)*0x4000)) 281#define MCF_DTIM_DTER(x) MCF_REG08(0xFC070003+((x)*0x4000)) 282#define MCF_DTIM_DTRR(x) MCF_REG32(0xFC070004+((x)*0x4000)) 283#define MCF_DTIM_DTCR(x) MCF_REG32(0xFC070008+((x)*0x4000)) 284#define MCF_DTIM_DTCN(x) MCF_REG32(0xFC07000C+((x)*0x4000)) 285 286/* Bit definitions and macros for MCF_DTIM_DTMR */ 287#define MCF_DTIM_DTMR_RST (0x0001) 288#define MCF_DTIM_DTMR_CLK(x) (((x)&0x0003)<<1) 289#define MCF_DTIM_DTMR_FRR (0x0008) 290#define MCF_DTIM_DTMR_ORRI (0x0010) 291#define MCF_DTIM_DTMR_OM (0x0020) 292#define MCF_DTIM_DTMR_CE(x) (((x)&0x0003)<<6) 293#define MCF_DTIM_DTMR_PS(x) (((x)&0x00FF)<<8) 294#define MCF_DTIM_DTMR_CE_ANY (0x00C0) 295#define MCF_DTIM_DTMR_CE_FALL (0x0080) 296#define MCF_DTIM_DTMR_CE_RISE (0x0040) 297#define MCF_DTIM_DTMR_CE_NONE (0x0000) 298#define MCF_DTIM_DTMR_CLK_DTIN (0x0006) 299#define MCF_DTIM_DTMR_CLK_DIV16 (0x0004) 300#define MCF_DTIM_DTMR_CLK_DIV1 (0x0002) 301#define MCF_DTIM_DTMR_CLK_STOP (0x0000) 302 303/* Bit definitions and macros for MCF_DTIM_DTXMR */ 304#define MCF_DTIM_DTXMR_MODE16 (0x01) 305#define MCF_DTIM_DTXMR_DMAEN (0x80) 306 307/* Bit definitions and macros for MCF_DTIM_DTER */ 308#define MCF_DTIM_DTER_CAP (0x01) 309#define MCF_DTIM_DTER_REF (0x02) 310 311/* Bit definitions and macros for MCF_DTIM_DTRR */ 312#define MCF_DTIM_DTRR_REF(x) (((x)&0xFFFFFFFF)<<0) 313 314/* Bit definitions and macros for MCF_DTIM_DTCR */ 315#define MCF_DTIM_DTCR_CAP(x) (((x)&0xFFFFFFFF)<<0) 316 317/* Bit definitions and macros for MCF_DTIM_DTCN */ 318#define MCF_DTIM_DTCN_CNT(x) (((x)&0xFFFFFFFF)<<0) 319 320/********************************************************************* 321 * 322 * FlexBus Chip Selects (FBCS) 323 * 324 *********************************************************************/ 325 326/* Register read/write macros */ 327#define MCF_FBCS0_CSAR MCF_REG32(0xFC008000) 328#define MCF_FBCS0_CSMR MCF_REG32(0xFC008004) 329#define MCF_FBCS0_CSCR MCF_REG32(0xFC008008) 330#define MCF_FBCS1_CSAR MCF_REG32(0xFC00800C) 331#define MCF_FBCS1_CSMR MCF_REG32(0xFC008010) 332#define MCF_FBCS1_CSCR MCF_REG32(0xFC008014) 333#define MCF_FBCS2_CSAR MCF_REG32(0xFC008018) 334#define MCF_FBCS2_CSMR MCF_REG32(0xFC00801C) 335#define MCF_FBCS2_CSCR MCF_REG32(0xFC008020) 336#define MCF_FBCS3_CSAR MCF_REG32(0xFC008024) 337#define MCF_FBCS3_CSMR MCF_REG32(0xFC008028) 338#define MCF_FBCS3_CSCR MCF_REG32(0xFC00802C) 339#define MCF_FBCS4_CSAR MCF_REG32(0xFC008030) 340#define MCF_FBCS4_CSMR MCF_REG32(0xFC008034) 341#define MCF_FBCS4_CSCR MCF_REG32(0xFC008038) 342#define MCF_FBCS5_CSAR MCF_REG32(0xFC00803C) 343#define MCF_FBCS5_CSMR MCF_REG32(0xFC008040) 344#define MCF_FBCS5_CSCR MCF_REG32(0xFC008044) 345#define MCF_FBCS_CSAR(x) MCF_REG32(0xFC008000+((x)*0x00C)) 346#define MCF_FBCS_CSMR(x) MCF_REG32(0xFC008004+((x)*0x00C)) 347#define MCF_FBCS_CSCR(x) MCF_REG32(0xFC008008+((x)*0x00C)) 348 349/* Bit definitions and macros for MCF_FBCS_CSAR */ 350#define MCF_FBCS_CSAR_BA(x) ((x)&0xFFFF0000) 351 352/* Bit definitions and macros for MCF_FBCS_CSMR */ 353#define MCF_FBCS_CSMR_V (0x00000001) 354#define MCF_FBCS_CSMR_WP (0x00000100) 355#define MCF_FBCS_CSMR_BAM(x) (((x)&0x0000FFFF)<<16) 356#define MCF_FBCS_CSMR_BAM_4G (0xFFFF0000) 357#define MCF_FBCS_CSMR_BAM_2G (0x7FFF0000) 358#define MCF_FBCS_CSMR_BAM_1G (0x3FFF0000) 359#define MCF_FBCS_CSMR_BAM_1024M (0x3FFF0000) 360#define MCF_FBCS_CSMR_BAM_512M (0x1FFF0000) 361#define MCF_FBCS_CSMR_BAM_256M (0x0FFF0000) 362#define MCF_FBCS_CSMR_BAM_128M (0x07FF0000) 363#define MCF_FBCS_CSMR_BAM_64M (0x03FF0000) 364#define MCF_FBCS_CSMR_BAM_32M (0x01FF0000) 365#define MCF_FBCS_CSMR_BAM_16M (0x00FF0000) 366#define MCF_FBCS_CSMR_BAM_8M (0x007F0000) 367#define MCF_FBCS_CSMR_BAM_4M (0x003F0000) 368#define MCF_FBCS_CSMR_BAM_2M (0x001F0000) 369#define MCF_FBCS_CSMR_BAM_1M (0x000F0000) 370#define MCF_FBCS_CSMR_BAM_1024K (0x000F0000) 371#define MCF_FBCS_CSMR_BAM_512K (0x00070000) 372#define MCF_FBCS_CSMR_BAM_256K (0x00030000) 373#define MCF_FBCS_CSMR_BAM_128K (0x00010000) 374#define MCF_FBCS_CSMR_BAM_64K (0x00000000) 375 376/* Bit definitions and macros for MCF_FBCS_CSCR */ 377#define MCF_FBCS_CSCR_BSTW (0x00000008) 378#define MCF_FBCS_CSCR_BSTR (0x00000010) 379#define MCF_FBCS_CSCR_BEM (0x00000020) 380#define MCF_FBCS_CSCR_PS(x) (((x)&0x00000003)<<6) 381#define MCF_FBCS_CSCR_AA (0x00000100) 382#define MCF_FBCS_CSCR_SBM (0x00000200) 383#define MCF_FBCS_CSCR_WS(x) (((x)&0x0000003F)<<10) 384#define MCF_FBCS_CSCR_WRAH(x) (((x)&0x00000003)<<16) 385#define MCF_FBCS_CSCR_RDAH(x) (((x)&0x00000003)<<18) 386#define MCF_FBCS_CSCR_ASET(x) (((x)&0x00000003)<<20) 387#define MCF_FBCS_CSCR_SWSEN (0x00800000) 388#define MCF_FBCS_CSCR_SWS(x) (((x)&0x0000003F)<<26) 389#define MCF_FBCS_CSCR_PS_8 (0x0040) 390#define MCF_FBCS_CSCR_PS_16 (0x0080) 391#define MCF_FBCS_CSCR_PS_32 (0x0000) 392 393/********************************************************************* 394 * 395 * General Purpose I/O (GPIO) 396 * 397 *********************************************************************/ 398 399/* Register read/write macros */ 400#define MCFGPIO_PODR_FECH (0xFC0A4000) 401#define MCFGPIO_PODR_FECL (0xFC0A4001) 402#define MCFGPIO_PODR_SSI (0xFC0A4002) 403#define MCFGPIO_PODR_BUSCTL (0xFC0A4003) 404#define MCFGPIO_PODR_BE (0xFC0A4004) 405#define MCFGPIO_PODR_CS (0xFC0A4005) 406#define MCFGPIO_PODR_PWM (0xFC0A4006) 407#define MCFGPIO_PODR_FECI2C (0xFC0A4007) 408#define MCFGPIO_PODR_UART (0xFC0A4009) 409#define MCFGPIO_PODR_QSPI (0xFC0A400A) 410#define MCFGPIO_PODR_TIMER (0xFC0A400B) 411#define MCFGPIO_PODR_LCDDATAH (0xFC0A400D) 412#define MCFGPIO_PODR_LCDDATAM (0xFC0A400E) 413#define MCFGPIO_PODR_LCDDATAL (0xFC0A400F) 414#define MCFGPIO_PODR_LCDCTLH (0xFC0A4010) 415#define MCFGPIO_PODR_LCDCTLL (0xFC0A4011) 416#define MCFGPIO_PDDR_FECH (0xFC0A4014) 417#define MCFGPIO_PDDR_FECL (0xFC0A4015) 418#define MCFGPIO_PDDR_SSI (0xFC0A4016) 419#define MCFGPIO_PDDR_BUSCTL (0xFC0A4017) 420#define MCFGPIO_PDDR_BE (0xFC0A4018) 421#define MCFGPIO_PDDR_CS (0xFC0A4019) 422#define MCFGPIO_PDDR_PWM (0xFC0A401A) 423#define MCFGPIO_PDDR_FECI2C (0xFC0A401B) 424#define MCFGPIO_PDDR_UART (0xFC0A401C) 425#define MCFGPIO_PDDR_QSPI (0xFC0A401E) 426#define MCFGPIO_PDDR_TIMER (0xFC0A401F) 427#define MCFGPIO_PDDR_LCDDATAH (0xFC0A4021) 428#define MCFGPIO_PDDR_LCDDATAM (0xFC0A4022) 429#define MCFGPIO_PDDR_LCDDATAL (0xFC0A4023) 430#define MCFGPIO_PDDR_LCDCTLH (0xFC0A4024) 431#define MCFGPIO_PDDR_LCDCTLL (0xFC0A4025) 432#define MCFGPIO_PPDSDR_FECH (0xFC0A4028) 433#define MCFGPIO_PPDSDR_FECL (0xFC0A4029) 434#define MCFGPIO_PPDSDR_SSI (0xFC0A402A) 435#define MCFGPIO_PPDSDR_BUSCTL (0xFC0A402B) 436#define MCFGPIO_PPDSDR_BE (0xFC0A402C) 437#define MCFGPIO_PPDSDR_CS (0xFC0A402D) 438#define MCFGPIO_PPDSDR_PWM (0xFC0A402E) 439#define MCFGPIO_PPDSDR_FECI2C (0xFC0A402F) 440#define MCFGPIO_PPDSDR_UART (0xFC0A4031) 441#define MCFGPIO_PPDSDR_QSPI (0xFC0A4032) 442#define MCFGPIO_PPDSDR_TIMER (0xFC0A4033) 443#define MCFGPIO_PPDSDR_LCDDATAH (0xFC0A4035) 444#define MCFGPIO_PPDSDR_LCDDATAM (0xFC0A4036) 445#define MCFGPIO_PPDSDR_LCDDATAL (0xFC0A4037) 446#define MCFGPIO_PPDSDR_LCDCTLH (0xFC0A4038) 447#define MCFGPIO_PPDSDR_LCDCTLL (0xFC0A4039) 448#define MCFGPIO_PCLRR_FECH (0xFC0A403C) 449#define MCFGPIO_PCLRR_FECL (0xFC0A403D) 450#define MCFGPIO_PCLRR_SSI (0xFC0A403E) 451#define MCFGPIO_PCLRR_BUSCTL (0xFC0A403F) 452#define MCFGPIO_PCLRR_BE (0xFC0A4040) 453#define MCFGPIO_PCLRR_CS (0xFC0A4041) 454#define MCFGPIO_PCLRR_PWM (0xFC0A4042) 455#define MCFGPIO_PCLRR_FECI2C (0xFC0A4043) 456#define MCFGPIO_PCLRR_UART (0xFC0A4045) 457#define MCFGPIO_PCLRR_QSPI (0xFC0A4046) 458#define MCFGPIO_PCLRR_TIMER (0xFC0A4047) 459#define MCFGPIO_PCLRR_LCDDATAH (0xFC0A4049) 460#define MCFGPIO_PCLRR_LCDDATAM (0xFC0A404A) 461#define MCFGPIO_PCLRR_LCDDATAL (0xFC0A404B) 462#define MCFGPIO_PCLRR_LCDCTLH (0xFC0A404C) 463#define MCFGPIO_PCLRR_LCDCTLL (0xFC0A404D) 464#define MCF_GPIO_PAR_FEC MCF_REG08(0xFC0A4050) 465#define MCF_GPIO_PAR_PWM MCF_REG08(0xFC0A4051) 466#define MCF_GPIO_PAR_BUSCTL MCF_REG08(0xFC0A4052) 467#define MCF_GPIO_PAR_FECI2C MCF_REG08(0xFC0A4053) 468#define MCF_GPIO_PAR_BE MCF_REG08(0xFC0A4054) 469#define MCF_GPIO_PAR_CS MCF_REG08(0xFC0A4055) 470#define MCF_GPIO_PAR_SSI MCF_REG16(0xFC0A4056) 471#define MCF_GPIO_PAR_UART MCF_REG16(0xFC0A4058) 472#define MCF_GPIO_PAR_QSPI MCF_REG16(0xFC0A405A) 473#define MCF_GPIO_PAR_TIMER MCF_REG08(0xFC0A405C) 474#define MCF_GPIO_PAR_LCDDATA MCF_REG08(0xFC0A405D) 475#define MCF_GPIO_PAR_LCDCTL MCF_REG16(0xFC0A405E) 476#define MCF_GPIO_PAR_IRQ MCF_REG16(0xFC0A4060) 477#define MCF_GPIO_MSCR_FLEXBUS MCF_REG08(0xFC0A4064) 478#define MCF_GPIO_MSCR_SDRAM MCF_REG08(0xFC0A4065) 479#define MCF_GPIO_DSCR_I2C MCF_REG08(0xFC0A4068) 480#define MCF_GPIO_DSCR_PWM MCF_REG08(0xFC0A4069) 481#define MCF_GPIO_DSCR_FEC MCF_REG08(0xFC0A406A) 482#define MCF_GPIO_DSCR_UART MCF_REG08(0xFC0A406B) 483#define MCF_GPIO_DSCR_QSPI MCF_REG08(0xFC0A406C) 484#define MCF_GPIO_DSCR_TIMER MCF_REG08(0xFC0A406D) 485#define MCF_GPIO_DSCR_SSI MCF_REG08(0xFC0A406E) 486#define MCF_GPIO_DSCR_LCD MCF_REG08(0xFC0A406F) 487#define MCF_GPIO_DSCR_DEBUG MCF_REG08(0xFC0A4070) 488#define MCF_GPIO_DSCR_CLKRST MCF_REG08(0xFC0A4071) 489#define MCF_GPIO_DSCR_IRQ MCF_REG08(0xFC0A4072) 490 491/* Bit definitions and macros for MCF_GPIO_PODR_FECH */ 492#define MCF_GPIO_PODR_FECH_PODR_FECH0 (0x01) 493#define MCF_GPIO_PODR_FECH_PODR_FECH1 (0x02) 494#define MCF_GPIO_PODR_FECH_PODR_FECH2 (0x04) 495#define MCF_GPIO_PODR_FECH_PODR_FECH3 (0x08) 496#define MCF_GPIO_PODR_FECH_PODR_FECH4 (0x10) 497#define MCF_GPIO_PODR_FECH_PODR_FECH5 (0x20) 498#define MCF_GPIO_PODR_FECH_PODR_FECH6 (0x40) 499#define MCF_GPIO_PODR_FECH_PODR_FECH7 (0x80) 500 501/* Bit definitions and macros for MCF_GPIO_PODR_FECL */ 502#define MCF_GPIO_PODR_FECL_PODR_FECL0 (0x01) 503#define MCF_GPIO_PODR_FECL_PODR_FECL1 (0x02) 504#define MCF_GPIO_PODR_FECL_PODR_FECL2 (0x04) 505#define MCF_GPIO_PODR_FECL_PODR_FECL3 (0x08) 506#define MCF_GPIO_PODR_FECL_PODR_FECL4 (0x10) 507#define MCF_GPIO_PODR_FECL_PODR_FECL5 (0x20) 508#define MCF_GPIO_PODR_FECL_PODR_FECL6 (0x40) 509#define MCF_GPIO_PODR_FECL_PODR_FECL7 (0x80) 510 511/* Bit definitions and macros for MCF_GPIO_PODR_SSI */ 512#define MCF_GPIO_PODR_SSI_PODR_SSI0 (0x01) 513#define MCF_GPIO_PODR_SSI_PODR_SSI1 (0x02) 514#define MCF_GPIO_PODR_SSI_PODR_SSI2 (0x04) 515#define MCF_GPIO_PODR_SSI_PODR_SSI3 (0x08) 516#define MCF_GPIO_PODR_SSI_PODR_SSI4 (0x10) 517 518/* Bit definitions and macros for MCF_GPIO_PODR_BUSCTL */ 519#define MCF_GPIO_PODR_BUSCTL_POSDR_BUSCTL0 (0x01) 520#define MCF_GPIO_PODR_BUSCTL_PODR_BUSCTL1 (0x02) 521#define MCF_GPIO_PODR_BUSCTL_PODR_BUSCTL2 (0x04) 522#define MCF_GPIO_PODR_BUSCTL_PODR_BUSCTL3 (0x08) 523 524/* Bit definitions and macros for MCF_GPIO_PODR_BE */ 525#define MCF_GPIO_PODR_BE_PODR_BE0 (0x01) 526#define MCF_GPIO_PODR_BE_PODR_BE1 (0x02) 527#define MCF_GPIO_PODR_BE_PODR_BE2 (0x04) 528#define MCF_GPIO_PODR_BE_PODR_BE3 (0x08) 529 530/* Bit definitions and macros for MCF_GPIO_PODR_CS */ 531#define MCF_GPIO_PODR_CS_PODR_CS1 (0x02) 532#define MCF_GPIO_PODR_CS_PODR_CS2 (0x04) 533#define MCF_GPIO_PODR_CS_PODR_CS3 (0x08) 534#define MCF_GPIO_PODR_CS_PODR_CS4 (0x10) 535#define MCF_GPIO_PODR_CS_PODR_CS5 (0x20) 536 537/* Bit definitions and macros for MCF_GPIO_PODR_PWM */ 538#define MCF_GPIO_PODR_PWM_PODR_PWM2 (0x04) 539#define MCF_GPIO_PODR_PWM_PODR_PWM3 (0x08) 540#define MCF_GPIO_PODR_PWM_PODR_PWM4 (0x10) 541#define MCF_GPIO_PODR_PWM_PODR_PWM5 (0x20) 542 543/* Bit definitions and macros for MCF_GPIO_PODR_FECI2C */ 544#define MCF_GPIO_PODR_FECI2C_PODR_FECI2C0 (0x01) 545#define MCF_GPIO_PODR_FECI2C_PODR_FECI2C1 (0x02) 546#define MCF_GPIO_PODR_FECI2C_PODR_FECI2C2 (0x04) 547#define MCF_GPIO_PODR_FECI2C_PODR_FECI2C3 (0x08) 548 549/* Bit definitions and macros for MCF_GPIO_PODR_UART */ 550#define MCF_GPIO_PODR_UART_PODR_UART0 (0x01) 551#define MCF_GPIO_PODR_UART_PODR_UART1 (0x02) 552#define MCF_GPIO_PODR_UART_PODR_UART2 (0x04) 553#define MCF_GPIO_PODR_UART_PODR_UART3 (0x08) 554#define MCF_GPIO_PODR_UART_PODR_UART4 (0x10) 555#define MCF_GPIO_PODR_UART_PODR_UART5 (0x20) 556#define MCF_GPIO_PODR_UART_PODR_UART6 (0x40) 557#define MCF_GPIO_PODR_UART_PODR_UART7 (0x80) 558 559/* Bit definitions and macros for MCF_GPIO_PODR_QSPI */ 560#define MCF_GPIO_PODR_QSPI_PODR_QSPI0 (0x01) 561#define MCF_GPIO_PODR_QSPI_PODR_QSPI1 (0x02) 562#define MCF_GPIO_PODR_QSPI_PODR_QSPI2 (0x04) 563#define MCF_GPIO_PODR_QSPI_PODR_QSPI3 (0x08) 564#define MCF_GPIO_PODR_QSPI_PODR_QSPI4 (0x10) 565#define MCF_GPIO_PODR_QSPI_PODR_QSPI5 (0x20) 566 567/* Bit definitions and macros for MCF_GPIO_PODR_TIMER */ 568#define MCF_GPIO_PODR_TIMER_PODR_TIMER0 (0x01) 569#define MCF_GPIO_PODR_TIMER_PODR_TIMER1 (0x02) 570#define MCF_GPIO_PODR_TIMER_PODR_TIMER2 (0x04) 571#define MCF_GPIO_PODR_TIMER_PODR_TIMER3 (0x08) 572 573/* Bit definitions and macros for MCF_GPIO_PODR_LCDDATAH */ 574#define MCF_GPIO_PODR_LCDDATAH_PODR_LCDDATAH0 (0x01) 575#define MCF_GPIO_PODR_LCDDATAH_PODR_LCDDATAH1 (0x02) 576 577/* Bit definitions and macros for MCF_GPIO_PODR_LCDDATAM */ 578#define MCF_GPIO_PODR_LCDDATAM_PODR_LCDDATAM0 (0x01) 579#define MCF_GPIO_PODR_LCDDATAM_PODR_LCDDATAM1 (0x02) 580#define MCF_GPIO_PODR_LCDDATAM_PODR_LCDDATAM2 (0x04) 581#define MCF_GPIO_PODR_LCDDATAM_PODR_LCDDATAM3 (0x08) 582#define MCF_GPIO_PODR_LCDDATAM_PODR_LCDDATAM4 (0x10) 583#define MCF_GPIO_PODR_LCDDATAM_PODR_LCDDATAM5 (0x20) 584#define MCF_GPIO_PODR_LCDDATAM_PODR_LCDDATAM6 (0x40) 585#define MCF_GPIO_PODR_LCDDATAM_PODR_LCDDATAM7 (0x80) 586 587/* Bit definitions and macros for MCF_GPIO_PODR_LCDDATAL */ 588#define MCF_GPIO_PODR_LCDDATAL_PODR_LCDDATAL0 (0x01) 589#define MCF_GPIO_PODR_LCDDATAL_PODR_LCDDATAL1 (0x02) 590#define MCF_GPIO_PODR_LCDDATAL_PODR_LCDDATAL2 (0x04) 591#define MCF_GPIO_PODR_LCDDATAL_PODR_LCDDATAL3 (0x08) 592#define MCF_GPIO_PODR_LCDDATAL_PODR_LCDDATAL4 (0x10) 593#define MCF_GPIO_PODR_LCDDATAL_PODR_LCDDATAL5 (0x20) 594#define MCF_GPIO_PODR_LCDDATAL_PODR_LCDDATAL6 (0x40) 595#define MCF_GPIO_PODR_LCDDATAL_PODR_LCDDATAL7 (0x80) 596 597/* Bit definitions and macros for MCF_GPIO_PODR_LCDCTLH */ 598#define MCF_GPIO_PODR_LCDCTLH_PODR_LCDCTLH0 (0x01) 599 600/* Bit definitions and macros for MCF_GPIO_PODR_LCDCTLL */ 601#define MCF_GPIO_PODR_LCDCTLL_PODR_LCDCTLL0 (0x01) 602#define MCF_GPIO_PODR_LCDCTLL_PODR_LCDCTLL1 (0x02) 603#define MCF_GPIO_PODR_LCDCTLL_PODR_LCDCTLL2 (0x04) 604#define MCF_GPIO_PODR_LCDCTLL_PODR_LCDCTLL3 (0x08) 605#define MCF_GPIO_PODR_LCDCTLL_PODR_LCDCTLL4 (0x10) 606#define MCF_GPIO_PODR_LCDCTLL_PODR_LCDCTLL5 (0x20) 607#define MCF_GPIO_PODR_LCDCTLL_PODR_LCDCTLL6 (0x40) 608#define MCF_GPIO_PODR_LCDCTLL_PODR_LCDCTLL7 (0x80) 609 610/* Bit definitions and macros for MCF_GPIO_PDDR_FECH */ 611#define MCF_GPIO_PDDR_FECH_PDDR_FECH0 (0x01) 612#define MCF_GPIO_PDDR_FECH_PDDR_FECH1 (0x02) 613#define MCF_GPIO_PDDR_FECH_PDDR_FECH2 (0x04) 614#define MCF_GPIO_PDDR_FECH_PDDR_FECH3 (0x08) 615#define MCF_GPIO_PDDR_FECH_PDDR_FECH4 (0x10) 616#define MCF_GPIO_PDDR_FECH_PDDR_FECH5 (0x20) 617#define MCF_GPIO_PDDR_FECH_PDDR_FECH6 (0x40) 618#define MCF_GPIO_PDDR_FECH_PDDR_FECH7 (0x80) 619 620/* Bit definitions and macros for MCF_GPIO_PDDR_FECL */ 621#define MCF_GPIO_PDDR_FECL_PDDR_FECL0 (0x01) 622#define MCF_GPIO_PDDR_FECL_PDDR_FECL1 (0x02) 623#define MCF_GPIO_PDDR_FECL_PDDR_FECL2 (0x04) 624#define MCF_GPIO_PDDR_FECL_PDDR_FECL3 (0x08) 625#define MCF_GPIO_PDDR_FECL_PDDR_FECL4 (0x10) 626#define MCF_GPIO_PDDR_FECL_PDDR_FECL5 (0x20) 627#define MCF_GPIO_PDDR_FECL_PDDR_FECL6 (0x40) 628#define MCF_GPIO_PDDR_FECL_PDDR_FECL7 (0x80) 629 630/* Bit definitions and macros for MCF_GPIO_PDDR_SSI */ 631#define MCF_GPIO_PDDR_SSI_PDDR_SSI0 (0x01) 632#define MCF_GPIO_PDDR_SSI_PDDR_SSI1 (0x02) 633#define MCF_GPIO_PDDR_SSI_PDDR_SSI2 (0x04) 634#define MCF_GPIO_PDDR_SSI_PDDR_SSI3 (0x08) 635#define MCF_GPIO_PDDR_SSI_PDDR_SSI4 (0x10) 636 637/* Bit definitions and macros for MCF_GPIO_PDDR_BUSCTL */ 638#define MCF_GPIO_PDDR_BUSCTL_POSDR_BUSCTL0 (0x01) 639#define MCF_GPIO_PDDR_BUSCTL_PDDR_BUSCTL1 (0x02) 640#define MCF_GPIO_PDDR_BUSCTL_PDDR_BUSCTL2 (0x04) 641#define MCF_GPIO_PDDR_BUSCTL_PDDR_BUSCTL3 (0x08) 642 643/* Bit definitions and macros for MCF_GPIO_PDDR_BE */ 644#define MCF_GPIO_PDDR_BE_PDDR_BE0 (0x01) 645#define MCF_GPIO_PDDR_BE_PDDR_BE1 (0x02) 646#define MCF_GPIO_PDDR_BE_PDDR_BE2 (0x04) 647#define MCF_GPIO_PDDR_BE_PDDR_BE3 (0x08) 648 649/* Bit definitions and macros for MCF_GPIO_PDDR_CS */ 650#define MCF_GPIO_PDDR_CS_PDDR_CS1 (0x02) 651#define MCF_GPIO_PDDR_CS_PDDR_CS2 (0x04) 652#define MCF_GPIO_PDDR_CS_PDDR_CS3 (0x08) 653#define MCF_GPIO_PDDR_CS_PDDR_CS4 (0x10) 654#define MCF_GPIO_PDDR_CS_PDDR_CS5 (0x20) 655 656/* Bit definitions and macros for MCF_GPIO_PDDR_PWM */ 657#define MCF_GPIO_PDDR_PWM_PDDR_PWM2 (0x04) 658#define MCF_GPIO_PDDR_PWM_PDDR_PWM3 (0x08) 659#define MCF_GPIO_PDDR_PWM_PDDR_PWM4 (0x10) 660#define MCF_GPIO_PDDR_PWM_PDDR_PWM5 (0x20) 661 662/* Bit definitions and macros for MCF_GPIO_PDDR_FECI2C */ 663#define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C0 (0x01) 664#define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C1 (0x02) 665#define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C2 (0x04) 666#define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C3 (0x08) 667 668/* Bit definitions and macros for MCF_GPIO_PDDR_UART */ 669#define MCF_GPIO_PDDR_UART_PDDR_UART0 (0x01) 670#define MCF_GPIO_PDDR_UART_PDDR_UART1 (0x02) 671#define MCF_GPIO_PDDR_UART_PDDR_UART2 (0x04) 672#define MCF_GPIO_PDDR_UART_PDDR_UART3 (0x08) 673#define MCF_GPIO_PDDR_UART_PDDR_UART4 (0x10) 674#define MCF_GPIO_PDDR_UART_PDDR_UART5 (0x20) 675#define MCF_GPIO_PDDR_UART_PDDR_UART6 (0x40) 676#define MCF_GPIO_PDDR_UART_PDDR_UART7 (0x80) 677 678/* Bit definitions and macros for MCF_GPIO_PDDR_QSPI */ 679#define MCF_GPIO_PDDR_QSPI_PDDR_QSPI0 (0x01) 680#define MCF_GPIO_PDDR_QSPI_PDDR_QSPI1 (0x02) 681#define MCF_GPIO_PDDR_QSPI_PDDR_QSPI2 (0x04) 682#define MCF_GPIO_PDDR_QSPI_PDDR_QSPI3 (0x08) 683#define MCF_GPIO_PDDR_QSPI_PDDR_QSPI4 (0x10) 684#define MCF_GPIO_PDDR_QSPI_PDDR_QSPI5 (0x20) 685 686/* Bit definitions and macros for MCF_GPIO_PDDR_TIMER */ 687#define MCF_GPIO_PDDR_TIMER_PDDR_TIMER0 (0x01) 688#define MCF_GPIO_PDDR_TIMER_PDDR_TIMER1 (0x02) 689#define MCF_GPIO_PDDR_TIMER_PDDR_TIMER2 (0x04) 690#define MCF_GPIO_PDDR_TIMER_PDDR_TIMER3 (0x08) 691 692/* Bit definitions and macros for MCF_GPIO_PDDR_LCDDATAH */ 693#define MCF_GPIO_PDDR_LCDDATAH_PDDR_LCDDATAH0 (0x01) 694#define MCF_GPIO_PDDR_LCDDATAH_PDDR_LCDDATAH1 (0x02) 695 696/* Bit definitions and macros for MCF_GPIO_PDDR_LCDDATAM */ 697#define MCF_GPIO_PDDR_LCDDATAM_PDDR_LCDDATAM0 (0x01) 698#define MCF_GPIO_PDDR_LCDDATAM_PDDR_LCDDATAM1 (0x02) 699#define MCF_GPIO_PDDR_LCDDATAM_PDDR_LCDDATAM2 (0x04) 700#define MCF_GPIO_PDDR_LCDDATAM_PDDR_LCDDATAM3 (0x08) 701#define MCF_GPIO_PDDR_LCDDATAM_PDDR_LCDDATAM4 (0x10) 702#define MCF_GPIO_PDDR_LCDDATAM_PDDR_LCDDATAM5 (0x20) 703#define MCF_GPIO_PDDR_LCDDATAM_PDDR_LCDDATAM6 (0x40) 704#define MCF_GPIO_PDDR_LCDDATAM_PDDR_LCDDATAM7 (0x80) 705 706/* Bit definitions and macros for MCF_GPIO_PDDR_LCDDATAL */ 707#define MCF_GPIO_PDDR_LCDDATAL_PDDR_LCDDATAL0 (0x01) 708#define MCF_GPIO_PDDR_LCDDATAL_PDDR_LCDDATAL1 (0x02) 709#define MCF_GPIO_PDDR_LCDDATAL_PDDR_LCDDATAL2 (0x04) 710#define MCF_GPIO_PDDR_LCDDATAL_PDDR_LCDDATAL3 (0x08) 711#define MCF_GPIO_PDDR_LCDDATAL_PDDR_LCDDATAL4 (0x10) 712#define MCF_GPIO_PDDR_LCDDATAL_PDDR_LCDDATAL5 (0x20) 713#define MCF_GPIO_PDDR_LCDDATAL_PDDR_LCDDATAL6 (0x40) 714#define MCF_GPIO_PDDR_LCDDATAL_PDDR_LCDDATAL7 (0x80) 715 716/* Bit definitions and macros for MCF_GPIO_PDDR_LCDCTLH */ 717#define MCF_GPIO_PDDR_LCDCTLH_PDDR_LCDCTLH0 (0x01) 718 719/* Bit definitions and macros for MCF_GPIO_PDDR_LCDCTLL */ 720#define MCF_GPIO_PDDR_LCDCTLL_PDDR_LCDCTLL0 (0x01) 721#define MCF_GPIO_PDDR_LCDCTLL_PDDR_LCDCTLL1 (0x02) 722#define MCF_GPIO_PDDR_LCDCTLL_PDDR_LCDCTLL2 (0x04) 723#define MCF_GPIO_PDDR_LCDCTLL_PDDR_LCDCTLL3 (0x08) 724#define MCF_GPIO_PDDR_LCDCTLL_PDDR_LCDCTLL4 (0x10) 725#define MCF_GPIO_PDDR_LCDCTLL_PDDR_LCDCTLL5 (0x20) 726#define MCF_GPIO_PDDR_LCDCTLL_PDDR_LCDCTLL6 (0x40) 727#define MCF_GPIO_PDDR_LCDCTLL_PDDR_LCDCTLL7 (0x80) 728 729/* Bit definitions and macros for MCF_GPIO_PPDSDR_FECH */ 730#define MCF_GPIO_PPDSDR_FECH_PPDSDR_FECH0 (0x01) 731#define MCF_GPIO_PPDSDR_FECH_PPDSDR_FECH1 (0x02) 732#define MCF_GPIO_PPDSDR_FECH_PPDSDR_FECH2 (0x04) 733#define MCF_GPIO_PPDSDR_FECH_PPDSDR_FECH3 (0x08) 734#define MCF_GPIO_PPDSDR_FECH_PPDSDR_FECH4 (0x10) 735#define MCF_GPIO_PPDSDR_FECH_PPDSDR_FECH5 (0x20) 736#define MCF_GPIO_PPDSDR_FECH_PPDSDR_FECH6 (0x40) 737#define MCF_GPIO_PPDSDR_FECH_PPDSDR_FECH7 (0x80) 738 739/* Bit definitions and macros for MCF_GPIO_PPDSDR_FECL */ 740#define MCF_GPIO_PPDSDR_FECL_PPDSDR_FECL0 (0x01) 741#define MCF_GPIO_PPDSDR_FECL_PPDSDR_FECL1 (0x02) 742#define MCF_GPIO_PPDSDR_FECL_PPDSDR_FECL2 (0x04) 743#define MCF_GPIO_PPDSDR_FECL_PPDSDR_FECL3 (0x08) 744#define MCF_GPIO_PPDSDR_FECL_PPDSDR_FECL4 (0x10) 745#define MCF_GPIO_PPDSDR_FECL_PPDSDR_FECL5 (0x20) 746#define MCF_GPIO_PPDSDR_FECL_PPDSDR_FECL6 (0x40) 747#define MCF_GPIO_PPDSDR_FECL_PPDSDR_FECL7 (0x80) 748 749/* Bit definitions and macros for MCF_GPIO_PPDSDR_SSI */ 750#define MCF_GPIO_PPDSDR_SSI_PPDSDR_SSI0 (0x01) 751#define MCF_GPIO_PPDSDR_SSI_PPDSDR_SSI1 (0x02) 752#define MCF_GPIO_PPDSDR_SSI_PPDSDR_SSI2 (0x04) 753#define MCF_GPIO_PPDSDR_SSI_PPDSDR_SSI3 (0x08) 754#define MCF_GPIO_PPDSDR_SSI_PPDSDR_SSI4 (0x10) 755 756/* Bit definitions and macros for MCF_GPIO_PPDSDR_BUSCTL */ 757#define MCF_GPIO_PPDSDR_BUSCTL_POSDR_BUSCTL0 (0x01) 758#define MCF_GPIO_PPDSDR_BUSCTL_PPDSDR_BUSCTL1 (0x02) 759#define MCF_GPIO_PPDSDR_BUSCTL_PPDSDR_BUSCTL2 (0x04) 760#define MCF_GPIO_PPDSDR_BUSCTL_PPDSDR_BUSCTL3 (0x08) 761 762/* Bit definitions and macros for MCF_GPIO_PPDSDR_BE */ 763#define MCF_GPIO_PPDSDR_BE_PPDSDR_BE0 (0x01) 764#define MCF_GPIO_PPDSDR_BE_PPDSDR_BE1 (0x02) 765#define MCF_GPIO_PPDSDR_BE_PPDSDR_BE2 (0x04) 766#define MCF_GPIO_PPDSDR_BE_PPDSDR_BE3 (0x08) 767 768/* Bit definitions and macros for MCF_GPIO_PPDSDR_CS */ 769#define MCF_GPIO_PPDSDR_CS_PPDSDR_CS1 (0x02) 770#define MCF_GPIO_PPDSDR_CS_PPDSDR_CS2 (0x04) 771#define MCF_GPIO_PPDSDR_CS_PPDSDR_CS3 (0x08) 772#define MCF_GPIO_PPDSDR_CS_PPDSDR_CS4 (0x10) 773#define MCF_GPIO_PPDSDR_CS_PPDSDR_CS5 (0x20) 774 775/* Bit definitions and macros for MCF_GPIO_PPDSDR_PWM */ 776#define MCF_GPIO_PPDSDR_PWM_PPDSDR_PWM2 (0x04) 777#define MCF_GPIO_PPDSDR_PWM_PPDSDR_PWM3 (0x08) 778#define MCF_GPIO_PPDSDR_PWM_PPDSDR_PWM4 (0x10) 779#define MCF_GPIO_PPDSDR_PWM_PPDSDR_PWM5 (0x20) 780 781/* Bit definitions and macros for MCF_GPIO_PPDSDR_FECI2C */ 782#define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C0 (0x01) 783#define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C1 (0x02) 784#define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C2 (0x04) 785#define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C3 (0x08) 786 787/* Bit definitions and macros for MCF_GPIO_PPDSDR_UART */ 788#define MCF_GPIO_PPDSDR_UART_PPDSDR_UART0 (0x01) 789#define MCF_GPIO_PPDSDR_UART_PPDSDR_UART1 (0x02) 790#define MCF_GPIO_PPDSDR_UART_PPDSDR_UART2 (0x04) 791#define MCF_GPIO_PPDSDR_UART_PPDSDR_UART3 (0x08) 792#define MCF_GPIO_PPDSDR_UART_PPDSDR_UART4 (0x10) 793#define MCF_GPIO_PPDSDR_UART_PPDSDR_UART5 (0x20) 794#define MCF_GPIO_PPDSDR_UART_PPDSDR_UART6 (0x40) 795#define MCF_GPIO_PPDSDR_UART_PPDSDR_UART7 (0x80) 796 797/* Bit definitions and macros for MCF_GPIO_PPDSDR_QSPI */ 798#define MCF_GPIO_PPDSDR_QSPI_PPDSDR_QSPI0 (0x01) 799#define MCF_GPIO_PPDSDR_QSPI_PPDSDR_QSPI1 (0x02) 800#define MCF_GPIO_PPDSDR_QSPI_PPDSDR_QSPI2 (0x04) 801#define MCF_GPIO_PPDSDR_QSPI_PPDSDR_QSPI3 (0x08) 802#define MCF_GPIO_PPDSDR_QSPI_PPDSDR_QSPI4 (0x10) 803#define MCF_GPIO_PPDSDR_QSPI_PPDSDR_QSPI5 (0x20) 804 805/* Bit definitions and macros for MCF_GPIO_PPDSDR_TIMER */ 806#define MCF_GPIO_PPDSDR_TIMER_PPDSDR_TIMER0 (0x01) 807#define MCF_GPIO_PPDSDR_TIMER_PPDSDR_TIMER1 (0x02) 808#define MCF_GPIO_PPDSDR_TIMER_PPDSDR_TIMER2 (0x04) 809#define MCF_GPIO_PPDSDR_TIMER_PPDSDR_TIMER3 (0x08) 810 811/* Bit definitions and macros for MCF_GPIO_PPDSDR_LCDDATAH */ 812#define MCF_GPIO_PPDSDR_LCDDATAH_PPDSDR_LCDDATAH0 (0x01) 813#define MCF_GPIO_PPDSDR_LCDDATAH_PPDSDR_LCDDATAH1 (0x02) 814 815/* Bit definitions and macros for MCF_GPIO_PPDSDR_LCDDATAM */ 816#define MCF_GPIO_PPDSDR_LCDDATAM_PPDSDR_LCDDATAM0 (0x01) 817#define MCF_GPIO_PPDSDR_LCDDATAM_PPDSDR_LCDDATAM1 (0x02) 818#define MCF_GPIO_PPDSDR_LCDDATAM_PPDSDR_LCDDATAM2 (0x04) 819#define MCF_GPIO_PPDSDR_LCDDATAM_PPDSDR_LCDDATAM3 (0x08) 820#define MCF_GPIO_PPDSDR_LCDDATAM_PPDSDR_LCDDATAM4 (0x10) 821#define MCF_GPIO_PPDSDR_LCDDATAM_PPDSDR_LCDDATAM5 (0x20) 822#define MCF_GPIO_PPDSDR_LCDDATAM_PPDSDR_LCDDATAM6 (0x40) 823#define MCF_GPIO_PPDSDR_LCDDATAM_PPDSDR_LCDDATAM7 (0x80) 824 825/* Bit definitions and macros for MCF_GPIO_PPDSDR_LCDDATAL */ 826#define MCF_GPIO_PPDSDR_LCDDATAL_PPDSDR_LCDDATAL0 (0x01) 827#define MCF_GPIO_PPDSDR_LCDDATAL_PPDSDR_LCDDATAL1 (0x02) 828#define MCF_GPIO_PPDSDR_LCDDATAL_PPDSDR_LCDDATAL2 (0x04) 829#define MCF_GPIO_PPDSDR_LCDDATAL_PPDSDR_LCDDATAL3 (0x08) 830#define MCF_GPIO_PPDSDR_LCDDATAL_PPDSDR_LCDDATAL4 (0x10) 831#define MCF_GPIO_PPDSDR_LCDDATAL_PPDSDR_LCDDATAL5 (0x20) 832#define MCF_GPIO_PPDSDR_LCDDATAL_PPDSDR_LCDDATAL6 (0x40) 833#define MCF_GPIO_PPDSDR_LCDDATAL_PPDSDR_LCDDATAL7 (0x80) 834 835/* Bit definitions and macros for MCF_GPIO_PPDSDR_LCDCTLH */ 836#define MCF_GPIO_PPDSDR_LCDCTLH_PPDSDR_LCDCTLH0 (0x01) 837 838/* Bit definitions and macros for MCF_GPIO_PPDSDR_LCDCTLL */ 839#define MCF_GPIO_PPDSDR_LCDCTLL_PPDSDR_LCDCTLL0 (0x01) 840#define MCF_GPIO_PPDSDR_LCDCTLL_PPDSDR_LCDCTLL1 (0x02) 841#define MCF_GPIO_PPDSDR_LCDCTLL_PPDSDR_LCDCTLL2 (0x04) 842#define MCF_GPIO_PPDSDR_LCDCTLL_PPDSDR_LCDCTLL3 (0x08) 843#define MCF_GPIO_PPDSDR_LCDCTLL_PPDSDR_LCDCTLL4 (0x10) 844#define MCF_GPIO_PPDSDR_LCDCTLL_PPDSDR_LCDCTLL5 (0x20) 845#define MCF_GPIO_PPDSDR_LCDCTLL_PPDSDR_LCDCTLL6 (0x40) 846#define MCF_GPIO_PPDSDR_LCDCTLL_PPDSDR_LCDCTLL7 (0x80) 847 848/* Bit definitions and macros for MCF_GPIO_PCLRR_FECH */ 849#define MCF_GPIO_PCLRR_FECH_PCLRR_FECH0 (0x01) 850#define MCF_GPIO_PCLRR_FECH_PCLRR_FECH1 (0x02) 851#define MCF_GPIO_PCLRR_FECH_PCLRR_FECH2 (0x04) 852#define MCF_GPIO_PCLRR_FECH_PCLRR_FECH3 (0x08) 853#define MCF_GPIO_PCLRR_FECH_PCLRR_FECH4 (0x10) 854#define MCF_GPIO_PCLRR_FECH_PCLRR_FECH5 (0x20) 855#define MCF_GPIO_PCLRR_FECH_PCLRR_FECH6 (0x40) 856#define MCF_GPIO_PCLRR_FECH_PCLRR_FECH7 (0x80) 857 858/* Bit definitions and macros for MCF_GPIO_PCLRR_FECL */ 859#define MCF_GPIO_PCLRR_FECL_PCLRR_FECL0 (0x01) 860#define MCF_GPIO_PCLRR_FECL_PCLRR_FECL1 (0x02) 861#define MCF_GPIO_PCLRR_FECL_PCLRR_FECL2 (0x04) 862#define MCF_GPIO_PCLRR_FECL_PCLRR_FECL3 (0x08) 863#define MCF_GPIO_PCLRR_FECL_PCLRR_FECL4 (0x10) 864#define MCF_GPIO_PCLRR_FECL_PCLRR_FECL5 (0x20) 865#define MCF_GPIO_PCLRR_FECL_PCLRR_FECL6 (0x40) 866#define MCF_GPIO_PCLRR_FECL_PCLRR_FECL7 (0x80) 867 868/* Bit definitions and macros for MCF_GPIO_PCLRR_SSI */ 869#define MCF_GPIO_PCLRR_SSI_PCLRR_SSI0 (0x01) 870#define MCF_GPIO_PCLRR_SSI_PCLRR_SSI1 (0x02) 871#define MCF_GPIO_PCLRR_SSI_PCLRR_SSI2 (0x04) 872#define MCF_GPIO_PCLRR_SSI_PCLRR_SSI3 (0x08) 873#define MCF_GPIO_PCLRR_SSI_PCLRR_SSI4 (0x10) 874 875/* Bit definitions and macros for MCF_GPIO_PCLRR_BUSCTL */ 876#define MCF_GPIO_PCLRR_BUSCTL_POSDR_BUSCTL0 (0x01) 877#define MCF_GPIO_PCLRR_BUSCTL_PCLRR_BUSCTL1 (0x02) 878#define MCF_GPIO_PCLRR_BUSCTL_PCLRR_BUSCTL2 (0x04) 879#define MCF_GPIO_PCLRR_BUSCTL_PCLRR_BUSCTL3 (0x08) 880 881/* Bit definitions and macros for MCF_GPIO_PCLRR_BE */ 882#define MCF_GPIO_PCLRR_BE_PCLRR_BE0 (0x01) 883#define MCF_GPIO_PCLRR_BE_PCLRR_BE1 (0x02) 884#define MCF_GPIO_PCLRR_BE_PCLRR_BE2 (0x04) 885#define MCF_GPIO_PCLRR_BE_PCLRR_BE3 (0x08) 886 887/* Bit definitions and macros for MCF_GPIO_PCLRR_CS */ 888#define MCF_GPIO_PCLRR_CS_PCLRR_CS1 (0x02) 889#define MCF_GPIO_PCLRR_CS_PCLRR_CS2 (0x04) 890#define MCF_GPIO_PCLRR_CS_PCLRR_CS3 (0x08) 891#define MCF_GPIO_PCLRR_CS_PCLRR_CS4 (0x10) 892#define MCF_GPIO_PCLRR_CS_PCLRR_CS5 (0x20) 893 894/* Bit definitions and macros for MCF_GPIO_PCLRR_PWM */ 895#define MCF_GPIO_PCLRR_PWM_PCLRR_PWM2 (0x04) 896#define MCF_GPIO_PCLRR_PWM_PCLRR_PWM3 (0x08) 897#define MCF_GPIO_PCLRR_PWM_PCLRR_PWM4 (0x10) 898#define MCF_GPIO_PCLRR_PWM_PCLRR_PWM5 (0x20) 899 900/* Bit definitions and macros for MCF_GPIO_PCLRR_FECI2C */ 901#define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C0 (0x01) 902#define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C1 (0x02) 903#define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C2 (0x04) 904#define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C3 (0x08) 905 906/* Bit definitions and macros for MCF_GPIO_PCLRR_UART */ 907#define MCF_GPIO_PCLRR_UART_PCLRR_UART0 (0x01) 908#define MCF_GPIO_PCLRR_UART_PCLRR_UART1 (0x02) 909#define MCF_GPIO_PCLRR_UART_PCLRR_UART2 (0x04) 910#define MCF_GPIO_PCLRR_UART_PCLRR_UART3 (0x08) 911#define MCF_GPIO_PCLRR_UART_PCLRR_UART4 (0x10) 912#define MCF_GPIO_PCLRR_UART_PCLRR_UART5 (0x20) 913#define MCF_GPIO_PCLRR_UART_PCLRR_UART6 (0x40) 914#define MCF_GPIO_PCLRR_UART_PCLRR_UART7 (0x80) 915 916/* Bit definitions and macros for MCF_GPIO_PCLRR_QSPI */ 917#define MCF_GPIO_PCLRR_QSPI_PCLRR_QSPI0 (0x01) 918#define MCF_GPIO_PCLRR_QSPI_PCLRR_QSPI1 (0x02) 919#define MCF_GPIO_PCLRR_QSPI_PCLRR_QSPI2 (0x04) 920#define MCF_GPIO_PCLRR_QSPI_PCLRR_QSPI3 (0x08) 921#define MCF_GPIO_PCLRR_QSPI_PCLRR_QSPI4 (0x10) 922#define MCF_GPIO_PCLRR_QSPI_PCLRR_QSPI5 (0x20) 923 924/* Bit definitions and macros for MCF_GPIO_PCLRR_TIMER */ 925#define MCF_GPIO_PCLRR_TIMER_PCLRR_TIMER0 (0x01) 926#define MCF_GPIO_PCLRR_TIMER_PCLRR_TIMER1 (0x02) 927#define MCF_GPIO_PCLRR_TIMER_PCLRR_TIMER2 (0x04) 928#define MCF_GPIO_PCLRR_TIMER_PCLRR_TIMER3 (0x08) 929 930/* Bit definitions and macros for MCF_GPIO_PCLRR_LCDDATAH */ 931#define MCF_GPIO_PCLRR_LCDDATAH_PCLRR_LCDDATAH0 (0x01) 932#define MCF_GPIO_PCLRR_LCDDATAH_PCLRR_LCDDATAH1 (0x02) 933 934/* Bit definitions and macros for MCF_GPIO_PCLRR_LCDDATAM */ 935#define MCF_GPIO_PCLRR_LCDDATAM_PCLRR_LCDDATAM0 (0x01) 936#define MCF_GPIO_PCLRR_LCDDATAM_PCLRR_LCDDATAM1 (0x02) 937#define MCF_GPIO_PCLRR_LCDDATAM_PCLRR_LCDDATAM2 (0x04) 938#define MCF_GPIO_PCLRR_LCDDATAM_PCLRR_LCDDATAM3 (0x08) 939#define MCF_GPIO_PCLRR_LCDDATAM_PCLRR_LCDDATAM4 (0x10) 940#define MCF_GPIO_PCLRR_LCDDATAM_PCLRR_LCDDATAM5 (0x20) 941#define MCF_GPIO_PCLRR_LCDDATAM_PCLRR_LCDDATAM6 (0x40) 942#define MCF_GPIO_PCLRR_LCDDATAM_PCLRR_LCDDATAM7 (0x80) 943 944/* Bit definitions and macros for MCF_GPIO_PCLRR_LCDDATAL */ 945#define MCF_GPIO_PCLRR_LCDDATAL_PCLRR_LCDDATAL0 (0x01) 946#define MCF_GPIO_PCLRR_LCDDATAL_PCLRR_LCDDATAL1 (0x02) 947#define MCF_GPIO_PCLRR_LCDDATAL_PCLRR_LCDDATAL2 (0x04) 948#define MCF_GPIO_PCLRR_LCDDATAL_PCLRR_LCDDATAL3 (0x08) 949#define MCF_GPIO_PCLRR_LCDDATAL_PCLRR_LCDDATAL4 (0x10) 950#define MCF_GPIO_PCLRR_LCDDATAL_PCLRR_LCDDATAL5 (0x20) 951#define MCF_GPIO_PCLRR_LCDDATAL_PCLRR_LCDDATAL6 (0x40) 952#define MCF_GPIO_PCLRR_LCDDATAL_PCLRR_LCDDATAL7 (0x80) 953 954/* Bit definitions and macros for MCF_GPIO_PCLRR_LCDCTLH */ 955#define MCF_GPIO_PCLRR_LCDCTLH_PCLRR_LCDCTLH0 (0x01) 956 957/* Bit definitions and macros for MCF_GPIO_PCLRR_LCDCTLL */ 958#define MCF_GPIO_PCLRR_LCDCTLL_PCLRR_LCDCTLL0 (0x01) 959#define MCF_GPIO_PCLRR_LCDCTLL_PCLRR_LCDCTLL1 (0x02) 960#define MCF_GPIO_PCLRR_LCDCTLL_PCLRR_LCDCTLL2 (0x04) 961#define MCF_GPIO_PCLRR_LCDCTLL_PCLRR_LCDCTLL3 (0x08) 962#define MCF_GPIO_PCLRR_LCDCTLL_PCLRR_LCDCTLL4 (0x10) 963#define MCF_GPIO_PCLRR_LCDCTLL_PCLRR_LCDCTLL5 (0x20) 964#define MCF_GPIO_PCLRR_LCDCTLL_PCLRR_LCDCTLL6 (0x40) 965#define MCF_GPIO_PCLRR_LCDCTLL_PCLRR_LCDCTLL7 (0x80) 966 967/* Bit definitions and macros for MCF_GPIO_PAR_FEC */ 968#define MCF_GPIO_PAR_FEC_PAR_FEC_MII(x) (((x)&0x03)<<0) 969#define MCF_GPIO_PAR_FEC_PAR_FEC_7W(x) (((x)&0x03)<<2) 970#define MCF_GPIO_PAR_FEC_PAR_FEC_7W_GPIO (0x00) 971#define MCF_GPIO_PAR_FEC_PAR_FEC_7W_URTS1 (0x04) 972#define MCF_GPIO_PAR_FEC_PAR_FEC_7W_FEC (0x0C) 973#define MCF_GPIO_PAR_FEC_PAR_FEC_MII_GPIO (0x00) 974#define MCF_GPIO_PAR_FEC_PAR_FEC_MII_UART (0x01) 975#define MCF_GPIO_PAR_FEC_PAR_FEC_MII_FEC (0x03) 976 977/* Bit definitions and macros for MCF_GPIO_PAR_PWM */ 978#define MCF_GPIO_PAR_PWM_PAR_PWM1(x) (((x)&0x03)<<0) 979#define MCF_GPIO_PAR_PWM_PAR_PWM3(x) (((x)&0x03)<<2) 980#define MCF_GPIO_PAR_PWM_PAR_PWM5 (0x10) 981#define MCF_GPIO_PAR_PWM_PAR_PWM7 (0x20) 982 983/* Bit definitions and macros for MCF_GPIO_PAR_BUSCTL */ 984#define MCF_GPIO_PAR_BUSCTL_PAR_TS(x) (((x)&0x03)<<3) 985#define MCF_GPIO_PAR_BUSCTL_PAR_RWB (0x20) 986#define MCF_GPIO_PAR_BUSCTL_PAR_TA (0x40) 987#define MCF_GPIO_PAR_BUSCTL_PAR_OE (0x80) 988#define MCF_GPIO_PAR_BUSCTL_PAR_OE_GPIO (0x00) 989#define MCF_GPIO_PAR_BUSCTL_PAR_OE_OE (0x80) 990#define MCF_GPIO_PAR_BUSCTL_PAR_TA_GPIO (0x00) 991#define MCF_GPIO_PAR_BUSCTL_PAR_TA_TA (0x40) 992#define MCF_GPIO_PAR_BUSCTL_PAR_RWB_GPIO (0x00) 993#define MCF_GPIO_PAR_BUSCTL_PAR_RWB_RWB (0x20) 994#define MCF_GPIO_PAR_BUSCTL_PAR_TS_GPIO (0x00) 995#define MCF_GPIO_PAR_BUSCTL_PAR_TS_DACK0 (0x10) 996#define MCF_GPIO_PAR_BUSCTL_PAR_TS_TS (0x18) 997 998/* Bit definitions and macros for MCF_GPIO_PAR_FECI2C */ 999#define MCF_GPIO_PAR_FECI2C_PAR_SDA(x) (((x)&0x03)<<0) 1000#define MCF_GPIO_PAR_FECI2C_PAR_SCL(x) (((x)&0x03)<<2) 1001#define MCF_GPIO_PAR_FECI2C_PAR_MDIO(x) (((x)&0x03)<<4) 1002#define MCF_GPIO_PAR_FECI2C_PAR_MDC(x) (((x)&0x03)<<6) 1003#define MCF_GPIO_PAR_FECI2C_PAR_MDC_GPIO (0x00) 1004#define MCF_GPIO_PAR_FECI2C_PAR_MDC_UTXD2 (0x40) 1005#define MCF_GPIO_PAR_FECI2C_PAR_MDC_SCL (0x80) 1006#define MCF_GPIO_PAR_FECI2C_PAR_MDC_EMDC (0xC0) 1007#define MCF_GPIO_PAR_FECI2C_PAR_MDIO_GPIO (0x00) 1008#define MCF_GPIO_PAR_FECI2C_PAR_MDIO_URXD2 (0x10) 1009#define MCF_GPIO_PAR_FECI2C_PAR_MDIO_SDA (0x20) 1010#define MCF_GPIO_PAR_FECI2C_PAR_MDIO_EMDIO (0x30) 1011#define MCF_GPIO_PAR_FECI2C_PAR_SCL_GPIO (0x00) 1012#define MCF_GPIO_PAR_FECI2C_PAR_SCL_UTXD2 (0x04) 1013#define MCF_GPIO_PAR_FECI2C_PAR_SCL_SCL (0x0C) 1014#define MCF_GPIO_PAR_FECI2C_PAR_SDA_GPIO (0x00) 1015#define MCF_GPIO_PAR_FECI2C_PAR_SDA_URXD2 (0x02) 1016#define MCF_GPIO_PAR_FECI2C_PAR_SDA_SDA (0x03) 1017 1018/* Bit definitions and macros for MCF_GPIO_PAR_BE */ 1019#define MCF_GPIO_PAR_BE_PAR_BE0 (0x01) 1020#define MCF_GPIO_PAR_BE_PAR_BE1 (0x02) 1021#define MCF_GPIO_PAR_BE_PAR_BE2 (0x04) 1022#define MCF_GPIO_PAR_BE_PAR_BE3 (0x08) 1023 1024/* Bit definitions and macros for MCF_GPIO_PAR_CS */ 1025#define MCF_GPIO_PAR_CS_PAR_CS1 (0x02) 1026#define MCF_GPIO_PAR_CS_PAR_CS2 (0x04) 1027#define MCF_GPIO_PAR_CS_PAR_CS3 (0x08) 1028#define MCF_GPIO_PAR_CS_PAR_CS4 (0x10) 1029#define MCF_GPIO_PAR_CS_PAR_CS5 (0x20) 1030#define MCF_GPIO_PAR_CS_PAR_CS_CS1_GPIO (0x00) 1031#define MCF_GPIO_PAR_CS_PAR_CS_CS1_SDCS1 (0x01) 1032#define MCF_GPIO_PAR_CS_PAR_CS_CS1_CS1 (0x03) 1033 1034/* Bit definitions and macros for MCF_GPIO_PAR_SSI */ 1035#define MCF_GPIO_PAR_SSI_PAR_MCLK (0x0080) 1036#define MCF_GPIO_PAR_SSI_PAR_TXD(x) (((x)&0x0003)<<8) 1037#define MCF_GPIO_PAR_SSI_PAR_RXD(x) (((x)&0x0003)<<10) 1038#define MCF_GPIO_PAR_SSI_PAR_FS(x) (((x)&0x0003)<<12) 1039#define MCF_GPIO_PAR_SSI_PAR_BCLK(x) (((x)&0x0003)<<14) 1040 1041/* Bit definitions and macros for MCF_GPIO_PAR_UART */ 1042#define MCF_GPIO_PAR_UART_PAR_UTXD0 (0x0001) 1043#define MCF_GPIO_PAR_UART_PAR_URXD0 (0x0002) 1044#define MCF_GPIO_PAR_UART_PAR_URTS0 (0x0004) 1045#define MCF_GPIO_PAR_UART_PAR_UCTS0 (0x0008) 1046#define MCF_GPIO_PAR_UART_PAR_UTXD1(x) (((x)&0x0003)<<4) 1047#define MCF_GPIO_PAR_UART_PAR_URXD1(x) (((x)&0x0003)<<6) 1048#define MCF_GPIO_PAR_UART_PAR_URTS1(x) (((x)&0x0003)<<8) 1049#define MCF_GPIO_PAR_UART_PAR_UCTS1(x) (((x)&0x0003)<<10) 1050#define MCF_GPIO_PAR_UART_PAR_UCTS1_GPIO (0x0000) 1051#define MCF_GPIO_PAR_UART_PAR_UCTS1_SSI_BCLK (0x0800) 1052#define MCF_GPIO_PAR_UART_PAR_UCTS1_ULPI_D7 (0x0400) 1053#define MCF_GPIO_PAR_UART_PAR_UCTS1_UCTS1 (0x0C00) 1054#define MCF_GPIO_PAR_UART_PAR_URTS1_GPIO (0x0000) 1055#define MCF_GPIO_PAR_UART_PAR_URTS1_SSI_FS (0x0200) 1056#define MCF_GPIO_PAR_UART_PAR_URTS1_ULPI_D6 (0x0100) 1057#define MCF_GPIO_PAR_UART_PAR_URTS1_URTS1 (0x0300) 1058#define MCF_GPIO_PAR_UART_PAR_URXD1_GPIO (0x0000) 1059#define MCF_GPIO_PAR_UART_PAR_URXD1_SSI_RXD (0x0080) 1060#define MCF_GPIO_PAR_UART_PAR_URXD1_ULPI_D5 (0x0040) 1061#define MCF_GPIO_PAR_UART_PAR_URXD1_URXD1 (0x00C0) 1062#define MCF_GPIO_PAR_UART_PAR_UTXD1_GPIO (0x0000) 1063#define MCF_GPIO_PAR_UART_PAR_UTXD1_SSI_TXD (0x0020) 1064#define MCF_GPIO_PAR_UART_PAR_UTXD1_ULPI_D4 (0x0010) 1065#define MCF_GPIO_PAR_UART_PAR_UTXD1_UTXD1 (0x0030) 1066 1067/* Bit definitions and macros for MCF_GPIO_PAR_QSPI */ 1068#define MCF_GPIO_PAR_QSPI_PAR_SCK(x) (((x)&0x0003)<<4) 1069#define MCF_GPIO_PAR_QSPI_PAR_DOUT(x) (((x)&0x0003)<<6) 1070#define MCF_GPIO_PAR_QSPI_PAR_DIN(x) (((x)&0x0003)<<8) 1071#define MCF_GPIO_PAR_QSPI_PAR_PCS0(x) (((x)&0x0003)<<10) 1072#define MCF_GPIO_PAR_QSPI_PAR_PCS1(x) (((x)&0x0003)<<12) 1073#define MCF_GPIO_PAR_QSPI_PAR_PCS2(x) (((x)&0x0003)<<14) 1074 1075/* Bit definitions and macros for MCF_GPIO_PAR_TIMER */ 1076#define MCF_GPIO_PAR_TIMER_PAR_TIN0(x) (((x)&0x03)<<0) 1077#define MCF_GPIO_PAR_TIMER_PAR_TIN1(x) (((x)&0x03)<<2) 1078#define MCF_GPIO_PAR_TIMER_PAR_TIN2(x) (((x)&0x03)<<4) 1079#define MCF_GPIO_PAR_TIMER_PAR_TIN3(x) (((x)&0x03)<<6) 1080#define MCF_GPIO_PAR_TIMER_PAR_TIN3_GPIO (0x00) 1081#define MCF_GPIO_PAR_TIMER_PAR_TIN3_TOUT3 (0x80) 1082#define MCF_GPIO_PAR_TIMER_PAR_TIN3_URXD2 (0x40) 1083#define MCF_GPIO_PAR_TIMER_PAR_TIN3_TIN3 (0xC0) 1084#define MCF_GPIO_PAR_TIMER_PAR_TIN2_GPIO (0x00) 1085#define MCF_GPIO_PAR_TIMER_PAR_TIN2_TOUT2 (0x20) 1086#define MCF_GPIO_PAR_TIMER_PAR_TIN2_UTXD2 (0x10) 1087#define MCF_GPIO_PAR_TIMER_PAR_TIN2_TIN2 (0x30) 1088#define MCF_GPIO_PAR_TIMER_PAR_TIN1_GPIO (0x00) 1089#define MCF_GPIO_PAR_TIMER_PAR_TIN1_TOUT1 (0x08) 1090#define MCF_GPIO_PAR_TIMER_PAR_TIN1_DACK1 (0x04) 1091#define MCF_GPIO_PAR_TIMER_PAR_TIN1_TIN1 (0x0C) 1092#define MCF_GPIO_PAR_TIMER_PAR_TIN0_GPIO (0x00) 1093#define MCF_GPIO_PAR_TIMER_PAR_TIN0_TOUT0 (0x02) 1094#define MCF_GPIO_PAR_TIMER_PAR_TIN0_DREQ0 (0x01) 1095#define MCF_GPIO_PAR_TIMER_PAR_TIN0_TIN0 (0x03) 1096 1097/* Bit definitions and macros for MCF_GPIO_PAR_LCDDATA */ 1098#define MCF_GPIO_PAR_LCDDATA_PAR_LD7_0(x) (((x)&0x03)<<0) 1099#define MCF_GPIO_PAR_LCDDATA_PAR_LD15_8(x) (((x)&0x03)<<2) 1100#define MCF_GPIO_PAR_LCDDATA_PAR_LD16(x) (((x)&0x03)<<4) 1101#define MCF_GPIO_PAR_LCDDATA_PAR_LD17(x) (((x)&0x03)<<6) 1102 1103/* Bit definitions and macros for MCF_GPIO_PAR_LCDCTL */ 1104#define MCF_GPIO_PAR_LCDCTL_PAR_CLS (0x0001) 1105#define MCF_GPIO_PAR_LCDCTL_PAR_PS (0x0002) 1106#define MCF_GPIO_PAR_LCDCTL_PAR_REV (0x0004) 1107#define MCF_GPIO_PAR_LCDCTL_PAR_SPL_SPR (0x0008) 1108#define MCF_GPIO_PAR_LCDCTL_PAR_CONTRAST (0x0010) 1109#define MCF_GPIO_PAR_LCDCTL_PAR_LSCLK (0x0020) 1110#define MCF_GPIO_PAR_LCDCTL_PAR_LP_HSYNC (0x0040) 1111#define MCF_GPIO_PAR_LCDCTL_PAR_FLM_VSYNC (0x0080) 1112#define MCF_GPIO_PAR_LCDCTL_PAR_ACD_OE (0x0100) 1113 1114/* Bit definitions and macros for MCF_GPIO_PAR_IRQ */ 1115#define MCF_GPIO_PAR_IRQ_PAR_IRQ1(x) (((x)&0x0003)<<4) 1116#define MCF_GPIO_PAR_IRQ_PAR_IRQ2(x) (((x)&0x0003)<<6) 1117#define MCF_GPIO_PAR_IRQ_PAR_IRQ4(x) (((x)&0x0003)<<8) 1118#define MCF_GPIO_PAR_IRQ_PAR_IRQ5(x) (((x)&0x0003)<<10) 1119#define MCF_GPIO_PAR_IRQ_PAR_IRQ6(x) (((x)&0x0003)<<12) 1120 1121/* Bit definitions and macros for MCF_GPIO_MSCR_FLEXBUS */ 1122#define MCF_GPIO_MSCR_FLEXBUS_MSCR_ADDRCTL(x) (((x)&0x03)<<0) 1123#define MCF_GPIO_MSCR_FLEXBUS_MSCR_DLOWER(x) (((x)&0x03)<<2) 1124#define MCF_GPIO_MSCR_FLEXBUS_MSCR_DUPPER(x) (((x)&0x03)<<4) 1125 1126/* Bit definitions and macros for MCF_GPIO_MSCR_SDRAM */ 1127#define MCF_GPIO_MSCR_SDRAM_MSCR_SDRAM(x) (((x)&0x03)<<0) 1128#define MCF_GPIO_MSCR_SDRAM_MSCR_SDCLK(x) (((x)&0x03)<<2) 1129#define MCF_GPIO_MSCR_SDRAM_MSCR_SDCLKB(x) (((x)&0x03)<<4) 1130 1131/* Bit definitions and macros for MCF_GPIO_DSCR_I2C */ 1132#define MCF_GPIO_DSCR_I2C_I2C_DSE(x) (((x)&0x03)<<0) 1133 1134/* Bit definitions and macros for MCF_GPIO_DSCR_PWM */ 1135#define MCF_GPIO_DSCR_PWM_PWM_DSE(x) (((x)&0x03)<<0) 1136 1137/* Bit definitions and macros for MCF_GPIO_DSCR_FEC */ 1138#define MCF_GPIO_DSCR_FEC_FEC_DSE(x) (((x)&0x03)<<0) 1139 1140/* Bit definitions and macros for MCF_GPIO_DSCR_UART */ 1141#define MCF_GPIO_DSCR_UART_UART0_DSE(x) (((x)&0x03)<<0) 1142#define MCF_GPIO_DSCR_UART_UART1_DSE(x) (((x)&0x03)<<2) 1143 1144/* Bit definitions and macros for MCF_GPIO_DSCR_QSPI */ 1145#define MCF_GPIO_DSCR_QSPI_QSPI_DSE(x) (((x)&0x03)<<0) 1146 1147/* Bit definitions and macros for MCF_GPIO_DSCR_TIMER */ 1148#define MCF_GPIO_DSCR_TIMER_TIMER_DSE(x) (((x)&0x03)<<0) 1149 1150/* Bit definitions and macros for MCF_GPIO_DSCR_SSI */ 1151#define MCF_GPIO_DSCR_SSI_SSI_DSE(x) (((x)&0x03)<<0) 1152 1153/* Bit definitions and macros for MCF_GPIO_DSCR_LCD */ 1154#define MCF_GPIO_DSCR_LCD_LCD_DSE(x) (((x)&0x03)<<0) 1155 1156/* Bit definitions and macros for MCF_GPIO_DSCR_DEBUG */ 1157#define MCF_GPIO_DSCR_DEBUG_DEBUG_DSE(x) (((x)&0x03)<<0) 1158 1159/* Bit definitions and macros for MCF_GPIO_DSCR_CLKRST */ 1160#define MCF_GPIO_DSCR_CLKRST_CLKRST_DSE(x) (((x)&0x03)<<0) 1161 1162/* Bit definitions and macros for MCF_GPIO_DSCR_IRQ */ 1163#define MCF_GPIO_DSCR_IRQ_IRQ_DSE(x) (((x)&0x03)<<0) 1164 1165/* 1166 * Generic GPIO support 1167 */ 1168#define MCFGPIO_PODR MCFGPIO_PODR_FECH 1169#define MCFGPIO_PDDR MCFGPIO_PDDR_FECH 1170#define MCFGPIO_PPDR MCFGPIO_PPDSDR_FECH 1171#define MCFGPIO_SETR MCFGPIO_PPDSDR_FECH 1172#define MCFGPIO_CLRR MCFGPIO_PCLRR_FECH 1173 1174#define MCFGPIO_PIN_MAX 136 1175#define MCFGPIO_IRQ_MAX 8 1176#define MCFGPIO_IRQ_VECBASE MCFINT_VECBASE 1177 1178 1179/********************************************************************* 1180 * 1181 * Interrupt Controller (INTC) 1182 * 1183 *********************************************************************/ 1184 1185/* Register read/write macros */ 1186#define MCF_INTC0_IPRH MCF_REG32(0xFC048000) 1187#define MCF_INTC0_IPRL MCF_REG32(0xFC048004) 1188#define MCF_INTC0_IMRH MCF_REG32(0xFC048008) 1189#define MCF_INTC0_IMRL MCF_REG32(0xFC04800C) 1190#define MCF_INTC0_INTFRCH MCF_REG32(0xFC048010) 1191#define MCF_INTC0_INTFRCL MCF_REG32(0xFC048014) 1192#define MCF_INTC0_ICONFIG MCF_REG16(0xFC04801A) 1193#define MCF_INTC0_SIMR MCF_REG08(0xFC04801C) 1194#define MCF_INTC0_CIMR MCF_REG08(0xFC04801D) 1195#define MCF_INTC0_CLMASK MCF_REG08(0xFC04801E) 1196#define MCF_INTC0_SLMASK MCF_REG08(0xFC04801F) 1197#define MCF_INTC0_ICR0 MCF_REG08(0xFC048040) 1198#define MCF_INTC0_ICR1 MCF_REG08(0xFC048041) 1199#define MCF_INTC0_ICR2 MCF_REG08(0xFC048042) 1200#define MCF_INTC0_ICR3 MCF_REG08(0xFC048043) 1201#define MCF_INTC0_ICR4 MCF_REG08(0xFC048044) 1202#define MCF_INTC0_ICR5 MCF_REG08(0xFC048045) 1203#define MCF_INTC0_ICR6 MCF_REG08(0xFC048046) 1204#define MCF_INTC0_ICR7 MCF_REG08(0xFC048047) 1205#define MCF_INTC0_ICR8 MCF_REG08(0xFC048048) 1206#define MCF_INTC0_ICR9 MCF_REG08(0xFC048049) 1207#define MCF_INTC0_ICR10 MCF_REG08(0xFC04804A) 1208#define MCF_INTC0_ICR11 MCF_REG08(0xFC04804B) 1209#define MCF_INTC0_ICR12 MCF_REG08(0xFC04804C) 1210#define MCF_INTC0_ICR13 MCF_REG08(0xFC04804D) 1211#define MCF_INTC0_ICR14 MCF_REG08(0xFC04804E) 1212#define MCF_INTC0_ICR15 MCF_REG08(0xFC04804F) 1213#define MCF_INTC0_ICR16 MCF_REG08(0xFC048050) 1214#define MCF_INTC0_ICR17 MCF_REG08(0xFC048051) 1215#define MCF_INTC0_ICR18 MCF_REG08(0xFC048052) 1216#define MCF_INTC0_ICR19 MCF_REG08(0xFC048053) 1217#define MCF_INTC0_ICR20 MCF_REG08(0xFC048054) 1218#define MCF_INTC0_ICR21 MCF_REG08(0xFC048055) 1219#define MCF_INTC0_ICR22 MCF_REG08(0xFC048056) 1220#define MCF_INTC0_ICR23 MCF_REG08(0xFC048057) 1221#define MCF_INTC0_ICR24 MCF_REG08(0xFC048058) 1222#define MCF_INTC0_ICR25 MCF_REG08(0xFC048059) 1223#define MCF_INTC0_ICR26 MCF_REG08(0xFC04805A) 1224#define MCF_INTC0_ICR27 MCF_REG08(0xFC04805B) 1225#define MCF_INTC0_ICR28 MCF_REG08(0xFC04805C) 1226#define MCF_INTC0_ICR29 MCF_REG08(0xFC04805D) 1227#define MCF_INTC0_ICR30 MCF_REG08(0xFC04805E) 1228#define MCF_INTC0_ICR31 MCF_REG08(0xFC04805F) 1229#define MCF_INTC0_ICR32 MCF_REG08(0xFC048060) 1230#define MCF_INTC0_ICR33 MCF_REG08(0xFC048061) 1231#define MCF_INTC0_ICR34 MCF_REG08(0xFC048062) 1232#define MCF_INTC0_ICR35 MCF_REG08(0xFC048063) 1233#define MCF_INTC0_ICR36 MCF_REG08(0xFC048064) 1234#define MCF_INTC0_ICR37 MCF_REG08(0xFC048065) 1235#define MCF_INTC0_ICR38 MCF_REG08(0xFC048066) 1236#define MCF_INTC0_ICR39 MCF_REG08(0xFC048067) 1237#define MCF_INTC0_ICR40 MCF_REG08(0xFC048068) 1238#define MCF_INTC0_ICR41 MCF_REG08(0xFC048069) 1239#define MCF_INTC0_ICR42 MCF_REG08(0xFC04806A) 1240#define MCF_INTC0_ICR43 MCF_REG08(0xFC04806B) 1241#define MCF_INTC0_ICR44 MCF_REG08(0xFC04806C) 1242#define MCF_INTC0_ICR45 MCF_REG08(0xFC04806D) 1243#define MCF_INTC0_ICR46 MCF_REG08(0xFC04806E) 1244#define MCF_INTC0_ICR47 MCF_REG08(0xFC04806F) 1245#define MCF_INTC0_ICR48 MCF_REG08(0xFC048070) 1246#define MCF_INTC0_ICR49 MCF_REG08(0xFC048071) 1247#define MCF_INTC0_ICR50 MCF_REG08(0xFC048072) 1248#define MCF_INTC0_ICR51 MCF_REG08(0xFC048073) 1249#define MCF_INTC0_ICR52 MCF_REG08(0xFC048074) 1250#define MCF_INTC0_ICR53 MCF_REG08(0xFC048075) 1251#define MCF_INTC0_ICR54 MCF_REG08(0xFC048076) 1252#define MCF_INTC0_ICR55 MCF_REG08(0xFC048077) 1253#define MCF_INTC0_ICR56 MCF_REG08(0xFC048078) 1254#define MCF_INTC0_ICR57 MCF_REG08(0xFC048079) 1255#define MCF_INTC0_ICR58 MCF_REG08(0xFC04807A) 1256#define MCF_INTC0_ICR59 MCF_REG08(0xFC04807B) 1257#define MCF_INTC0_ICR60 MCF_REG08(0xFC04807C) 1258#define MCF_INTC0_ICR61 MCF_REG08(0xFC04807D) 1259#define MCF_INTC0_ICR62 MCF_REG08(0xFC04807E) 1260#define MCF_INTC0_ICR63 MCF_REG08(0xFC04807F) 1261#define MCF_INTC0_ICR(x) MCF_REG08(0xFC048040+((x)*0x001)) 1262#define MCF_INTC0_SWIACK MCF_REG08(0xFC0480E0) 1263#define MCF_INTC0_L1IACK MCF_REG08(0xFC0480E4) 1264#define MCF_INTC0_L2IACK MCF_REG08(0xFC0480E8) 1265#define MCF_INTC0_L3IACK MCF_REG08(0xFC0480EC) 1266#define MCF_INTC0_L4IACK MCF_REG08(0xFC0480F0) 1267#define MCF_INTC0_L5IACK MCF_REG08(0xFC0480F4) 1268#define MCF_INTC0_L6IACK MCF_REG08(0xFC0480F8) 1269#define MCF_INTC0_L7IACK MCF_REG08(0xFC0480FC) 1270#define MCF_INTC0_LIACK(x) MCF_REG08(0xFC0480E4+((x)*0x004)) 1271#define MCF_INTC1_IPRH MCF_REG32(0xFC04C000) 1272#define MCF_INTC1_IPRL MCF_REG32(0xFC04C004) 1273#define MCF_INTC1_IMRH MCF_REG32(0xFC04C008) 1274#define MCF_INTC1_IMRL MCF_REG32(0xFC04C00C) 1275#define MCF_INTC1_INTFRCH MCF_REG32(0xFC04C010) 1276#define MCF_INTC1_INTFRCL MCF_REG32(0xFC04C014) 1277#define MCF_INTC1_ICONFIG MCF_REG16(0xFC04C01A) 1278#define MCF_INTC1_SIMR MCF_REG08(0xFC04C01C) 1279#define MCF_INTC1_CIMR MCF_REG08(0xFC04C01D) 1280#define MCF_INTC1_CLMASK MCF_REG08(0xFC04C01E) 1281#define MCF_INTC1_SLMASK MCF_REG08(0xFC04C01F) 1282#define MCF_INTC1_ICR0 MCF_REG08(0xFC04C040) 1283#define MCF_INTC1_ICR1 MCF_REG08(0xFC04C041) 1284#define MCF_INTC1_ICR2 MCF_REG08(0xFC04C042) 1285#define MCF_INTC1_ICR3 MCF_REG08(0xFC04C043) 1286#define MCF_INTC1_ICR4 MCF_REG08(0xFC04C044) 1287#define MCF_INTC1_ICR5 MCF_REG08(0xFC04C045) 1288#define MCF_INTC1_ICR6 MCF_REG08(0xFC04C046) 1289#define MCF_INTC1_ICR7 MCF_REG08(0xFC04C047) 1290#define MCF_INTC1_ICR8 MCF_REG08(0xFC04C048) 1291#define MCF_INTC1_ICR9 MCF_REG08(0xFC04C049) 1292#define MCF_INTC1_ICR10 MCF_REG08(0xFC04C04A) 1293#define MCF_INTC1_ICR11 MCF_REG08(0xFC04C04B) 1294#define MCF_INTC1_ICR12 MCF_REG08(0xFC04C04C) 1295#define MCF_INTC1_ICR13 MCF_REG08(0xFC04C04D) 1296#define MCF_INTC1_ICR14 MCF_REG08(0xFC04C04E) 1297#define MCF_INTC1_ICR15 MCF_REG08(0xFC04C04F) 1298#define MCF_INTC1_ICR16 MCF_REG08(0xFC04C050) 1299#define MCF_INTC1_ICR17 MCF_REG08(0xFC04C051) 1300#define MCF_INTC1_ICR18 MCF_REG08(0xFC04C052) 1301#define MCF_INTC1_ICR19 MCF_REG08(0xFC04C053) 1302#define MCF_INTC1_ICR20 MCF_REG08(0xFC04C054) 1303#define MCF_INTC1_ICR21 MCF_REG08(0xFC04C055) 1304#define MCF_INTC1_ICR22 MCF_REG08(0xFC04C056) 1305#define MCF_INTC1_ICR23 MCF_REG08(0xFC04C057) 1306#define MCF_INTC1_ICR24 MCF_REG08(0xFC04C058) 1307#define MCF_INTC1_ICR25 MCF_REG08(0xFC04C059) 1308#define MCF_INTC1_ICR26 MCF_REG08(0xFC04C05A) 1309#define MCF_INTC1_ICR27 MCF_REG08(0xFC04C05B) 1310#define MCF_INTC1_ICR28 MCF_REG08(0xFC04C05C) 1311#define MCF_INTC1_ICR29 MCF_REG08(0xFC04C05D) 1312#define MCF_INTC1_ICR30 MCF_REG08(0xFC04C05E) 1313#define MCF_INTC1_ICR31 MCF_REG08(0xFC04C05F) 1314#define MCF_INTC1_ICR32 MCF_REG08(0xFC04C060) 1315#define MCF_INTC1_ICR33 MCF_REG08(0xFC04C061) 1316#define MCF_INTC1_ICR34 MCF_REG08(0xFC04C062) 1317#define MCF_INTC1_ICR35 MCF_REG08(0xFC04C063) 1318#define MCF_INTC1_ICR36 MCF_REG08(0xFC04C064) 1319#define MCF_INTC1_ICR37 MCF_REG08(0xFC04C065) 1320#define MCF_INTC1_ICR38 MCF_REG08(0xFC04C066) 1321#define MCF_INTC1_ICR39 MCF_REG08(0xFC04C067) 1322#define MCF_INTC1_ICR40 MCF_REG08(0xFC04C068) 1323#define MCF_INTC1_ICR41 MCF_REG08(0xFC04C069) 1324#define MCF_INTC1_ICR42 MCF_REG08(0xFC04C06A) 1325#define MCF_INTC1_ICR43 MCF_REG08(0xFC04C06B) 1326#define MCF_INTC1_ICR44 MCF_REG08(0xFC04C06C) 1327#define MCF_INTC1_ICR45 MCF_REG08(0xFC04C06D) 1328#define MCF_INTC1_ICR46 MCF_REG08(0xFC04C06E) 1329#define MCF_INTC1_ICR47 MCF_REG08(0xFC04C06F) 1330#define MCF_INTC1_ICR48 MCF_REG08(0xFC04C070) 1331#define MCF_INTC1_ICR49 MCF_REG08(0xFC04C071) 1332#define MCF_INTC1_ICR50 MCF_REG08(0xFC04C072) 1333#define MCF_INTC1_ICR51 MCF_REG08(0xFC04C073) 1334#define MCF_INTC1_ICR52 MCF_REG08(0xFC04C074) 1335#define MCF_INTC1_ICR53 MCF_REG08(0xFC04C075) 1336#define MCF_INTC1_ICR54 MCF_REG08(0xFC04C076) 1337#define MCF_INTC1_ICR55 MCF_REG08(0xFC04C077) 1338#define MCF_INTC1_ICR56 MCF_REG08(0xFC04C078) 1339#define MCF_INTC1_ICR57 MCF_REG08(0xFC04C079) 1340#define MCF_INTC1_ICR58 MCF_REG08(0xFC04C07A) 1341#define MCF_INTC1_ICR59 MCF_REG08(0xFC04C07B) 1342#define MCF_INTC1_ICR60 MCF_REG08(0xFC04C07C) 1343#define MCF_INTC1_ICR61 MCF_REG08(0xFC04C07D) 1344#define MCF_INTC1_ICR62 MCF_REG08(0xFC04C07E) 1345#define MCF_INTC1_ICR63 MCF_REG08(0xFC04C07F) 1346#define MCF_INTC1_ICR(x) MCF_REG08(0xFC04C040+((x)*0x001)) 1347#define MCF_INTC1_SWIACK MCF_REG08(0xFC04C0E0) 1348#define MCF_INTC1_L1IACK MCF_REG08(0xFC04C0E4) 1349#define MCF_INTC1_L2IACK MCF_REG08(0xFC04C0E8) 1350#define MCF_INTC1_L3IACK MCF_REG08(0xFC04C0EC) 1351#define MCF_INTC1_L4IACK MCF_REG08(0xFC04C0F0) 1352#define MCF_INTC1_L5IACK MCF_REG08(0xFC04C0F4) 1353#define MCF_INTC1_L6IACK MCF_REG08(0xFC04C0F8) 1354#define MCF_INTC1_L7IACK MCF_REG08(0xFC04C0FC) 1355#define MCF_INTC1_LIACK(x) MCF_REG08(0xFC04C0E4+((x)*0x004)) 1356#define MCF_INTC_IPRH(x) MCF_REG32(0xFC048000+((x)*0x4000)) 1357#define MCF_INTC_IPRL(x) MCF_REG32(0xFC048004+((x)*0x4000)) 1358#define MCF_INTC_IMRH(x) MCF_REG32(0xFC048008+((x)*0x4000)) 1359#define MCF_INTC_IMRL(x) MCF_REG32(0xFC04800C+((x)*0x4000)) 1360#define MCF_INTC_INTFRCH(x) MCF_REG32(0xFC048010+((x)*0x4000)) 1361#define MCF_INTC_INTFRCL(x) MCF_REG32(0xFC048014+((x)*0x4000)) 1362#define MCF_INTC_ICONFIG(x) MCF_REG16(0xFC04801A+((x)*0x4000)) 1363#define MCF_INTC_SIMR(x) MCF_REG08(0xFC04801C+((x)*0x4000)) 1364#define MCF_INTC_CIMR(x) MCF_REG08(0xFC04801D+((x)*0x4000)) 1365#define MCF_INTC_CLMASK(x) MCF_REG08(0xFC04801E+((x)*0x4000)) 1366#define MCF_INTC_SLMASK(x) MCF_REG08(0xFC04801F+((x)*0x4000)) 1367#define MCF_INTC_ICR0(x) MCF_REG08(0xFC048040+((x)*0x4000)) 1368#define MCF_INTC_ICR1(x) MCF_REG08(0xFC048041+((x)*0x4000)) 1369#define MCF_INTC_ICR2(x) MCF_REG08(0xFC048042+((x)*0x4000)) 1370#define MCF_INTC_ICR3(x) MCF_REG08(0xFC048043+((x)*0x4000)) 1371#define MCF_INTC_ICR4(x) MCF_REG08(0xFC048044+((x)*0x4000)) 1372#define MCF_INTC_ICR5(x) MCF_REG08(0xFC048045+((x)*0x4000)) 1373#define MCF_INTC_ICR6(x) MCF_REG08(0xFC048046+((x)*0x4000)) 1374#define MCF_INTC_ICR7(x) MCF_REG08(0xFC048047+((x)*0x4000)) 1375#define MCF_INTC_ICR8(x) MCF_REG08(0xFC048048+((x)*0x4000)) 1376#define MCF_INTC_ICR9(x) MCF_REG08(0xFC048049+((x)*0x4000)) 1377#define MCF_INTC_ICR10(x) MCF_REG08(0xFC04804A+((x)*0x4000)) 1378#define MCF_INTC_ICR11(x) MCF_REG08(0xFC04804B+((x)*0x4000)) 1379#define MCF_INTC_ICR12(x) MCF_REG08(0xFC04804C+((x)*0x4000)) 1380#define MCF_INTC_ICR13(x) MCF_REG08(0xFC04804D+((x)*0x4000)) 1381#define MCF_INTC_ICR14(x) MCF_REG08(0xFC04804E+((x)*0x4000)) 1382#define MCF_INTC_ICR15(x) MCF_REG08(0xFC04804F+((x)*0x4000)) 1383#define MCF_INTC_ICR16(x) MCF_REG08(0xFC048050+((x)*0x4000)) 1384#define MCF_INTC_ICR17(x) MCF_REG08(0xFC048051+((x)*0x4000)) 1385#define MCF_INTC_ICR18(x) MCF_REG08(0xFC048052+((x)*0x4000)) 1386#define MCF_INTC_ICR19(x) MCF_REG08(0xFC048053+((x)*0x4000)) 1387#define MCF_INTC_ICR20(x) MCF_REG08(0xFC048054+((x)*0x4000)) 1388#define MCF_INTC_ICR21(x) MCF_REG08(0xFC048055+((x)*0x4000)) 1389#define MCF_INTC_ICR22(x) MCF_REG08(0xFC048056+((x)*0x4000)) 1390#define MCF_INTC_ICR23(x) MCF_REG08(0xFC048057+((x)*0x4000)) 1391#define MCF_INTC_ICR24(x) MCF_REG08(0xFC048058+((x)*0x4000)) 1392#define MCF_INTC_ICR25(x) MCF_REG08(0xFC048059+((x)*0x4000)) 1393#define MCF_INTC_ICR26(x) MCF_REG08(0xFC04805A+((x)*0x4000)) 1394#define MCF_INTC_ICR27(x) MCF_REG08(0xFC04805B+((x)*0x4000)) 1395#define MCF_INTC_ICR28(x) MCF_REG08(0xFC04805C+((x)*0x4000)) 1396#define MCF_INTC_ICR29(x) MCF_REG08(0xFC04805D+((x)*0x4000)) 1397#define MCF_INTC_ICR30(x) MCF_REG08(0xFC04805E+((x)*0x4000)) 1398#define MCF_INTC_ICR31(x) MCF_REG08(0xFC04805F+((x)*0x4000)) 1399#define MCF_INTC_ICR32(x) MCF_REG08(0xFC048060+((x)*0x4000)) 1400#define MCF_INTC_ICR33(x) MCF_REG08(0xFC048061+((x)*0x4000)) 1401#define MCF_INTC_ICR34(x) MCF_REG08(0xFC048062+((x)*0x4000)) 1402#define MCF_INTC_ICR35(x) MCF_REG08(0xFC048063+((x)*0x4000)) 1403#define MCF_INTC_ICR36(x) MCF_REG08(0xFC048064+((x)*0x4000)) 1404#define MCF_INTC_ICR37(x) MCF_REG08(0xFC048065+((x)*0x4000)) 1405#define MCF_INTC_ICR38(x) MCF_REG08(0xFC048066+((x)*0x4000)) 1406#define MCF_INTC_ICR39(x) MCF_REG08(0xFC048067+((x)*0x4000)) 1407#define MCF_INTC_ICR40(x) MCF_REG08(0xFC048068+((x)*0x4000)) 1408#define MCF_INTC_ICR41(x) MCF_REG08(0xFC048069+((x)*0x4000)) 1409#define MCF_INTC_ICR42(x) MCF_REG08(0xFC04806A+((x)*0x4000)) 1410#define MCF_INTC_ICR43(x) MCF_REG08(0xFC04806B+((x)*0x4000)) 1411#define MCF_INTC_ICR44(x) MCF_REG08(0xFC04806C+((x)*0x4000)) 1412#define MCF_INTC_ICR45(x) MCF_REG08(0xFC04806D+((x)*0x4000)) 1413#define MCF_INTC_ICR46(x) MCF_REG08(0xFC04806E+((x)*0x4000)) 1414#define MCF_INTC_ICR47(x) MCF_REG08(0xFC04806F+((x)*0x4000)) 1415#define MCF_INTC_ICR48(x) MCF_REG08(0xFC048070+((x)*0x4000)) 1416#define MCF_INTC_ICR49(x) MCF_REG08(0xFC048071+((x)*0x4000)) 1417#define MCF_INTC_ICR50(x) MCF_REG08(0xFC048072+((x)*0x4000)) 1418#define MCF_INTC_ICR51(x) MCF_REG08(0xFC048073+((x)*0x4000)) 1419#define MCF_INTC_ICR52(x) MCF_REG08(0xFC048074+((x)*0x4000)) 1420#define MCF_INTC_ICR53(x) MCF_REG08(0xFC048075+((x)*0x4000)) 1421#define MCF_INTC_ICR54(x) MCF_REG08(0xFC048076+((x)*0x4000)) 1422#define MCF_INTC_ICR55(x) MCF_REG08(0xFC048077+((x)*0x4000)) 1423#define MCF_INTC_ICR56(x) MCF_REG08(0xFC048078+((x)*0x4000)) 1424#define MCF_INTC_ICR57(x) MCF_REG08(0xFC048079+((x)*0x4000)) 1425#define MCF_INTC_ICR58(x) MCF_REG08(0xFC04807A+((x)*0x4000)) 1426#define MCF_INTC_ICR59(x) MCF_REG08(0xFC04807B+((x)*0x4000)) 1427#define MCF_INTC_ICR60(x) MCF_REG08(0xFC04807C+((x)*0x4000)) 1428#define MCF_INTC_ICR61(x) MCF_REG08(0xFC04807D+((x)*0x4000)) 1429#define MCF_INTC_ICR62(x) MCF_REG08(0xFC04807E+((x)*0x4000)) 1430#define MCF_INTC_ICR63(x) MCF_REG08(0xFC04807F+((x)*0x4000)) 1431#define MCF_INTC_SWIACK(x) MCF_REG08(0xFC0480E0+((x)*0x4000)) 1432#define MCF_INTC_L1IACK(x) MCF_REG08(0xFC0480E4+((x)*0x4000)) 1433#define MCF_INTC_L2IACK(x) MCF_REG08(0xFC0480E8+((x)*0x4000)) 1434#define MCF_INTC_L3IACK(x) MCF_REG08(0xFC0480EC+((x)*0x4000)) 1435#define MCF_INTC_L4IACK(x) MCF_REG08(0xFC0480F0+((x)*0x4000)) 1436#define MCF_INTC_L5IACK(x) MCF_REG08(0xFC0480F4+((x)*0x4000)) 1437#define MCF_INTC_L6IACK(x) MCF_REG08(0xFC0480F8+((x)*0x4000)) 1438#define MCF_INTC_L7IACK(x) MCF_REG08(0xFC0480FC+((x)*0x4000)) 1439 1440/* Bit definitions and macros for MCF_INTC_IPRH */ 1441#define MCF_INTC_IPRH_INT32 (0x00000001) 1442#define MCF_INTC_IPRH_INT33 (0x00000002) 1443#define MCF_INTC_IPRH_INT34 (0x00000004) 1444#define MCF_INTC_IPRH_INT35 (0x00000008) 1445#define MCF_INTC_IPRH_INT36 (0x00000010) 1446#define MCF_INTC_IPRH_INT37 (0x00000020) 1447#define MCF_INTC_IPRH_INT38 (0x00000040) 1448#define MCF_INTC_IPRH_INT39 (0x00000080) 1449#define MCF_INTC_IPRH_INT40 (0x00000100) 1450#define MCF_INTC_IPRH_INT41 (0x00000200) 1451#define MCF_INTC_IPRH_INT42 (0x00000400) 1452#define MCF_INTC_IPRH_INT43 (0x00000800) 1453#define MCF_INTC_IPRH_INT44 (0x00001000) 1454#define MCF_INTC_IPRH_INT45 (0x00002000) 1455#define MCF_INTC_IPRH_INT46 (0x00004000) 1456#define MCF_INTC_IPRH_INT47 (0x00008000) 1457#define MCF_INTC_IPRH_INT48 (0x00010000) 1458#define MCF_INTC_IPRH_INT49 (0x00020000) 1459#define MCF_INTC_IPRH_INT50 (0x00040000) 1460#define MCF_INTC_IPRH_INT51 (0x00080000) 1461#define MCF_INTC_IPRH_INT52 (0x00100000) 1462#define MCF_INTC_IPRH_INT53 (0x00200000) 1463#define MCF_INTC_IPRH_INT54 (0x00400000) 1464#define MCF_INTC_IPRH_INT55 (0x00800000) 1465#define MCF_INTC_IPRH_INT56 (0x01000000) 1466#define MCF_INTC_IPRH_INT57 (0x02000000) 1467#define MCF_INTC_IPRH_INT58 (0x04000000) 1468#define MCF_INTC_IPRH_INT59 (0x08000000) 1469#define MCF_INTC_IPRH_INT60 (0x10000000) 1470#define MCF_INTC_IPRH_INT61 (0x20000000) 1471#define MCF_INTC_IPRH_INT62 (0x40000000) 1472#define MCF_INTC_IPRH_INT63 (0x80000000) 1473 1474/* Bit definitions and macros for MCF_INTC_IPRL */ 1475#define MCF_INTC_IPRL_INT0 (0x00000001) 1476#define MCF_INTC_IPRL_INT1 (0x00000002) 1477#define MCF_INTC_IPRL_INT2 (0x00000004) 1478#define MCF_INTC_IPRL_INT3 (0x00000008) 1479#define MCF_INTC_IPRL_INT4 (0x00000010) 1480#define MCF_INTC_IPRL_INT5 (0x00000020) 1481#define MCF_INTC_IPRL_INT6 (0x00000040) 1482#define MCF_INTC_IPRL_INT7 (0x00000080) 1483#define MCF_INTC_IPRL_INT8 (0x00000100) 1484#define MCF_INTC_IPRL_INT9 (0x00000200) 1485#define MCF_INTC_IPRL_INT10 (0x00000400) 1486#define MCF_INTC_IPRL_INT11 (0x00000800) 1487#define MCF_INTC_IPRL_INT12 (0x00001000) 1488#define MCF_INTC_IPRL_INT13 (0x00002000) 1489#define MCF_INTC_IPRL_INT14 (0x00004000) 1490#define MCF_INTC_IPRL_INT15 (0x00008000) 1491#define MCF_INTC_IPRL_INT16 (0x00010000) 1492#define MCF_INTC_IPRL_INT17 (0x00020000) 1493#define MCF_INTC_IPRL_INT18 (0x00040000) 1494#define MCF_INTC_IPRL_INT19 (0x00080000) 1495#define MCF_INTC_IPRL_INT20 (0x00100000) 1496#define MCF_INTC_IPRL_INT21 (0x00200000) 1497#define MCF_INTC_IPRL_INT22 (0x00400000) 1498#define MCF_INTC_IPRL_INT23 (0x00800000) 1499#define MCF_INTC_IPRL_INT24 (0x01000000) 1500#define MCF_INTC_IPRL_INT25 (0x02000000) 1501#define MCF_INTC_IPRL_INT26 (0x04000000) 1502#define MCF_INTC_IPRL_INT27 (0x08000000) 1503#define MCF_INTC_IPRL_INT28 (0x10000000) 1504#define MCF_INTC_IPRL_INT29 (0x20000000) 1505#define MCF_INTC_IPRL_INT30 (0x40000000) 1506#define MCF_INTC_IPRL_INT31 (0x80000000) 1507 1508/* Bit definitions and macros for MCF_INTC_IMRH */ 1509#define MCF_INTC_IMRH_INT_MASK32 (0x00000001) 1510#define MCF_INTC_IMRH_INT_MASK33 (0x00000002) 1511#define MCF_INTC_IMRH_INT_MASK34 (0x00000004) 1512#define MCF_INTC_IMRH_INT_MASK35 (0x00000008) 1513#define MCF_INTC_IMRH_INT_MASK36 (0x00000010) 1514#define MCF_INTC_IMRH_INT_MASK37 (0x00000020) 1515#define MCF_INTC_IMRH_INT_MASK38 (0x00000040) 1516#define MCF_INTC_IMRH_INT_MASK39 (0x00000080) 1517#define MCF_INTC_IMRH_INT_MASK40 (0x00000100) 1518#define MCF_INTC_IMRH_INT_MASK41 (0x00000200) 1519#define MCF_INTC_IMRH_INT_MASK42 (0x00000400) 1520#define MCF_INTC_IMRH_INT_MASK43 (0x00000800) 1521#define MCF_INTC_IMRH_INT_MASK44 (0x00001000) 1522#define MCF_INTC_IMRH_INT_MASK45 (0x00002000) 1523#define MCF_INTC_IMRH_INT_MASK46 (0x00004000) 1524#define MCF_INTC_IMRH_INT_MASK47 (0x00008000) 1525#define MCF_INTC_IMRH_INT_MASK48 (0x00010000) 1526#define MCF_INTC_IMRH_INT_MASK49 (0x00020000) 1527#define MCF_INTC_IMRH_INT_MASK50 (0x00040000) 1528#define MCF_INTC_IMRH_INT_MASK51 (0x00080000) 1529#define MCF_INTC_IMRH_INT_MASK52 (0x00100000) 1530#define MCF_INTC_IMRH_INT_MASK53 (0x00200000) 1531#define MCF_INTC_IMRH_INT_MASK54 (0x00400000) 1532#define MCF_INTC_IMRH_INT_MASK55 (0x00800000) 1533#define MCF_INTC_IMRH_INT_MASK56 (0x01000000) 1534#define MCF_INTC_IMRH_INT_MASK57 (0x02000000) 1535#define MCF_INTC_IMRH_INT_MASK58 (0x04000000) 1536#define MCF_INTC_IMRH_INT_MASK59 (0x08000000) 1537#define MCF_INTC_IMRH_INT_MASK60 (0x10000000) 1538#define MCF_INTC_IMRH_INT_MASK61 (0x20000000) 1539#define MCF_INTC_IMRH_INT_MASK62 (0x40000000) 1540#define MCF_INTC_IMRH_INT_MASK63 (0x80000000) 1541 1542/* Bit definitions and macros for MCF_INTC_IMRL */ 1543#define MCF_INTC_IMRL_INT_MASK0 (0x00000001) 1544#define MCF_INTC_IMRL_INT_MASK1 (0x00000002) 1545#define MCF_INTC_IMRL_INT_MASK2 (0x00000004) 1546#define MCF_INTC_IMRL_INT_MASK3 (0x00000008) 1547#define MCF_INTC_IMRL_INT_MASK4 (0x00000010) 1548#define MCF_INTC_IMRL_INT_MASK5 (0x00000020) 1549#define MCF_INTC_IMRL_INT_MASK6 (0x00000040) 1550#define MCF_INTC_IMRL_INT_MASK7 (0x00000080) 1551#define MCF_INTC_IMRL_INT_MASK8 (0x00000100) 1552#define MCF_INTC_IMRL_INT_MASK9 (0x00000200) 1553#define MCF_INTC_IMRL_INT_MASK10 (0x00000400) 1554#define MCF_INTC_IMRL_INT_MASK11 (0x00000800) 1555#define MCF_INTC_IMRL_INT_MASK12 (0x00001000) 1556#define MCF_INTC_IMRL_INT_MASK13 (0x00002000) 1557#define MCF_INTC_IMRL_INT_MASK14 (0x00004000) 1558#define MCF_INTC_IMRL_INT_MASK15 (0x00008000) 1559#define MCF_INTC_IMRL_INT_MASK16 (0x00010000) 1560#define MCF_INTC_IMRL_INT_MASK17 (0x00020000) 1561#define MCF_INTC_IMRL_INT_MASK18 (0x00040000) 1562#define MCF_INTC_IMRL_INT_MASK19 (0x00080000) 1563#define MCF_INTC_IMRL_INT_MASK20 (0x00100000) 1564#define MCF_INTC_IMRL_INT_MASK21 (0x00200000) 1565#define MCF_INTC_IMRL_INT_MASK22 (0x00400000) 1566#define MCF_INTC_IMRL_INT_MASK23 (0x00800000) 1567#define MCF_INTC_IMRL_INT_MASK24 (0x01000000) 1568#define MCF_INTC_IMRL_INT_MASK25 (0x02000000) 1569#define MCF_INTC_IMRL_INT_MASK26 (0x04000000) 1570#define MCF_INTC_IMRL_INT_MASK27 (0x08000000) 1571#define MCF_INTC_IMRL_INT_MASK28 (0x10000000) 1572#define MCF_INTC_IMRL_INT_MASK29 (0x20000000) 1573#define MCF_INTC_IMRL_INT_MASK30 (0x40000000) 1574#define MCF_INTC_IMRL_INT_MASK31 (0x80000000) 1575 1576/* Bit definitions and macros for MCF_INTC_INTFRCH */ 1577#define MCF_INTC_INTFRCH_INTFRC32 (0x00000001) 1578#define MCF_INTC_INTFRCH_INTFRC33 (0x00000002) 1579#define MCF_INTC_INTFRCH_INTFRC34 (0x00000004) 1580#define MCF_INTC_INTFRCH_INTFRC35 (0x00000008) 1581#define MCF_INTC_INTFRCH_INTFRC36 (0x00000010) 1582#define MCF_INTC_INTFRCH_INTFRC37 (0x00000020) 1583#define MCF_INTC_INTFRCH_INTFRC38 (0x00000040) 1584#define MCF_INTC_INTFRCH_INTFRC39 (0x00000080) 1585#define MCF_INTC_INTFRCH_INTFRC40 (0x00000100) 1586#define MCF_INTC_INTFRCH_INTFRC41 (0x00000200) 1587#define MCF_INTC_INTFRCH_INTFRC42 (0x00000400) 1588#define MCF_INTC_INTFRCH_INTFRC43 (0x00000800) 1589#define MCF_INTC_INTFRCH_INTFRC44 (0x00001000) 1590#define MCF_INTC_INTFRCH_INTFRC45 (0x00002000) 1591#define MCF_INTC_INTFRCH_INTFRC46 (0x00004000) 1592#define MCF_INTC_INTFRCH_INTFRC47 (0x00008000) 1593#define MCF_INTC_INTFRCH_INTFRC48 (0x00010000) 1594#define MCF_INTC_INTFRCH_INTFRC49 (0x00020000) 1595#define MCF_INTC_INTFRCH_INTFRC50 (0x00040000) 1596#define MCF_INTC_INTFRCH_INTFRC51 (0x00080000) 1597#define MCF_INTC_INTFRCH_INTFRC52 (0x00100000) 1598#define MCF_INTC_INTFRCH_INTFRC53 (0x00200000) 1599#define MCF_INTC_INTFRCH_INTFRC54 (0x00400000) 1600#define MCF_INTC_INTFRCH_INTFRC55 (0x00800000) 1601#define MCF_INTC_INTFRCH_INTFRC56 (0x01000000) 1602#define MCF_INTC_INTFRCH_INTFRC57 (0x02000000) 1603#define MCF_INTC_INTFRCH_INTFRC58 (0x04000000) 1604#define MCF_INTC_INTFRCH_INTFRC59 (0x08000000) 1605#define MCF_INTC_INTFRCH_INTFRC60 (0x10000000) 1606#define MCF_INTC_INTFRCH_INTFRC61 (0x20000000) 1607#define MCF_INTC_INTFRCH_INTFRC62 (0x40000000) 1608#define MCF_INTC_INTFRCH_INTFRC63 (0x80000000) 1609 1610/* Bit definitions and macros for MCF_INTC_INTFRCL */ 1611#define MCF_INTC_INTFRCL_INTFRC0 (0x00000001) 1612#define MCF_INTC_INTFRCL_INTFRC1 (0x00000002) 1613#define MCF_INTC_INTFRCL_INTFRC2 (0x00000004) 1614#define MCF_INTC_INTFRCL_INTFRC3 (0x00000008) 1615#define MCF_INTC_INTFRCL_INTFRC4 (0x00000010) 1616#define MCF_INTC_INTFRCL_INTFRC5 (0x00000020) 1617#define MCF_INTC_INTFRCL_INTFRC6 (0x00000040) 1618#define MCF_INTC_INTFRCL_INTFRC7 (0x00000080) 1619#define MCF_INTC_INTFRCL_INTFRC8 (0x00000100) 1620#define MCF_INTC_INTFRCL_INTFRC9 (0x00000200) 1621#define MCF_INTC_INTFRCL_INTFRC10 (0x00000400) 1622#define MCF_INTC_INTFRCL_INTFRC11 (0x00000800) 1623#define MCF_INTC_INTFRCL_INTFRC12 (0x00001000) 1624#define MCF_INTC_INTFRCL_INTFRC13 (0x00002000) 1625#define MCF_INTC_INTFRCL_INTFRC14 (0x00004000) 1626#define MCF_INTC_INTFRCL_INTFRC15 (0x00008000) 1627#define MCF_INTC_INTFRCL_INTFRC16 (0x00010000) 1628#define MCF_INTC_INTFRCL_INTFRC17 (0x00020000) 1629#define MCF_INTC_INTFRCL_INTFRC18 (0x00040000) 1630#define MCF_INTC_INTFRCL_INTFRC19 (0x00080000) 1631#define MCF_INTC_INTFRCL_INTFRC20 (0x00100000) 1632#define MCF_INTC_INTFRCL_INTFRC21 (0x00200000) 1633#define MCF_INTC_INTFRCL_INTFRC22 (0x00400000) 1634#define MCF_INTC_INTFRCL_INTFRC23 (0x00800000) 1635#define MCF_INTC_INTFRCL_INTFRC24 (0x01000000) 1636#define MCF_INTC_INTFRCL_INTFRC25 (0x02000000) 1637#define MCF_INTC_INTFRCL_INTFRC26 (0x04000000) 1638#define MCF_INTC_INTFRCL_INTFRC27 (0x08000000) 1639#define MCF_INTC_INTFRCL_INTFRC28 (0x10000000) 1640#define MCF_INTC_INTFRCL_INTFRC29 (0x20000000) 1641#define MCF_INTC_INTFRCL_INTFRC30 (0x40000000) 1642#define MCF_INTC_INTFRCL_INTFRC31 (0x80000000) 1643 1644/* Bit definitions and macros for MCF_INTC_ICONFIG */ 1645#define MCF_INTC_ICONFIG_EMASK (0x0020) 1646#define MCF_INTC_ICONFIG_ELVLPRI1 (0x0200) 1647#define MCF_INTC_ICONFIG_ELVLPRI2 (0x0400) 1648#define MCF_INTC_ICONFIG_ELVLPRI3 (0x0800) 1649#define MCF_INTC_ICONFIG_ELVLPRI4 (0x1000) 1650#define MCF_INTC_ICONFIG_ELVLPRI5 (0x2000) 1651#define MCF_INTC_ICONFIG_ELVLPRI6 (0x4000) 1652#define MCF_INTC_ICONFIG_ELVLPRI7 (0x8000) 1653 1654/* Bit definitions and macros for MCF_INTC_SIMR */ 1655#define MCF_INTC_SIMR_SIMR(x) (((x)&0x7F)<<0) 1656 1657/* Bit definitions and macros for MCF_INTC_CIMR */ 1658#define MCF_INTC_CIMR_CIMR(x) (((x)&0x7F)<<0) 1659 1660/* Bit definitions and macros for MCF_INTC_CLMASK */ 1661#define MCF_INTC_CLMASK_CLMASK(x) (((x)&0x0F)<<0) 1662 1663/* Bit definitions and macros for MCF_INTC_SLMASK */ 1664#define MCF_INTC_SLMASK_SLMASK(x) (((x)&0x0F)<<0) 1665 1666/* Bit definitions and macros for MCF_INTC_ICR */ 1667#define MCF_INTC_ICR_IL(x) (((x)&0x07)<<0) 1668 1669/* Bit definitions and macros for MCF_INTC_SWIACK */ 1670#define MCF_INTC_SWIACK_VECTOR(x) (((x)&0xFF)<<0) 1671 1672/* Bit definitions and macros for MCF_INTC_LIACK */ 1673#define MCF_INTC_LIACK_VECTOR(x) (((x)&0xFF)<<0) 1674 1675/********************************************************************/ 1676/********************************************************************* 1677* 1678* LCD Controller (LCDC) 1679* 1680*********************************************************************/ 1681 1682/* Register read/write macros */ 1683#define MCF_LCDC_LSSAR MCF_REG32(0xFC0AC000) 1684#define MCF_LCDC_LSR MCF_REG32(0xFC0AC004) 1685#define MCF_LCDC_LVPWR MCF_REG32(0xFC0AC008) 1686#define MCF_LCDC_LCPR MCF_REG32(0xFC0AC00C) 1687#define MCF_LCDC_LCWHBR MCF_REG32(0xFC0AC010) 1688#define MCF_LCDC_LCCMR MCF_REG32(0xFC0AC014) 1689#define MCF_LCDC_LPCR MCF_REG32(0xFC0AC018) 1690#define MCF_LCDC_LHCR MCF_REG32(0xFC0AC01C) 1691#define MCF_LCDC_LVCR MCF_REG32(0xFC0AC020) 1692#define MCF_LCDC_LPOR MCF_REG32(0xFC0AC024) 1693#define MCF_LCDC_LSCR MCF_REG32(0xFC0AC028) 1694#define MCF_LCDC_LPCCR MCF_REG32(0xFC0AC02C) 1695#define MCF_LCDC_LDCR MCF_REG32(0xFC0AC030) 1696#define MCF_LCDC_LRMCR MCF_REG32(0xFC0AC034) 1697#define MCF_LCDC_LICR MCF_REG32(0xFC0AC038) 1698#define MCF_LCDC_LIER MCF_REG32(0xFC0AC03C) 1699#define MCF_LCDC_LISR MCF_REG32(0xFC0AC040) 1700#define MCF_LCDC_LGWSAR MCF_REG32(0xFC0AC050) 1701#define MCF_LCDC_LGWSR MCF_REG32(0xFC0AC054) 1702#define MCF_LCDC_LGWVPWR MCF_REG32(0xFC0AC058) 1703#define MCF_LCDC_LGWPOR MCF_REG32(0xFC0AC05C) 1704#define MCF_LCDC_LGWPR MCF_REG32(0xFC0AC060) 1705#define MCF_LCDC_LGWCR MCF_REG32(0xFC0AC064) 1706#define MCF_LCDC_LGWDCR MCF_REG32(0xFC0AC068) 1707#define MCF_LCDC_BPLUT_BASE MCF_REG32(0xFC0AC800) 1708#define MCF_LCDC_GWLUT_BASE MCF_REG32(0xFC0ACC00) 1709 1710/* Bit definitions and macros for MCF_LCDC_LSSAR */ 1711#define MCF_LCDC_LSSAR_SSA(x) (((x)&0x3FFFFFFF)<<2) 1712 1713/* Bit definitions and macros for MCF_LCDC_LSR */ 1714#define MCF_LCDC_LSR_YMAX(x) (((x)&0x000003FF)<<0) 1715#define MCF_LCDC_LSR_XMAX(x) (((x)&0x0000003F)<<20) 1716 1717/* Bit definitions and macros for MCF_LCDC_LVPWR */ 1718#define MCF_LCDC_LVPWR_VPW(x) (((x)&0x000003FF)<<0) 1719 1720/* Bit definitions and macros for MCF_LCDC_LCPR */ 1721#define MCF_LCDC_LCPR_CYP(x) (((x)&0x000003FF)<<0) 1722#define MCF_LCDC_LCPR_CXP(x) (((x)&0x000003FF)<<16) 1723#define MCF_LCDC_LCPR_OP (0x10000000) 1724#define MCF_LCDC_LCPR_CC(x) (((x)&0x00000003)<<30) 1725#define MCF_LCDC_LCPR_CC_TRANSPARENT (0x00000000) 1726#define MCF_LCDC_LCPR_CC_OR (0x40000000) 1727#define MCF_LCDC_LCPR_CC_XOR (0x80000000) 1728#define MCF_LCDC_LCPR_CC_AND (0xC0000000) 1729#define MCF_LCDC_LCPR_OP_ON (0x10000000) 1730#define MCF_LCDC_LCPR_OP_OFF (0x00000000) 1731 1732/* Bit definitions and macros for MCF_LCDC_LCWHBR */ 1733#define MCF_LCDC_LCWHBR_BD(x) (((x)&0x000000FF)<<0) 1734#define MCF_LCDC_LCWHBR_CH(x) (((x)&0x0000001F)<<16) 1735#define MCF_LCDC_LCWHBR_CW(x) (((x)&0x0000001F)<<24) 1736#define MCF_LCDC_LCWHBR_BK_EN (0x80000000) 1737#define MCF_LCDC_LCWHBR_BK_EN_ON (0x80000000) 1738#define MCF_LCDC_LCWHBR_BK_EN_OFF (0x00000000) 1739 1740/* Bit definitions and macros for MCF_LCDC_LCCMR */ 1741#define MCF_LCDC_LCCMR_CUR_COL_B(x) (((x)&0x0000003F)<<0) 1742#define MCF_LCDC_LCCMR_CUR_COL_G(x) (((x)&0x0000003F)<<6) 1743#define MCF_LCDC_LCCMR_CUR_COL_R(x) (((x)&0x0000003F)<<12) 1744 1745/* Bit definitions and macros for MCF_LCDC_LPCR */ 1746#define MCF_LCDC_LPCR_PCD(x) (((x)&0x0000003F)<<0) 1747#define MCF_LCDC_LPCR_SHARP (0x00000040) 1748#define MCF_LCDC_LPCR_SCLKSEL (0x00000080) 1749#define MCF_LCDC_LPCR_ACD(x) (((x)&0x0000007F)<<8) 1750#define MCF_LCDC_LPCR_ACDSEL (0x00008000) 1751#define MCF_LCDC_LPCR_REV_VS (0x00010000) 1752#define MCF_LCDC_LPCR_SWAP_SEL (0x00020000) 1753#define MCF_LCDC_LPCR_ENDSEL (0x00040000) 1754#define MCF_LCDC_LPCR_SCLKIDLE (0x00080000) 1755#define MCF_LCDC_LPCR_OEPOL (0x00100000) 1756#define MCF_LCDC_LPCR_CLKPOL (0x00200000) 1757#define MCF_LCDC_LPCR_LPPOL (0x00400000) 1758#define MCF_LCDC_LPCR_FLM (0x00800000) 1759#define MCF_LCDC_LPCR_PIXPOL (0x01000000) 1760#define MCF_LCDC_LPCR_BPIX(x) (((x)&0x00000007)<<25) 1761#define MCF_LCDC_LPCR_PBSIZ(x) (((x)&0x00000003)<<28) 1762#define MCF_LCDC_LPCR_COLOR (0x40000000) 1763#define MCF_LCDC_LPCR_TFT (0x80000000) 1764#define MCF_LCDC_LPCR_MODE_MONOCGROME (0x00000000) 1765#define MCF_LCDC_LPCR_MODE_CSTN (0x40000000) 1766#define MCF_LCDC_LPCR_MODE_TFT (0xC0000000) 1767#define MCF_LCDC_LPCR_PBSIZ_1 (0x00000000) 1768#define MCF_LCDC_LPCR_PBSIZ_2 (0x10000000) 1769#define MCF_LCDC_LPCR_PBSIZ_4 (0x20000000) 1770#define MCF_LCDC_LPCR_PBSIZ_8 (0x30000000) 1771#define MCF_LCDC_LPCR_BPIX_1bpp (0x00000000) 1772#define MCF_LCDC_LPCR_BPIX_2bpp (0x02000000) 1773#define MCF_LCDC_LPCR_BPIX_4bpp (0x04000000) 1774#define MCF_LCDC_LPCR_BPIX_8bpp (0x06000000) 1775#define MCF_LCDC_LPCR_BPIX_12bpp (0x08000000) 1776#define MCF_LCDC_LPCR_BPIX_16bpp (0x0A000000) 1777#define MCF_LCDC_LPCR_BPIX_18bpp (0x0C000000) 1778 1779#define MCF_LCDC_LPCR_PANEL_TYPE(x) (((x)&0x00000003)<<30) 1780 1781/* Bit definitions and macros for MCF_LCDC_LHCR */ 1782#define MCF_LCDC_LHCR_H_WAIT_2(x) (((x)&0x000000FF)<<0) 1783#define MCF_LCDC_LHCR_H_WAIT_1(x) (((x)&0x000000FF)<<8) 1784#define MCF_LCDC_LHCR_H_WIDTH(x) (((x)&0x0000003F)<<26) 1785 1786/* Bit definitions and macros for MCF_LCDC_LVCR */ 1787#define MCF_LCDC_LVCR_V_WAIT_2(x) (((x)&0x000000FF)<<0) 1788#define MCF_LCDC_LVCR_V_WAIT_1(x) (((x)&0x000000FF)<<8) 1789#define MCF_LCDC_LVCR_V_WIDTH(x) (((x)&0x0000003F)<<26) 1790 1791/* Bit definitions and macros for MCF_LCDC_LPOR */ 1792#define MCF_LCDC_LPOR_POS(x) (((x)&0x0000001F)<<0) 1793 1794/* Bit definitions and macros for MCF_LCDC_LPCCR */ 1795#define MCF_LCDC_LPCCR_PW(x) (((x)&0x000000FF)<<0) 1796#define MCF_LCDC_LPCCR_CC_EN (0x00000100) 1797#define MCF_LCDC_LPCCR_SCR(x) (((x)&0x00000003)<<9) 1798#define MCF_LCDC_LPCCR_LDMSK (0x00008000) 1799#define MCF_LCDC_LPCCR_CLS_HI_WIDTH(x) (((x)&0x000001FF)<<16) 1800#define MCF_LCDC_LPCCR_SCR_LINEPULSE (0x00000000) 1801#define MCF_LCDC_LPCCR_SCR_PIXELCLK (0x00002000) 1802#define MCF_LCDC_LPCCR_SCR_LCDCLOCK (0x00004000) 1803 1804/* Bit definitions and macros for MCF_LCDC_LDCR */ 1805#define MCF_LCDC_LDCR_TM(x) (((x)&0x0000001F)<<0) 1806#define MCF_LCDC_LDCR_HM(x) (((x)&0x0000001F)<<16) 1807#define MCF_LCDC_LDCR_BURST (0x80000000) 1808 1809/* Bit definitions and macros for MCF_LCDC_LRMCR */ 1810#define MCF_LCDC_LRMCR_SEL_REF (0x00000001) 1811 1812/* Bit definitions and macros for MCF_LCDC_LICR */ 1813#define MCF_LCDC_LICR_INTCON (0x00000001) 1814#define MCF_LCDC_LICR_INTSYN (0x00000004) 1815#define MCF_LCDC_LICR_GW_INT_CON (0x00000010) 1816 1817/* Bit definitions and macros for MCF_LCDC_LIER */ 1818#define MCF_LCDC_LIER_BOF_EN (0x00000001) 1819#define MCF_LCDC_LIER_EOF_EN (0x00000002) 1820#define MCF_LCDC_LIER_ERR_RES_EN (0x00000004) 1821#define MCF_LCDC_LIER_UDR_ERR_EN (0x00000008) 1822#define MCF_LCDC_LIER_GW_BOF_EN (0x00000010) 1823#define MCF_LCDC_LIER_GW_EOF_EN (0x00000020) 1824#define MCF_LCDC_LIER_GW_ERR_RES_EN (0x00000040) 1825#define MCF_LCDC_LIER_GW_UDR_ERR_EN (0x00000080) 1826 1827/* Bit definitions and macros for MCF_LCDC_LISR */ 1828#define MCF_LCDC_LISR_BOF (0x00000001) 1829#define MCF_LCDC_LISR_EOF (0x00000002) 1830#define MCF_LCDC_LISR_ERR_RES (0x00000004) 1831#define MCF_LCDC_LISR_UDR_ERR (0x00000008) 1832#define MCF_LCDC_LISR_GW_BOF (0x00000010) 1833#define MCF_LCDC_LISR_GW_EOF (0x00000020) 1834#define MCF_LCDC_LISR_GW_ERR_RES (0x00000040) 1835#define MCF_LCDC_LISR_GW_UDR_ERR (0x00000080) 1836 1837/* Bit definitions and macros for MCF_LCDC_LGWSAR */ 1838#define MCF_LCDC_LGWSAR_GWSA(x) (((x)&0x3FFFFFFF)<<2) 1839 1840/* Bit definitions and macros for MCF_LCDC_LGWSR */ 1841#define MCF_LCDC_LGWSR_GWH(x) (((x)&0x000003FF)<<0) 1842#define MCF_LCDC_LGWSR_GWW(x) (((x)&0x0000003F)<<20) 1843 1844/* Bit definitions and macros for MCF_LCDC_LGWVPWR */ 1845#define MCF_LCDC_LGWVPWR_GWVPW(x) (((x)&0x000003FF)<<0) 1846 1847/* Bit definitions and macros for MCF_LCDC_LGWPOR */ 1848#define MCF_LCDC_LGWPOR_GWPO(x) (((x)&0x0000001F)<<0) 1849 1850/* Bit definitions and macros for MCF_LCDC_LGWPR */ 1851#define MCF_LCDC_LGWPR_GWYP(x) (((x)&0x000003FF)<<0) 1852#define MCF_LCDC_LGWPR_GWXP(x) (((x)&0x000003FF)<<16) 1853 1854/* Bit definitions and macros for MCF_LCDC_LGWCR */ 1855#define MCF_LCDC_LGWCR_GWCKB(x) (((x)&0x0000003F)<<0) 1856#define MCF_LCDC_LGWCR_GWCKG(x) (((x)&0x0000003F)<<6) 1857#define MCF_LCDC_LGWCR_GWCKR(x) (((x)&0x0000003F)<<12) 1858#define MCF_LCDC_LGWCR_GW_RVS (0x00200000) 1859#define MCF_LCDC_LGWCR_GWE (0x00400000) 1860#define MCF_LCDC_LGWCR_GWCKE (0x00800000) 1861#define MCF_LCDC_LGWCR_GWAV(x) (((x)&0x000000FF)<<24) 1862 1863/* Bit definitions and macros for MCF_LCDC_LGWDCR */ 1864#define MCF_LCDC_LGWDCR_GWTM(x) (((x)&0x0000001F)<<0) 1865#define MCF_LCDC_LGWDCR_GWHM(x) (((x)&0x0000001F)<<16) 1866#define MCF_LCDC_LGWDCR_GWBT (0x80000000) 1867 1868/* Bit definitions and macros for MCF_LCDC_LSCR */ 1869#define MCF_LCDC_LSCR_PS_RISE_DELAY(x) (((x)&0x0000003F)<<26) 1870#define MCF_LCDC_LSCR_CLS_RISE_DELAY(x) (((x)&0x000000FF)<<16) 1871#define MCF_LCDC_LSCR_REV_TOGGLE_DELAY(x) (((x)&0x0000000F)<<8) 1872#define MCF_LCDC_LSCR_GRAY_2(x) (((x)&0x0000000F)<<4) 1873#define MCF_LCDC_LSCR_GRAY_1(x) (((x)&0x0000000F)<<0) 1874 1875/* Bit definitions and macros for MCF_LCDC_BPLUT_BASE */ 1876#define MCF_LCDC_BPLUT_BASE_BASE(x) (((x)&0xFFFFFFFF)<<0) 1877 1878/* Bit definitions and macros for MCF_LCDC_GWLUT_BASE */ 1879#define MCF_LCDC_GWLUT_BASE_BASE(x) (((x)&0xFFFFFFFF)<<0) 1880 1881/********************************************************************* 1882 * 1883 * Phase Locked Loop (PLL) 1884 * 1885 *********************************************************************/ 1886 1887/* Register read/write macros */ 1888#define MCF_PLL_PODR MCF_REG08(0xFC0C0000) 1889#define MCF_PLL_PLLCR MCF_REG08(0xFC0C0004) 1890#define MCF_PLL_PMDR MCF_REG08(0xFC0C0008) 1891#define MCF_PLL_PFDR MCF_REG08(0xFC0C000C) 1892 1893/* Bit definitions and macros for MCF_PLL_PODR */ 1894#define MCF_PLL_PODR_BUSDIV(x) (((x)&0x0F)<<0) 1895#define MCF_PLL_PODR_CPUDIV(x) (((x)&0x0F)<<4) 1896 1897/* Bit definitions and macros for MCF_PLL_PLLCR */ 1898#define MCF_PLL_PLLCR_DITHDEV(x) (((x)&0x07)<<0) 1899#define MCF_PLL_PLLCR_DITHEN (0x80) 1900 1901/* Bit definitions and macros for MCF_PLL_PMDR */ 1902#define MCF_PLL_PMDR_MODDIV(x) (((x)&0xFF)<<0) 1903 1904/* Bit definitions and macros for MCF_PLL_PFDR */ 1905#define MCF_PLL_PFDR_MFD(x) (((x)&0xFF)<<0) 1906 1907/********************************************************************* 1908 * 1909 * System Control Module Registers (SCM) 1910 * 1911 *********************************************************************/ 1912 1913/* Register read/write macros */ 1914#define MCF_SCM_MPR MCF_REG32(0xFC000000) 1915#define MCF_SCM_PACRA MCF_REG32(0xFC000020) 1916#define MCF_SCM_PACRB MCF_REG32(0xFC000024) 1917#define MCF_SCM_PACRC MCF_REG32(0xFC000028) 1918#define MCF_SCM_PACRD MCF_REG32(0xFC00002C) 1919#define MCF_SCM_PACRE MCF_REG32(0xFC000040) 1920#define MCF_SCM_PACRF MCF_REG32(0xFC000044) 1921 1922#define MCF_SCM_BCR MCF_REG32(0xFC040024) 1923 1924/********************************************************************* 1925 * 1926 * SDRAM Controller (SDRAMC) 1927 * 1928 *********************************************************************/ 1929 1930/* Register read/write macros */ 1931#define MCF_SDRAMC_SDMR MCF_REG32(0xFC0B8000) 1932#define MCF_SDRAMC_SDCR MCF_REG32(0xFC0B8004) 1933#define MCF_SDRAMC_SDCFG1 MCF_REG32(0xFC0B8008) 1934#define MCF_SDRAMC_SDCFG2 MCF_REG32(0xFC0B800C) 1935#define MCF_SDRAMC_LIMP_FIX MCF_REG32(0xFC0B8080) 1936#define MCF_SDRAMC_SDDS MCF_REG32(0xFC0B8100) 1937#define MCF_SDRAMC_SDCS0 MCF_REG32(0xFC0B8110) 1938#define MCF_SDRAMC_SDCS1 MCF_REG32(0xFC0B8114) 1939#define MCF_SDRAMC_SDCS2 MCF_REG32(0xFC0B8118) 1940#define MCF_SDRAMC_SDCS3 MCF_REG32(0xFC0B811C) 1941#define MCF_SDRAMC_SDCS(x) MCF_REG32(0xFC0B8110+((x)*0x004)) 1942 1943/* Bit definitions and macros for MCF_SDRAMC_SDMR */ 1944#define MCF_SDRAMC_SDMR_CMD (0x00010000) 1945#define MCF_SDRAMC_SDMR_AD(x) (((x)&0x00000FFF)<<18) 1946#define MCF_SDRAMC_SDMR_BNKAD(x) (((x)&0x00000003)<<30) 1947#define MCF_SDRAMC_SDMR_BNKAD_LMR (0x00000000) 1948#define MCF_SDRAMC_SDMR_BNKAD_LEMR (0x40000000) 1949 1950/* Bit definitions and macros for MCF_SDRAMC_SDCR */ 1951#define MCF_SDRAMC_SDCR_IPALL (0x00000002) 1952#define MCF_SDRAMC_SDCR_IREF (0x00000004) 1953#define MCF_SDRAMC_SDCR_DQS_OE(x) (((x)&0x0000000F)<<8) 1954#define MCF_SDRAMC_SDCR_PS(x) (((x)&0x00000003)<<12) 1955#define MCF_SDRAMC_SDCR_RCNT(x) (((x)&0x0000003F)<<16) 1956#define MCF_SDRAMC_SDCR_OE_RULE (0x00400000) 1957#define MCF_SDRAMC_SDCR_MUX(x) (((x)&0x00000003)<<24) 1958#define MCF_SDRAMC_SDCR_REF (0x10000000) 1959#define MCF_SDRAMC_SDCR_DDR (0x20000000) 1960#define MCF_SDRAMC_SDCR_CKE (0x40000000) 1961#define MCF_SDRAMC_SDCR_MODE_EN (0x80000000) 1962#define MCF_SDRAMC_SDCR_PS_16 (0x00002000) 1963#define MCF_SDRAMC_SDCR_PS_32 (0x00000000) 1964 1965/* Bit definitions and macros for MCF_SDRAMC_SDCFG1 */ 1966#define MCF_SDRAMC_SDCFG1_WTLAT(x) (((x)&0x00000007)<<4) 1967#define MCF_SDRAMC_SDCFG1_REF2ACT(x) (((x)&0x0000000F)<<8) 1968#define MCF_SDRAMC_SDCFG1_PRE2ACT(x) (((x)&0x00000007)<<12) 1969#define MCF_SDRAMC_SDCFG1_ACT2RW(x) (((x)&0x00000007)<<16) 1970#define MCF_SDRAMC_SDCFG1_RDLAT(x) (((x)&0x0000000F)<<20) 1971#define MCF_SDRAMC_SDCFG1_SWT2RD(x) (((x)&0x00000007)<<24) 1972#define MCF_SDRAMC_SDCFG1_SRD2RW(x) (((x)&0x0000000F)<<28) 1973 1974/* Bit definitions and macros for MCF_SDRAMC_SDCFG2 */ 1975#define MCF_SDRAMC_SDCFG2_BL(x) (((x)&0x0000000F)<<16) 1976#define MCF_SDRAMC_SDCFG2_BRD2WT(x) (((x)&0x0000000F)<<20) 1977#define MCF_SDRAMC_SDCFG2_BWT2RW(x) (((x)&0x0000000F)<<24) 1978#define MCF_SDRAMC_SDCFG2_BRD2PRE(x) (((x)&0x0000000F)<<28) 1979 1980#define MCF_SDRAMC_REFRESH (0x40000000) 1981 1982/* Bit definitions and macros for MCF_SDRAMC_SDDS */ 1983#define MCF_SDRAMC_SDDS_SB_D(x) (((x)&0x00000003)<<0) 1984#define MCF_SDRAMC_SDDS_SB_S(x) (((x)&0x00000003)<<2) 1985#define MCF_SDRAMC_SDDS_SB_A(x) (((x)&0x00000003)<<4) 1986#define MCF_SDRAMC_SDDS_SB_C(x) (((x)&0x00000003)<<6) 1987#define MCF_SDRAMC_SDDS_SB_E(x) (((x)&0x00000003)<<8) 1988 1989/* Bit definitions and macros for MCF_SDRAMC_SDCS */ 1990#define MCF_SDRAMC_SDCS_CSSZ(x) (((x)&0x0000001F)<<0) 1991#define MCF_SDRAMC_SDCS_BASE(x) (((x)&0x00000FFF)<<20) 1992#define MCF_SDRAMC_SDCS_BA(x) ((x)&0xFFF00000) 1993#define MCF_SDRAMC_SDCS_CSSZ_DIABLE (0x00000000) 1994#define MCF_SDRAMC_SDCS_CSSZ_1MBYTE (0x00000013) 1995#define MCF_SDRAMC_SDCS_CSSZ_2MBYTE (0x00000014) 1996#define MCF_SDRAMC_SDCS_CSSZ_4MBYTE (0x00000015) 1997#define MCF_SDRAMC_SDCS_CSSZ_8MBYTE (0x00000016) 1998#define MCF_SDRAMC_SDCS_CSSZ_16MBYTE (0x00000017) 1999#define MCF_SDRAMC_SDCS_CSSZ_32MBYTE (0x00000018) 2000#define MCF_SDRAMC_SDCS_CSSZ_64MBYTE (0x00000019) 2001#define MCF_SDRAMC_SDCS_CSSZ_128MBYTE (0x0000001A) 2002#define MCF_SDRAMC_SDCS_CSSZ_256MBYTE (0x0000001B) 2003#define MCF_SDRAMC_SDCS_CSSZ_512MBYTE (0x0000001C) 2004#define MCF_SDRAMC_SDCS_CSSZ_1GBYTE (0x0000001D) 2005#define MCF_SDRAMC_SDCS_CSSZ_2GBYTE (0x0000001E) 2006#define MCF_SDRAMC_SDCS_CSSZ_4GBYTE (0x0000001F) 2007 2008/********************************************************************* 2009 * 2010 * FlexCAN module registers 2011 * 2012 *********************************************************************/ 2013#define MCF_FLEXCAN_BASEADDR(x) (0xFC020000+(x)*0x0800) 2014#define MCF_FLEXCAN_CANMCR(x) MCF_REG32(0xFC020000+(x)*0x0800+0x00) 2015#define MCF_FLEXCAN_CANCTRL(x) MCF_REG32(0xFC020000+(x)*0x0800+0x04) 2016#define MCF_FLEXCAN_TIMER(x) MCF_REG32(0xFC020000+(x)*0x0800+0x08) 2017#define MCF_FLEXCAN_RXGMASK(x) MCF_REG32(0xFC020000+(x)*0x0800+0x10) 2018#define MCF_FLEXCAN_RX14MASK(x) MCF_REG32(0xFC020000+(x)*0x0800+0x14) 2019#define MCF_FLEXCAN_RX15MASK(x) MCF_REG32(0xFC020000+(x)*0x0800+0x18) 2020#define MCF_FLEXCAN_ERRCNT(x) MCF_REG32(0xFC020000+(x)*0x0800+0x1C) 2021#define MCF_FLEXCAN_ERRSTAT(x) MCF_REG32(0xFC020000+(x)*0x0800+0x20) 2022#define MCF_FLEXCAN_IMASK(x) MCF_REG32(0xFC020000+(x)*0x0800+0x28) 2023#define MCF_FLEXCAN_IFLAG(x) MCF_REG32(0xFC020000+(x)*0x0800+0x30) 2024 2025#define MCF_FLEXCAN_MB_CNT(x,y) MCF_REG32(0xFC020080+(x)*0x0800+(y)*0x10+0x0) 2026#define MCF_FLEXCAN_MB_ID(x,y) MCF_REG32(0xFC020080+(x)*0x0800+(y)*0x10+0x4) 2027#define MCF_FLEXCAN_MB_DB(x,y,z) MCF_REG08(0xFC020080+(x)*0x0800+(y)*0x10+0x8+(z)*0x1) 2028 2029/* 2030 * FlexCAN Module Configuration Register 2031 */ 2032#define CANMCR_MDIS (0x80000000) 2033#define CANMCR_FRZ (0x40000000) 2034#define CANMCR_HALT (0x10000000) 2035#define CANMCR_SOFTRST (0x02000000) 2036#define CANMCR_FRZACK (0x01000000) 2037#define CANMCR_SUPV (0x00800000) 2038#define CANMCR_MAXMB(x) ((x)&0x0F) 2039 2040/* 2041 * FlexCAN Control Register 2042 */ 2043#define CANCTRL_PRESDIV(x) (((x)&0xFF)<<24) 2044#define CANCTRL_RJW(x) (((x)&0x03)<<22) 2045#define CANCTRL_PSEG1(x) (((x)&0x07)<<19) 2046#define CANCTRL_PSEG2(x) (((x)&0x07)<<16) 2047#define CANCTRL_BOFFMSK (0x00008000) 2048#define CANCTRL_ERRMSK (0x00004000) 2049#define CANCTRL_CLKSRC (0x00002000) 2050#define CANCTRL_LPB (0x00001000) 2051#define CANCTRL_SAMP (0x00000080) 2052#define CANCTRL_BOFFREC (0x00000040) 2053#define CANCTRL_TSYNC (0x00000020) 2054#define CANCTRL_LBUF (0x00000010) 2055#define CANCTRL_LOM (0x00000008) 2056#define CANCTRL_PROPSEG(x) ((x)&0x07) 2057 2058/* 2059 * FlexCAN Error Counter Register 2060 */ 2061#define ERRCNT_RXECTR(x) (((x)&0xFF)<<8) 2062#define ERRCNT_TXECTR(x) ((x)&0xFF) 2063 2064/* 2065 * FlexCAN Error and Status Register 2066 */ 2067#define ERRSTAT_BITERR(x) (((x)&0x03)<<14) 2068#define ERRSTAT_ACKERR (0x00002000) 2069#define ERRSTAT_CRCERR (0x00001000) 2070#define ERRSTAT_FRMERR (0x00000800) 2071#define ERRSTAT_STFERR (0x00000400) 2072#define ERRSTAT_TXWRN (0x00000200) 2073#define ERRSTAT_RXWRN (0x00000100) 2074#define ERRSTAT_IDLE (0x00000080) 2075#define ERRSTAT_TXRX (0x00000040) 2076#define ERRSTAT_FLTCONF(x) (((x)&0x03)<<4) 2077#define ERRSTAT_BOFFINT (0x00000004) 2078#define ERRSTAT_ERRINT (0x00000002) 2079 2080/* 2081 * Interrupt Mask Register 2082 */ 2083#define IMASK_BUF15M (0x8000) 2084#define IMASK_BUF14M (0x4000) 2085#define IMASK_BUF13M (0x2000) 2086#define IMASK_BUF12M (0x1000) 2087#define IMASK_BUF11M (0x0800) 2088#define IMASK_BUF10M (0x0400) 2089#define IMASK_BUF9M (0x0200) 2090#define IMASK_BUF8M (0x0100) 2091#define IMASK_BUF7M (0x0080) 2092#define IMASK_BUF6M (0x0040) 2093#define IMASK_BUF5M (0x0020) 2094#define IMASK_BUF4M (0x0010) 2095#define IMASK_BUF3M (0x0008) 2096#define IMASK_BUF2M (0x0004) 2097#define IMASK_BUF1M (0x0002) 2098#define IMASK_BUF0M (0x0001) 2099#define IMASK_BUFnM(x) (0x1<<(x)) 2100#define IMASK_BUFF_ENABLE_ALL (0x1111) 2101#define IMASK_BUFF_DISABLE_ALL (0x0000) 2102 2103/* 2104 * Interrupt Flag Register 2105 */ 2106#define IFLAG_BUF15M (0x8000) 2107#define IFLAG_BUF14M (0x4000) 2108#define IFLAG_BUF13M (0x2000) 2109#define IFLAG_BUF12M (0x1000) 2110#define IFLAG_BUF11M (0x0800) 2111#define IFLAG_BUF10M (0x0400) 2112#define IFLAG_BUF9M (0x0200) 2113#define IFLAG_BUF8M (0x0100) 2114#define IFLAG_BUF7M (0x0080) 2115#define IFLAG_BUF6M (0x0040) 2116#define IFLAG_BUF5M (0x0020) 2117#define IFLAG_BUF4M (0x0010) 2118#define IFLAG_BUF3M (0x0008) 2119#define IFLAG_BUF2M (0x0004) 2120#define IFLAG_BUF1M (0x0002) 2121#define IFLAG_BUF0M (0x0001) 2122#define IFLAG_BUFF_SET_ALL (0xFFFF) 2123#define IFLAG_BUFF_CLEAR_ALL (0x0000) 2124#define IFLAG_BUFnM(x) (0x1<<(x)) 2125 2126/* 2127 * Message Buffers 2128 */ 2129#define MB_CNT_CODE(x) (((x)&0x0F)<<24) 2130#define MB_CNT_SRR (0x00400000) 2131#define MB_CNT_IDE (0x00200000) 2132#define MB_CNT_RTR (0x00100000) 2133#define MB_CNT_LENGTH(x) (((x)&0x0F)<<16) 2134#define MB_CNT_TIMESTAMP(x) ((x)&0xFFFF) 2135#define MB_ID_STD(x) (((x)&0x07FF)<<18) 2136#define MB_ID_EXT(x) ((x)&0x3FFFF) 2137 2138/********************************************************************* 2139 * 2140 * Edge Port Module (EPORT) 2141 * 2142 *********************************************************************/ 2143 2144/* Register read/write macros */ 2145#define MCFEPORT_EPPAR (0xFC094000) 2146#define MCFEPORT_EPDDR (0xFC094002) 2147#define MCFEPORT_EPIER (0xFC094003) 2148#define MCFEPORT_EPDR (0xFC094004) 2149#define MCFEPORT_EPPDR (0xFC094005) 2150#define MCFEPORT_EPFR (0xFC094006) 2151 2152/* Bit definitions and macros for MCF_EPORT_EPPAR */ 2153#define MCF_EPORT_EPPAR_EPPA1(x) (((x)&0x0003)<<2) 2154#define MCF_EPORT_EPPAR_EPPA2(x) (((x)&0x0003)<<4) 2155#define MCF_EPORT_EPPAR_EPPA3(x) (((x)&0x0003)<<6) 2156#define MCF_EPORT_EPPAR_EPPA4(x) (((x)&0x0003)<<8) 2157#define MCF_EPORT_EPPAR_EPPA5(x) (((x)&0x0003)<<10) 2158#define MCF_EPORT_EPPAR_EPPA6(x) (((x)&0x0003)<<12) 2159#define MCF_EPORT_EPPAR_EPPA7(x) (((x)&0x0003)<<14) 2160#define MCF_EPORT_EPPAR_LEVEL (0) 2161#define MCF_EPORT_EPPAR_RISING (1) 2162#define MCF_EPORT_EPPAR_FALLING (2) 2163#define MCF_EPORT_EPPAR_BOTH (3) 2164#define MCF_EPORT_EPPAR_EPPA7_LEVEL (0x0000) 2165#define MCF_EPORT_EPPAR_EPPA7_RISING (0x4000) 2166#define MCF_EPORT_EPPAR_EPPA7_FALLING (0x8000) 2167#define MCF_EPORT_EPPAR_EPPA7_BOTH (0xC000) 2168#define MCF_EPORT_EPPAR_EPPA6_LEVEL (0x0000) 2169#define MCF_EPORT_EPPAR_EPPA6_RISING (0x1000) 2170#define MCF_EPORT_EPPAR_EPPA6_FALLING (0x2000) 2171#define MCF_EPORT_EPPAR_EPPA6_BOTH (0x3000) 2172#define MCF_EPORT_EPPAR_EPPA5_LEVEL (0x0000) 2173#define MCF_EPORT_EPPAR_EPPA5_RISING (0x0400) 2174#define MCF_EPORT_EPPAR_EPPA5_FALLING (0x0800) 2175#define MCF_EPORT_EPPAR_EPPA5_BOTH (0x0C00) 2176#define MCF_EPORT_EPPAR_EPPA4_LEVEL (0x0000) 2177#define MCF_EPORT_EPPAR_EPPA4_RISING (0x0100) 2178#define MCF_EPORT_EPPAR_EPPA4_FALLING (0x0200) 2179#define MCF_EPORT_EPPAR_EPPA4_BOTH (0x0300) 2180#define MCF_EPORT_EPPAR_EPPA3_LEVEL (0x0000) 2181#define MCF_EPORT_EPPAR_EPPA3_RISING (0x0040) 2182#define MCF_EPORT_EPPAR_EPPA3_FALLING (0x0080) 2183#define MCF_EPORT_EPPAR_EPPA3_BOTH (0x00C0) 2184#define MCF_EPORT_EPPAR_EPPA2_LEVEL (0x0000) 2185#define MCF_EPORT_EPPAR_EPPA2_RISING (0x0010) 2186#define MCF_EPORT_EPPAR_EPPA2_FALLING (0x0020) 2187#define MCF_EPORT_EPPAR_EPPA2_BOTH (0x0030) 2188#define MCF_EPORT_EPPAR_EPPA1_LEVEL (0x0000) 2189#define MCF_EPORT_EPPAR_EPPA1_RISING (0x0004) 2190#define MCF_EPORT_EPPAR_EPPA1_FALLING (0x0008) 2191#define MCF_EPORT_EPPAR_EPPA1_BOTH (0x000C) 2192 2193/* Bit definitions and macros for MCF_EPORT_EPDDR */ 2194#define MCF_EPORT_EPDDR_EPDD1 (0x02) 2195#define MCF_EPORT_EPDDR_EPDD2 (0x04) 2196#define MCF_EPORT_EPDDR_EPDD3 (0x08) 2197#define MCF_EPORT_EPDDR_EPDD4 (0x10) 2198#define MCF_EPORT_EPDDR_EPDD5 (0x20) 2199#define MCF_EPORT_EPDDR_EPDD6 (0x40) 2200#define MCF_EPORT_EPDDR_EPDD7 (0x80) 2201 2202/* Bit definitions and macros for MCF_EPORT_EPIER */ 2203#define MCF_EPORT_EPIER_EPIE1 (0x02) 2204#define MCF_EPORT_EPIER_EPIE2 (0x04) 2205#define MCF_EPORT_EPIER_EPIE3 (0x08) 2206#define MCF_EPORT_EPIER_EPIE4 (0x10) 2207#define MCF_EPORT_EPIER_EPIE5 (0x20) 2208#define MCF_EPORT_EPIER_EPIE6 (0x40) 2209#define MCF_EPORT_EPIER_EPIE7 (0x80) 2210 2211/* Bit definitions and macros for MCF_EPORT_EPDR */ 2212#define MCF_EPORT_EPDR_EPD1 (0x02) 2213#define MCF_EPORT_EPDR_EPD2 (0x04) 2214#define MCF_EPORT_EPDR_EPD3 (0x08) 2215#define MCF_EPORT_EPDR_EPD4 (0x10) 2216#define MCF_EPORT_EPDR_EPD5 (0x20) 2217#define MCF_EPORT_EPDR_EPD6 (0x40) 2218#define MCF_EPORT_EPDR_EPD7 (0x80) 2219 2220/* Bit definitions and macros for MCF_EPORT_EPPDR */ 2221#define MCF_EPORT_EPPDR_EPPD1 (0x02) 2222#define MCF_EPORT_EPPDR_EPPD2 (0x04) 2223#define MCF_EPORT_EPPDR_EPPD3 (0x08) 2224#define MCF_EPORT_EPPDR_EPPD4 (0x10) 2225#define MCF_EPORT_EPPDR_EPPD5 (0x20) 2226#define MCF_EPORT_EPPDR_EPPD6 (0x40) 2227#define MCF_EPORT_EPPDR_EPPD7 (0x80) 2228 2229/* Bit definitions and macros for MCF_EPORT_EPFR */ 2230#define MCF_EPORT_EPFR_EPF1 (0x02) 2231#define MCF_EPORT_EPFR_EPF2 (0x04) 2232#define MCF_EPORT_EPFR_EPF3 (0x08) 2233#define MCF_EPORT_EPFR_EPF4 (0x10) 2234#define MCF_EPORT_EPFR_EPF5 (0x20) 2235#define MCF_EPORT_EPFR_EPF6 (0x40) 2236#define MCF_EPORT_EPFR_EPF7 (0x80) 2237 2238/********************************************************************/ 2239#endif /* m532xsim_h */ 2240