1#ifndef __iop_sw_cfg_defs_h 2#define __iop_sw_cfg_defs_h 3 4/* 5 * This file is autogenerated from 6 * file: iop_sw_cfg.r 7 * 8 * by ../../../tools/rdesc/bin/rdes2c -outfile iop_sw_cfg_defs.h iop_sw_cfg.r 9 * Any changes here will be lost. 10 * 11 * -*- buffer-read-only: t -*- 12 */ 13/* Main access macros */ 14#ifndef REG_RD 15#define REG_RD( scope, inst, reg ) \ 16 REG_READ( reg_##scope##_##reg, \ 17 (inst) + REG_RD_ADDR_##scope##_##reg ) 18#endif 19 20#ifndef REG_WR 21#define REG_WR( scope, inst, reg, val ) \ 22 REG_WRITE( reg_##scope##_##reg, \ 23 (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) 24#endif 25 26#ifndef REG_RD_VECT 27#define REG_RD_VECT( scope, inst, reg, index ) \ 28 REG_READ( reg_##scope##_##reg, \ 29 (inst) + REG_RD_ADDR_##scope##_##reg + \ 30 (index) * STRIDE_##scope##_##reg ) 31#endif 32 33#ifndef REG_WR_VECT 34#define REG_WR_VECT( scope, inst, reg, index, val ) \ 35 REG_WRITE( reg_##scope##_##reg, \ 36 (inst) + REG_WR_ADDR_##scope##_##reg + \ 37 (index) * STRIDE_##scope##_##reg, (val) ) 38#endif 39 40#ifndef REG_RD_INT 41#define REG_RD_INT( scope, inst, reg ) \ 42 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) 43#endif 44 45#ifndef REG_WR_INT 46#define REG_WR_INT( scope, inst, reg, val ) \ 47 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) 48#endif 49 50#ifndef REG_RD_INT_VECT 51#define REG_RD_INT_VECT( scope, inst, reg, index ) \ 52 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ 53 (index) * STRIDE_##scope##_##reg ) 54#endif 55 56#ifndef REG_WR_INT_VECT 57#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ 58 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ 59 (index) * STRIDE_##scope##_##reg, (val) ) 60#endif 61 62#ifndef REG_TYPE_CONV 63#define REG_TYPE_CONV( type, orgtype, val ) \ 64 ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) 65#endif 66 67#ifndef reg_page_size 68#define reg_page_size 8192 69#endif 70 71#ifndef REG_ADDR 72#define REG_ADDR( scope, inst, reg ) \ 73 ( (inst) + REG_RD_ADDR_##scope##_##reg ) 74#endif 75 76#ifndef REG_ADDR_VECT 77#define REG_ADDR_VECT( scope, inst, reg, index ) \ 78 ( (inst) + REG_RD_ADDR_##scope##_##reg + \ 79 (index) * STRIDE_##scope##_##reg ) 80#endif 81 82/* C-code for register scope iop_sw_cfg */ 83 84/* Register rw_crc_par_owner, scope iop_sw_cfg, type rw */ 85typedef struct { 86 unsigned int cfg : 2; 87 unsigned int dummy1 : 30; 88} reg_iop_sw_cfg_rw_crc_par_owner; 89#define REG_RD_ADDR_iop_sw_cfg_rw_crc_par_owner 0 90#define REG_WR_ADDR_iop_sw_cfg_rw_crc_par_owner 0 91 92/* Register rw_dmc_in_owner, scope iop_sw_cfg, type rw */ 93typedef struct { 94 unsigned int cfg : 2; 95 unsigned int dummy1 : 30; 96} reg_iop_sw_cfg_rw_dmc_in_owner; 97#define REG_RD_ADDR_iop_sw_cfg_rw_dmc_in_owner 4 98#define REG_WR_ADDR_iop_sw_cfg_rw_dmc_in_owner 4 99 100/* Register rw_dmc_out_owner, scope iop_sw_cfg, type rw */ 101typedef struct { 102 unsigned int cfg : 2; 103 unsigned int dummy1 : 30; 104} reg_iop_sw_cfg_rw_dmc_out_owner; 105#define REG_RD_ADDR_iop_sw_cfg_rw_dmc_out_owner 8 106#define REG_WR_ADDR_iop_sw_cfg_rw_dmc_out_owner 8 107 108/* Register rw_fifo_in_owner, scope iop_sw_cfg, type rw */ 109typedef struct { 110 unsigned int cfg : 2; 111 unsigned int dummy1 : 30; 112} reg_iop_sw_cfg_rw_fifo_in_owner; 113#define REG_RD_ADDR_iop_sw_cfg_rw_fifo_in_owner 12 114#define REG_WR_ADDR_iop_sw_cfg_rw_fifo_in_owner 12 115 116/* Register rw_fifo_in_extra_owner, scope iop_sw_cfg, type rw */ 117typedef struct { 118 unsigned int cfg : 2; 119 unsigned int dummy1 : 30; 120} reg_iop_sw_cfg_rw_fifo_in_extra_owner; 121#define REG_RD_ADDR_iop_sw_cfg_rw_fifo_in_extra_owner 16 122#define REG_WR_ADDR_iop_sw_cfg_rw_fifo_in_extra_owner 16 123 124/* Register rw_fifo_out_owner, scope iop_sw_cfg, type rw */ 125typedef struct { 126 unsigned int cfg : 2; 127 unsigned int dummy1 : 30; 128} reg_iop_sw_cfg_rw_fifo_out_owner; 129#define REG_RD_ADDR_iop_sw_cfg_rw_fifo_out_owner 20 130#define REG_WR_ADDR_iop_sw_cfg_rw_fifo_out_owner 20 131 132/* Register rw_fifo_out_extra_owner, scope iop_sw_cfg, type rw */ 133typedef struct { 134 unsigned int cfg : 2; 135 unsigned int dummy1 : 30; 136} reg_iop_sw_cfg_rw_fifo_out_extra_owner; 137#define REG_RD_ADDR_iop_sw_cfg_rw_fifo_out_extra_owner 24 138#define REG_WR_ADDR_iop_sw_cfg_rw_fifo_out_extra_owner 24 139 140/* Register rw_sap_in_owner, scope iop_sw_cfg, type rw */ 141typedef struct { 142 unsigned int cfg : 2; 143 unsigned int dummy1 : 30; 144} reg_iop_sw_cfg_rw_sap_in_owner; 145#define REG_RD_ADDR_iop_sw_cfg_rw_sap_in_owner 28 146#define REG_WR_ADDR_iop_sw_cfg_rw_sap_in_owner 28 147 148/* Register rw_sap_out_owner, scope iop_sw_cfg, type rw */ 149typedef struct { 150 unsigned int cfg : 2; 151 unsigned int dummy1 : 30; 152} reg_iop_sw_cfg_rw_sap_out_owner; 153#define REG_RD_ADDR_iop_sw_cfg_rw_sap_out_owner 32 154#define REG_WR_ADDR_iop_sw_cfg_rw_sap_out_owner 32 155 156/* Register rw_scrc_in_owner, scope iop_sw_cfg, type rw */ 157typedef struct { 158 unsigned int cfg : 2; 159 unsigned int dummy1 : 30; 160} reg_iop_sw_cfg_rw_scrc_in_owner; 161#define REG_RD_ADDR_iop_sw_cfg_rw_scrc_in_owner 36 162#define REG_WR_ADDR_iop_sw_cfg_rw_scrc_in_owner 36 163 164/* Register rw_scrc_out_owner, scope iop_sw_cfg, type rw */ 165typedef struct { 166 unsigned int cfg : 2; 167 unsigned int dummy1 : 30; 168} reg_iop_sw_cfg_rw_scrc_out_owner; 169#define REG_RD_ADDR_iop_sw_cfg_rw_scrc_out_owner 40 170#define REG_WR_ADDR_iop_sw_cfg_rw_scrc_out_owner 40 171 172/* Register rw_spu_owner, scope iop_sw_cfg, type rw */ 173typedef struct { 174 unsigned int cfg : 1; 175 unsigned int dummy1 : 31; 176} reg_iop_sw_cfg_rw_spu_owner; 177#define REG_RD_ADDR_iop_sw_cfg_rw_spu_owner 44 178#define REG_WR_ADDR_iop_sw_cfg_rw_spu_owner 44 179 180/* Register rw_timer_grp0_owner, scope iop_sw_cfg, type rw */ 181typedef struct { 182 unsigned int cfg : 2; 183 unsigned int dummy1 : 30; 184} reg_iop_sw_cfg_rw_timer_grp0_owner; 185#define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp0_owner 48 186#define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp0_owner 48 187 188/* Register rw_timer_grp1_owner, scope iop_sw_cfg, type rw */ 189typedef struct { 190 unsigned int cfg : 2; 191 unsigned int dummy1 : 30; 192} reg_iop_sw_cfg_rw_timer_grp1_owner; 193#define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp1_owner 52 194#define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp1_owner 52 195 196/* Register rw_trigger_grp0_owner, scope iop_sw_cfg, type rw */ 197typedef struct { 198 unsigned int cfg : 2; 199 unsigned int dummy1 : 30; 200} reg_iop_sw_cfg_rw_trigger_grp0_owner; 201#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp0_owner 56 202#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp0_owner 56 203 204/* Register rw_trigger_grp1_owner, scope iop_sw_cfg, type rw */ 205typedef struct { 206 unsigned int cfg : 2; 207 unsigned int dummy1 : 30; 208} reg_iop_sw_cfg_rw_trigger_grp1_owner; 209#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp1_owner 60 210#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp1_owner 60 211 212/* Register rw_trigger_grp2_owner, scope iop_sw_cfg, type rw */ 213typedef struct { 214 unsigned int cfg : 2; 215 unsigned int dummy1 : 30; 216} reg_iop_sw_cfg_rw_trigger_grp2_owner; 217#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp2_owner 64 218#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp2_owner 64 219 220/* Register rw_trigger_grp3_owner, scope iop_sw_cfg, type rw */ 221typedef struct { 222 unsigned int cfg : 2; 223 unsigned int dummy1 : 30; 224} reg_iop_sw_cfg_rw_trigger_grp3_owner; 225#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp3_owner 68 226#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp3_owner 68 227 228/* Register rw_trigger_grp4_owner, scope iop_sw_cfg, type rw */ 229typedef struct { 230 unsigned int cfg : 2; 231 unsigned int dummy1 : 30; 232} reg_iop_sw_cfg_rw_trigger_grp4_owner; 233#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp4_owner 72 234#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp4_owner 72 235 236/* Register rw_trigger_grp5_owner, scope iop_sw_cfg, type rw */ 237typedef struct { 238 unsigned int cfg : 2; 239 unsigned int dummy1 : 30; 240} reg_iop_sw_cfg_rw_trigger_grp5_owner; 241#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp5_owner 76 242#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp5_owner 76 243 244/* Register rw_trigger_grp6_owner, scope iop_sw_cfg, type rw */ 245typedef struct { 246 unsigned int cfg : 2; 247 unsigned int dummy1 : 30; 248} reg_iop_sw_cfg_rw_trigger_grp6_owner; 249#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp6_owner 80 250#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp6_owner 80 251 252/* Register rw_trigger_grp7_owner, scope iop_sw_cfg, type rw */ 253typedef struct { 254 unsigned int cfg : 2; 255 unsigned int dummy1 : 30; 256} reg_iop_sw_cfg_rw_trigger_grp7_owner; 257#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp7_owner 84 258#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp7_owner 84 259 260/* Register rw_bus_mask, scope iop_sw_cfg, type rw */ 261typedef struct { 262 unsigned int byte0 : 8; 263 unsigned int byte1 : 8; 264 unsigned int byte2 : 8; 265 unsigned int byte3 : 8; 266} reg_iop_sw_cfg_rw_bus_mask; 267#define REG_RD_ADDR_iop_sw_cfg_rw_bus_mask 88 268#define REG_WR_ADDR_iop_sw_cfg_rw_bus_mask 88 269 270/* Register rw_bus_oe_mask, scope iop_sw_cfg, type rw */ 271typedef struct { 272 unsigned int byte0 : 1; 273 unsigned int byte1 : 1; 274 unsigned int byte2 : 1; 275 unsigned int byte3 : 1; 276 unsigned int dummy1 : 28; 277} reg_iop_sw_cfg_rw_bus_oe_mask; 278#define REG_RD_ADDR_iop_sw_cfg_rw_bus_oe_mask 92 279#define REG_WR_ADDR_iop_sw_cfg_rw_bus_oe_mask 92 280 281/* Register rw_gio_mask, scope iop_sw_cfg, type rw */ 282typedef struct { 283 unsigned int val : 32; 284} reg_iop_sw_cfg_rw_gio_mask; 285#define REG_RD_ADDR_iop_sw_cfg_rw_gio_mask 96 286#define REG_WR_ADDR_iop_sw_cfg_rw_gio_mask 96 287 288/* Register rw_gio_oe_mask, scope iop_sw_cfg, type rw */ 289typedef struct { 290 unsigned int val : 32; 291} reg_iop_sw_cfg_rw_gio_oe_mask; 292#define REG_RD_ADDR_iop_sw_cfg_rw_gio_oe_mask 100 293#define REG_WR_ADDR_iop_sw_cfg_rw_gio_oe_mask 100 294 295/* Register rw_pinmapping, scope iop_sw_cfg, type rw */ 296typedef struct { 297 unsigned int bus_byte0 : 2; 298 unsigned int bus_byte1 : 2; 299 unsigned int bus_byte2 : 2; 300 unsigned int bus_byte3 : 2; 301 unsigned int gio3_0 : 2; 302 unsigned int gio7_4 : 2; 303 unsigned int gio11_8 : 2; 304 unsigned int gio15_12 : 2; 305 unsigned int gio19_16 : 2; 306 unsigned int gio23_20 : 2; 307 unsigned int gio27_24 : 2; 308 unsigned int gio31_28 : 2; 309 unsigned int dummy1 : 8; 310} reg_iop_sw_cfg_rw_pinmapping; 311#define REG_RD_ADDR_iop_sw_cfg_rw_pinmapping 104 312#define REG_WR_ADDR_iop_sw_cfg_rw_pinmapping 104 313 314/* Register rw_bus_out_cfg, scope iop_sw_cfg, type rw */ 315typedef struct { 316 unsigned int bus_lo : 2; 317 unsigned int bus_hi : 2; 318 unsigned int bus_lo_oe : 2; 319 unsigned int bus_hi_oe : 2; 320 unsigned int dummy1 : 24; 321} reg_iop_sw_cfg_rw_bus_out_cfg; 322#define REG_RD_ADDR_iop_sw_cfg_rw_bus_out_cfg 108 323#define REG_WR_ADDR_iop_sw_cfg_rw_bus_out_cfg 108 324 325/* Register rw_gio_out_grp0_cfg, scope iop_sw_cfg, type rw */ 326typedef struct { 327 unsigned int gio0 : 3; 328 unsigned int gio0_oe : 1; 329 unsigned int gio1 : 3; 330 unsigned int gio1_oe : 1; 331 unsigned int gio2 : 3; 332 unsigned int gio2_oe : 1; 333 unsigned int gio3 : 3; 334 unsigned int gio3_oe : 1; 335 unsigned int dummy1 : 16; 336} reg_iop_sw_cfg_rw_gio_out_grp0_cfg; 337#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp0_cfg 112 338#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp0_cfg 112 339 340/* Register rw_gio_out_grp1_cfg, scope iop_sw_cfg, type rw */ 341typedef struct { 342 unsigned int gio4 : 3; 343 unsigned int gio4_oe : 1; 344 unsigned int gio5 : 3; 345 unsigned int gio5_oe : 1; 346 unsigned int gio6 : 3; 347 unsigned int gio6_oe : 1; 348 unsigned int gio7 : 3; 349 unsigned int gio7_oe : 1; 350 unsigned int dummy1 : 16; 351} reg_iop_sw_cfg_rw_gio_out_grp1_cfg; 352#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp1_cfg 116 353#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp1_cfg 116 354 355/* Register rw_gio_out_grp2_cfg, scope iop_sw_cfg, type rw */ 356typedef struct { 357 unsigned int gio8 : 3; 358 unsigned int gio8_oe : 1; 359 unsigned int gio9 : 3; 360 unsigned int gio9_oe : 1; 361 unsigned int gio10 : 3; 362 unsigned int gio10_oe : 1; 363 unsigned int gio11 : 3; 364 unsigned int gio11_oe : 1; 365 unsigned int dummy1 : 16; 366} reg_iop_sw_cfg_rw_gio_out_grp2_cfg; 367#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp2_cfg 120 368#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp2_cfg 120 369 370/* Register rw_gio_out_grp3_cfg, scope iop_sw_cfg, type rw */ 371typedef struct { 372 unsigned int gio12 : 3; 373 unsigned int gio12_oe : 1; 374 unsigned int gio13 : 3; 375 unsigned int gio13_oe : 1; 376 unsigned int gio14 : 3; 377 unsigned int gio14_oe : 1; 378 unsigned int gio15 : 3; 379 unsigned int gio15_oe : 1; 380 unsigned int dummy1 : 16; 381} reg_iop_sw_cfg_rw_gio_out_grp3_cfg; 382#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp3_cfg 124 383#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp3_cfg 124 384 385/* Register rw_gio_out_grp4_cfg, scope iop_sw_cfg, type rw */ 386typedef struct { 387 unsigned int gio16 : 3; 388 unsigned int gio16_oe : 1; 389 unsigned int gio17 : 3; 390 unsigned int gio17_oe : 1; 391 unsigned int gio18 : 3; 392 unsigned int gio18_oe : 1; 393 unsigned int gio19 : 3; 394 unsigned int gio19_oe : 1; 395 unsigned int dummy1 : 16; 396} reg_iop_sw_cfg_rw_gio_out_grp4_cfg; 397#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp4_cfg 128 398#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp4_cfg 128 399 400/* Register rw_gio_out_grp5_cfg, scope iop_sw_cfg, type rw */ 401typedef struct { 402 unsigned int gio20 : 3; 403 unsigned int gio20_oe : 1; 404 unsigned int gio21 : 3; 405 unsigned int gio21_oe : 1; 406 unsigned int gio22 : 3; 407 unsigned int gio22_oe : 1; 408 unsigned int gio23 : 3; 409 unsigned int gio23_oe : 1; 410 unsigned int dummy1 : 16; 411} reg_iop_sw_cfg_rw_gio_out_grp5_cfg; 412#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp5_cfg 132 413#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp5_cfg 132 414 415/* Register rw_gio_out_grp6_cfg, scope iop_sw_cfg, type rw */ 416typedef struct { 417 unsigned int gio24 : 3; 418 unsigned int gio24_oe : 1; 419 unsigned int gio25 : 3; 420 unsigned int gio25_oe : 1; 421 unsigned int gio26 : 3; 422 unsigned int gio26_oe : 1; 423 unsigned int gio27 : 3; 424 unsigned int gio27_oe : 1; 425 unsigned int dummy1 : 16; 426} reg_iop_sw_cfg_rw_gio_out_grp6_cfg; 427#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp6_cfg 136 428#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp6_cfg 136 429 430/* Register rw_gio_out_grp7_cfg, scope iop_sw_cfg, type rw */ 431typedef struct { 432 unsigned int gio28 : 3; 433 unsigned int gio28_oe : 1; 434 unsigned int gio29 : 3; 435 unsigned int gio29_oe : 1; 436 unsigned int gio30 : 3; 437 unsigned int gio30_oe : 1; 438 unsigned int gio31 : 3; 439 unsigned int gio31_oe : 1; 440 unsigned int dummy1 : 16; 441} reg_iop_sw_cfg_rw_gio_out_grp7_cfg; 442#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp7_cfg 140 443#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp7_cfg 140 444 445/* Register rw_spu_cfg, scope iop_sw_cfg, type rw */ 446typedef struct { 447 unsigned int bus0_in : 1; 448 unsigned int bus1_in : 1; 449 unsigned int dummy1 : 30; 450} reg_iop_sw_cfg_rw_spu_cfg; 451#define REG_RD_ADDR_iop_sw_cfg_rw_spu_cfg 144 452#define REG_WR_ADDR_iop_sw_cfg_rw_spu_cfg 144 453 454/* Register rw_timer_grp0_cfg, scope iop_sw_cfg, type rw */ 455typedef struct { 456 unsigned int ext_clk : 3; 457 unsigned int tmr0_en : 2; 458 unsigned int tmr1_en : 2; 459 unsigned int tmr2_en : 2; 460 unsigned int tmr3_en : 2; 461 unsigned int tmr0_dis : 2; 462 unsigned int tmr1_dis : 2; 463 unsigned int tmr2_dis : 2; 464 unsigned int tmr3_dis : 2; 465 unsigned int dummy1 : 13; 466} reg_iop_sw_cfg_rw_timer_grp0_cfg; 467#define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp0_cfg 148 468#define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp0_cfg 148 469 470/* Register rw_timer_grp1_cfg, scope iop_sw_cfg, type rw */ 471typedef struct { 472 unsigned int ext_clk : 3; 473 unsigned int tmr0_en : 2; 474 unsigned int tmr1_en : 2; 475 unsigned int tmr2_en : 2; 476 unsigned int tmr3_en : 2; 477 unsigned int tmr0_dis : 2; 478 unsigned int tmr1_dis : 2; 479 unsigned int tmr2_dis : 2; 480 unsigned int tmr3_dis : 2; 481 unsigned int dummy1 : 13; 482} reg_iop_sw_cfg_rw_timer_grp1_cfg; 483#define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp1_cfg 152 484#define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp1_cfg 152 485 486/* Register rw_trigger_grps_cfg, scope iop_sw_cfg, type rw */ 487typedef struct { 488 unsigned int grp0_dis : 1; 489 unsigned int grp0_en : 1; 490 unsigned int grp1_dis : 1; 491 unsigned int grp1_en : 1; 492 unsigned int grp2_dis : 1; 493 unsigned int grp2_en : 1; 494 unsigned int grp3_dis : 1; 495 unsigned int grp3_en : 1; 496 unsigned int grp4_dis : 1; 497 unsigned int grp4_en : 1; 498 unsigned int grp5_dis : 1; 499 unsigned int grp5_en : 1; 500 unsigned int grp6_dis : 1; 501 unsigned int grp6_en : 1; 502 unsigned int grp7_dis : 1; 503 unsigned int grp7_en : 1; 504 unsigned int dummy1 : 16; 505} reg_iop_sw_cfg_rw_trigger_grps_cfg; 506#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grps_cfg 156 507#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grps_cfg 156 508 509/* Register rw_pdp_cfg, scope iop_sw_cfg, type rw */ 510typedef struct { 511 unsigned int out_strb : 4; 512 unsigned int in_src : 2; 513 unsigned int in_size : 3; 514 unsigned int in_last : 2; 515 unsigned int in_strb : 4; 516 unsigned int dummy1 : 17; 517} reg_iop_sw_cfg_rw_pdp_cfg; 518#define REG_RD_ADDR_iop_sw_cfg_rw_pdp_cfg 160 519#define REG_WR_ADDR_iop_sw_cfg_rw_pdp_cfg 160 520 521/* Register rw_sdp_cfg, scope iop_sw_cfg, type rw */ 522typedef struct { 523 unsigned int sdp_out_strb : 3; 524 unsigned int sdp_in_data : 3; 525 unsigned int sdp_in_last : 2; 526 unsigned int sdp_in_strb : 3; 527 unsigned int dummy1 : 21; 528} reg_iop_sw_cfg_rw_sdp_cfg; 529#define REG_RD_ADDR_iop_sw_cfg_rw_sdp_cfg 164 530#define REG_WR_ADDR_iop_sw_cfg_rw_sdp_cfg 164 531 532 533/* Constants */ 534enum { 535 regk_iop_sw_cfg_a = 0x00000001, 536 regk_iop_sw_cfg_b = 0x00000002, 537 regk_iop_sw_cfg_bus = 0x00000000, 538 regk_iop_sw_cfg_bus_rot16 = 0x00000002, 539 regk_iop_sw_cfg_bus_rot24 = 0x00000003, 540 regk_iop_sw_cfg_bus_rot8 = 0x00000001, 541 regk_iop_sw_cfg_clk12 = 0x00000000, 542 regk_iop_sw_cfg_cpu = 0x00000000, 543 regk_iop_sw_cfg_gated_clk0 = 0x0000000e, 544 regk_iop_sw_cfg_gated_clk1 = 0x0000000f, 545 regk_iop_sw_cfg_gio0 = 0x00000004, 546 regk_iop_sw_cfg_gio1 = 0x00000001, 547 regk_iop_sw_cfg_gio2 = 0x00000005, 548 regk_iop_sw_cfg_gio3 = 0x00000002, 549 regk_iop_sw_cfg_gio4 = 0x00000006, 550 regk_iop_sw_cfg_gio5 = 0x00000003, 551 regk_iop_sw_cfg_gio6 = 0x00000007, 552 regk_iop_sw_cfg_gio7 = 0x00000004, 553 regk_iop_sw_cfg_gio_in18 = 0x00000002, 554 regk_iop_sw_cfg_gio_in19 = 0x00000003, 555 regk_iop_sw_cfg_gio_in20 = 0x00000004, 556 regk_iop_sw_cfg_gio_in21 = 0x00000005, 557 regk_iop_sw_cfg_gio_in26 = 0x00000006, 558 regk_iop_sw_cfg_gio_in27 = 0x00000007, 559 regk_iop_sw_cfg_gio_in4 = 0x00000000, 560 regk_iop_sw_cfg_gio_in5 = 0x00000001, 561 regk_iop_sw_cfg_last_timer_grp0_tmr2 = 0x00000001, 562 regk_iop_sw_cfg_last_timer_grp1_tmr2 = 0x00000002, 563 regk_iop_sw_cfg_last_timer_grp1_tmr3 = 0x00000003, 564 regk_iop_sw_cfg_mpu = 0x00000001, 565 regk_iop_sw_cfg_none = 0x00000000, 566 regk_iop_sw_cfg_pdp_out = 0x00000001, 567 regk_iop_sw_cfg_pdp_out_hi = 0x00000001, 568 regk_iop_sw_cfg_pdp_out_lo = 0x00000000, 569 regk_iop_sw_cfg_rw_bus_mask_default = 0x00000000, 570 regk_iop_sw_cfg_rw_bus_oe_mask_default = 0x00000000, 571 regk_iop_sw_cfg_rw_bus_out_cfg_default = 0x00000000, 572 regk_iop_sw_cfg_rw_crc_par_owner_default = 0x00000000, 573 regk_iop_sw_cfg_rw_dmc_in_owner_default = 0x00000000, 574 regk_iop_sw_cfg_rw_dmc_out_owner_default = 0x00000000, 575 regk_iop_sw_cfg_rw_fifo_in_extra_owner_default = 0x00000000, 576 regk_iop_sw_cfg_rw_fifo_in_owner_default = 0x00000000, 577 regk_iop_sw_cfg_rw_fifo_out_extra_owner_default = 0x00000000, 578 regk_iop_sw_cfg_rw_fifo_out_owner_default = 0x00000000, 579 regk_iop_sw_cfg_rw_gio_mask_default = 0x00000000, 580 regk_iop_sw_cfg_rw_gio_oe_mask_default = 0x00000000, 581 regk_iop_sw_cfg_rw_gio_out_grp0_cfg_default = 0x00000000, 582 regk_iop_sw_cfg_rw_gio_out_grp1_cfg_default = 0x00000000, 583 regk_iop_sw_cfg_rw_gio_out_grp2_cfg_default = 0x00000000, 584 regk_iop_sw_cfg_rw_gio_out_grp3_cfg_default = 0x00000000, 585 regk_iop_sw_cfg_rw_gio_out_grp4_cfg_default = 0x00000000, 586 regk_iop_sw_cfg_rw_gio_out_grp5_cfg_default = 0x00000000, 587 regk_iop_sw_cfg_rw_gio_out_grp6_cfg_default = 0x00000000, 588 regk_iop_sw_cfg_rw_gio_out_grp7_cfg_default = 0x00000000, 589 regk_iop_sw_cfg_rw_pdp_cfg_default = 0x00000000, 590 regk_iop_sw_cfg_rw_pinmapping_default = 0x00555555, 591 regk_iop_sw_cfg_rw_sap_in_owner_default = 0x00000000, 592 regk_iop_sw_cfg_rw_sap_out_owner_default = 0x00000000, 593 regk_iop_sw_cfg_rw_scrc_in_owner_default = 0x00000000, 594 regk_iop_sw_cfg_rw_scrc_out_owner_default = 0x00000000, 595 regk_iop_sw_cfg_rw_sdp_cfg_default = 0x00000000, 596 regk_iop_sw_cfg_rw_spu_cfg_default = 0x00000000, 597 regk_iop_sw_cfg_rw_spu_owner_default = 0x00000000, 598 regk_iop_sw_cfg_rw_timer_grp0_cfg_default = 0x00000000, 599 regk_iop_sw_cfg_rw_timer_grp0_owner_default = 0x00000000, 600 regk_iop_sw_cfg_rw_timer_grp1_cfg_default = 0x00000000, 601 regk_iop_sw_cfg_rw_timer_grp1_owner_default = 0x00000000, 602 regk_iop_sw_cfg_rw_trigger_grp0_owner_default = 0x00000000, 603 regk_iop_sw_cfg_rw_trigger_grp1_owner_default = 0x00000000, 604 regk_iop_sw_cfg_rw_trigger_grp2_owner_default = 0x00000000, 605 regk_iop_sw_cfg_rw_trigger_grp3_owner_default = 0x00000000, 606 regk_iop_sw_cfg_rw_trigger_grp4_owner_default = 0x00000000, 607 regk_iop_sw_cfg_rw_trigger_grp5_owner_default = 0x00000000, 608 regk_iop_sw_cfg_rw_trigger_grp6_owner_default = 0x00000000, 609 regk_iop_sw_cfg_rw_trigger_grp7_owner_default = 0x00000000, 610 regk_iop_sw_cfg_rw_trigger_grps_cfg_default = 0x00000000, 611 regk_iop_sw_cfg_sdp_out = 0x00000004, 612 regk_iop_sw_cfg_size16 = 0x00000002, 613 regk_iop_sw_cfg_size24 = 0x00000003, 614 regk_iop_sw_cfg_size32 = 0x00000004, 615 regk_iop_sw_cfg_size8 = 0x00000001, 616 regk_iop_sw_cfg_spu = 0x00000002, 617 regk_iop_sw_cfg_spu_bus_out0_hi = 0x00000002, 618 regk_iop_sw_cfg_spu_bus_out0_lo = 0x00000002, 619 regk_iop_sw_cfg_spu_bus_out1_hi = 0x00000003, 620 regk_iop_sw_cfg_spu_bus_out1_lo = 0x00000003, 621 regk_iop_sw_cfg_spu_g0 = 0x00000007, 622 regk_iop_sw_cfg_spu_g1 = 0x00000007, 623 regk_iop_sw_cfg_spu_g2 = 0x00000007, 624 regk_iop_sw_cfg_spu_g3 = 0x00000007, 625 regk_iop_sw_cfg_spu_g4 = 0x00000007, 626 regk_iop_sw_cfg_spu_g5 = 0x00000007, 627 regk_iop_sw_cfg_spu_g6 = 0x00000007, 628 regk_iop_sw_cfg_spu_g7 = 0x00000007, 629 regk_iop_sw_cfg_spu_gio0 = 0x00000000, 630 regk_iop_sw_cfg_spu_gio1 = 0x00000001, 631 regk_iop_sw_cfg_spu_gio5 = 0x00000005, 632 regk_iop_sw_cfg_spu_gio6 = 0x00000006, 633 regk_iop_sw_cfg_spu_gio7 = 0x00000007, 634 regk_iop_sw_cfg_spu_gio_out0 = 0x00000008, 635 regk_iop_sw_cfg_spu_gio_out1 = 0x00000009, 636 regk_iop_sw_cfg_spu_gio_out2 = 0x0000000a, 637 regk_iop_sw_cfg_spu_gio_out3 = 0x0000000b, 638 regk_iop_sw_cfg_spu_gio_out4 = 0x0000000c, 639 regk_iop_sw_cfg_spu_gio_out5 = 0x0000000d, 640 regk_iop_sw_cfg_spu_gio_out6 = 0x0000000e, 641 regk_iop_sw_cfg_spu_gio_out7 = 0x0000000f, 642 regk_iop_sw_cfg_spu_gioout0 = 0x00000000, 643 regk_iop_sw_cfg_spu_gioout1 = 0x00000000, 644 regk_iop_sw_cfg_spu_gioout10 = 0x00000007, 645 regk_iop_sw_cfg_spu_gioout11 = 0x00000007, 646 regk_iop_sw_cfg_spu_gioout12 = 0x00000007, 647 regk_iop_sw_cfg_spu_gioout13 = 0x00000007, 648 regk_iop_sw_cfg_spu_gioout14 = 0x00000007, 649 regk_iop_sw_cfg_spu_gioout15 = 0x00000007, 650 regk_iop_sw_cfg_spu_gioout16 = 0x00000007, 651 regk_iop_sw_cfg_spu_gioout17 = 0x00000007, 652 regk_iop_sw_cfg_spu_gioout18 = 0x00000007, 653 regk_iop_sw_cfg_spu_gioout19 = 0x00000007, 654 regk_iop_sw_cfg_spu_gioout2 = 0x00000001, 655 regk_iop_sw_cfg_spu_gioout20 = 0x00000007, 656 regk_iop_sw_cfg_spu_gioout21 = 0x00000007, 657 regk_iop_sw_cfg_spu_gioout22 = 0x00000007, 658 regk_iop_sw_cfg_spu_gioout23 = 0x00000007, 659 regk_iop_sw_cfg_spu_gioout24 = 0x00000007, 660 regk_iop_sw_cfg_spu_gioout25 = 0x00000007, 661 regk_iop_sw_cfg_spu_gioout26 = 0x00000007, 662 regk_iop_sw_cfg_spu_gioout27 = 0x00000007, 663 regk_iop_sw_cfg_spu_gioout28 = 0x00000007, 664 regk_iop_sw_cfg_spu_gioout29 = 0x00000007, 665 regk_iop_sw_cfg_spu_gioout3 = 0x00000001, 666 regk_iop_sw_cfg_spu_gioout30 = 0x00000007, 667 regk_iop_sw_cfg_spu_gioout31 = 0x00000007, 668 regk_iop_sw_cfg_spu_gioout4 = 0x00000002, 669 regk_iop_sw_cfg_spu_gioout5 = 0x00000002, 670 regk_iop_sw_cfg_spu_gioout6 = 0x00000003, 671 regk_iop_sw_cfg_spu_gioout7 = 0x00000003, 672 regk_iop_sw_cfg_spu_gioout8 = 0x00000007, 673 regk_iop_sw_cfg_spu_gioout9 = 0x00000007, 674 regk_iop_sw_cfg_strb_timer_grp0_tmr0 = 0x00000001, 675 regk_iop_sw_cfg_strb_timer_grp0_tmr1 = 0x00000002, 676 regk_iop_sw_cfg_strb_timer_grp1_tmr0 = 0x00000003, 677 regk_iop_sw_cfg_strb_timer_grp1_tmr1 = 0x00000002, 678 regk_iop_sw_cfg_timer_grp0 = 0x00000000, 679 regk_iop_sw_cfg_timer_grp0_rot = 0x00000001, 680 regk_iop_sw_cfg_timer_grp0_strb0 = 0x00000005, 681 regk_iop_sw_cfg_timer_grp0_strb1 = 0x00000005, 682 regk_iop_sw_cfg_timer_grp0_strb2 = 0x00000005, 683 regk_iop_sw_cfg_timer_grp0_strb3 = 0x00000005, 684 regk_iop_sw_cfg_timer_grp0_tmr0 = 0x00000002, 685 regk_iop_sw_cfg_timer_grp1 = 0x00000000, 686 regk_iop_sw_cfg_timer_grp1_rot = 0x00000001, 687 regk_iop_sw_cfg_timer_grp1_strb0 = 0x00000006, 688 regk_iop_sw_cfg_timer_grp1_strb1 = 0x00000006, 689 regk_iop_sw_cfg_timer_grp1_strb2 = 0x00000006, 690 regk_iop_sw_cfg_timer_grp1_strb3 = 0x00000006, 691 regk_iop_sw_cfg_timer_grp1_tmr0 = 0x00000003, 692 regk_iop_sw_cfg_trig0_0 = 0x00000000, 693 regk_iop_sw_cfg_trig0_1 = 0x00000000, 694 regk_iop_sw_cfg_trig0_2 = 0x00000000, 695 regk_iop_sw_cfg_trig0_3 = 0x00000000, 696 regk_iop_sw_cfg_trig1_0 = 0x00000000, 697 regk_iop_sw_cfg_trig1_1 = 0x00000000, 698 regk_iop_sw_cfg_trig1_2 = 0x00000000, 699 regk_iop_sw_cfg_trig1_3 = 0x00000000, 700 regk_iop_sw_cfg_trig2_0 = 0x00000001, 701 regk_iop_sw_cfg_trig2_1 = 0x00000001, 702 regk_iop_sw_cfg_trig2_2 = 0x00000001, 703 regk_iop_sw_cfg_trig2_3 = 0x00000001, 704 regk_iop_sw_cfg_trig3_0 = 0x00000001, 705 regk_iop_sw_cfg_trig3_1 = 0x00000001, 706 regk_iop_sw_cfg_trig3_2 = 0x00000001, 707 regk_iop_sw_cfg_trig3_3 = 0x00000001, 708 regk_iop_sw_cfg_trig4_0 = 0x00000002, 709 regk_iop_sw_cfg_trig4_1 = 0x00000002, 710 regk_iop_sw_cfg_trig4_2 = 0x00000002, 711 regk_iop_sw_cfg_trig4_3 = 0x00000002, 712 regk_iop_sw_cfg_trig5_0 = 0x00000002, 713 regk_iop_sw_cfg_trig5_1 = 0x00000002, 714 regk_iop_sw_cfg_trig5_2 = 0x00000002, 715 regk_iop_sw_cfg_trig5_3 = 0x00000002, 716 regk_iop_sw_cfg_trig6_0 = 0x00000003, 717 regk_iop_sw_cfg_trig6_1 = 0x00000003, 718 regk_iop_sw_cfg_trig6_2 = 0x00000003, 719 regk_iop_sw_cfg_trig6_3 = 0x00000003, 720 regk_iop_sw_cfg_trig7_0 = 0x00000003, 721 regk_iop_sw_cfg_trig7_1 = 0x00000003, 722 regk_iop_sw_cfg_trig7_2 = 0x00000003, 723 regk_iop_sw_cfg_trig7_3 = 0x00000003 724}; 725#endif /* __iop_sw_cfg_defs_h */ 726