1#ifndef __iop_sap_out_defs_h 2#define __iop_sap_out_defs_h 3 4/* 5 * This file is autogenerated from 6 * file: iop_sap_out.r 7 * 8 * by ../../../tools/rdesc/bin/rdes2c -outfile iop_sap_out_defs.h iop_sap_out.r 9 * Any changes here will be lost. 10 * 11 * -*- buffer-read-only: t -*- 12 */ 13/* Main access macros */ 14#ifndef REG_RD 15#define REG_RD( scope, inst, reg ) \ 16 REG_READ( reg_##scope##_##reg, \ 17 (inst) + REG_RD_ADDR_##scope##_##reg ) 18#endif 19 20#ifndef REG_WR 21#define REG_WR( scope, inst, reg, val ) \ 22 REG_WRITE( reg_##scope##_##reg, \ 23 (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) 24#endif 25 26#ifndef REG_RD_VECT 27#define REG_RD_VECT( scope, inst, reg, index ) \ 28 REG_READ( reg_##scope##_##reg, \ 29 (inst) + REG_RD_ADDR_##scope##_##reg + \ 30 (index) * STRIDE_##scope##_##reg ) 31#endif 32 33#ifndef REG_WR_VECT 34#define REG_WR_VECT( scope, inst, reg, index, val ) \ 35 REG_WRITE( reg_##scope##_##reg, \ 36 (inst) + REG_WR_ADDR_##scope##_##reg + \ 37 (index) * STRIDE_##scope##_##reg, (val) ) 38#endif 39 40#ifndef REG_RD_INT 41#define REG_RD_INT( scope, inst, reg ) \ 42 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) 43#endif 44 45#ifndef REG_WR_INT 46#define REG_WR_INT( scope, inst, reg, val ) \ 47 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) 48#endif 49 50#ifndef REG_RD_INT_VECT 51#define REG_RD_INT_VECT( scope, inst, reg, index ) \ 52 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ 53 (index) * STRIDE_##scope##_##reg ) 54#endif 55 56#ifndef REG_WR_INT_VECT 57#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ 58 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ 59 (index) * STRIDE_##scope##_##reg, (val) ) 60#endif 61 62#ifndef REG_TYPE_CONV 63#define REG_TYPE_CONV( type, orgtype, val ) \ 64 ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) 65#endif 66 67#ifndef reg_page_size 68#define reg_page_size 8192 69#endif 70 71#ifndef REG_ADDR 72#define REG_ADDR( scope, inst, reg ) \ 73 ( (inst) + REG_RD_ADDR_##scope##_##reg ) 74#endif 75 76#ifndef REG_ADDR_VECT 77#define REG_ADDR_VECT( scope, inst, reg, index ) \ 78 ( (inst) + REG_RD_ADDR_##scope##_##reg + \ 79 (index) * STRIDE_##scope##_##reg ) 80#endif 81 82/* C-code for register scope iop_sap_out */ 83 84/* Register rw_gen_gated, scope iop_sap_out, type rw */ 85typedef struct { 86 unsigned int clk0_src : 2; 87 unsigned int clk0_gate_src : 2; 88 unsigned int clk0_force_src : 3; 89 unsigned int clk1_src : 2; 90 unsigned int clk1_gate_src : 2; 91 unsigned int clk1_force_src : 3; 92 unsigned int dummy1 : 18; 93} reg_iop_sap_out_rw_gen_gated; 94#define REG_RD_ADDR_iop_sap_out_rw_gen_gated 0 95#define REG_WR_ADDR_iop_sap_out_rw_gen_gated 0 96 97/* Register rw_bus, scope iop_sap_out, type rw */ 98typedef struct { 99 unsigned int byte0_clk_sel : 2; 100 unsigned int byte0_clk_ext : 2; 101 unsigned int byte0_gated_clk : 1; 102 unsigned int byte0_clk_inv : 1; 103 unsigned int byte0_delay : 1; 104 unsigned int byte1_clk_sel : 2; 105 unsigned int byte1_clk_ext : 2; 106 unsigned int byte1_gated_clk : 1; 107 unsigned int byte1_clk_inv : 1; 108 unsigned int byte1_delay : 1; 109 unsigned int byte2_clk_sel : 2; 110 unsigned int byte2_clk_ext : 2; 111 unsigned int byte2_gated_clk : 1; 112 unsigned int byte2_clk_inv : 1; 113 unsigned int byte2_delay : 1; 114 unsigned int byte3_clk_sel : 2; 115 unsigned int byte3_clk_ext : 2; 116 unsigned int byte3_gated_clk : 1; 117 unsigned int byte3_clk_inv : 1; 118 unsigned int byte3_delay : 1; 119 unsigned int dummy1 : 4; 120} reg_iop_sap_out_rw_bus; 121#define REG_RD_ADDR_iop_sap_out_rw_bus 4 122#define REG_WR_ADDR_iop_sap_out_rw_bus 4 123 124/* Register rw_bus_lo_oe, scope iop_sap_out, type rw */ 125typedef struct { 126 unsigned int byte0_clk_sel : 2; 127 unsigned int byte0_clk_ext : 2; 128 unsigned int byte0_gated_clk : 1; 129 unsigned int byte0_clk_inv : 1; 130 unsigned int byte0_delay : 1; 131 unsigned int byte0_logic : 2; 132 unsigned int byte0_logic_src : 2; 133 unsigned int byte1_clk_sel : 2; 134 unsigned int byte1_clk_ext : 2; 135 unsigned int byte1_gated_clk : 1; 136 unsigned int byte1_clk_inv : 1; 137 unsigned int byte1_delay : 1; 138 unsigned int byte1_logic : 2; 139 unsigned int byte1_logic_src : 2; 140 unsigned int dummy1 : 10; 141} reg_iop_sap_out_rw_bus_lo_oe; 142#define REG_RD_ADDR_iop_sap_out_rw_bus_lo_oe 8 143#define REG_WR_ADDR_iop_sap_out_rw_bus_lo_oe 8 144 145/* Register rw_bus_hi_oe, scope iop_sap_out, type rw */ 146typedef struct { 147 unsigned int byte2_clk_sel : 2; 148 unsigned int byte2_clk_ext : 2; 149 unsigned int byte2_gated_clk : 1; 150 unsigned int byte2_clk_inv : 1; 151 unsigned int byte2_delay : 1; 152 unsigned int byte2_logic : 2; 153 unsigned int byte2_logic_src : 2; 154 unsigned int byte3_clk_sel : 2; 155 unsigned int byte3_clk_ext : 2; 156 unsigned int byte3_gated_clk : 1; 157 unsigned int byte3_clk_inv : 1; 158 unsigned int byte3_delay : 1; 159 unsigned int byte3_logic : 2; 160 unsigned int byte3_logic_src : 2; 161 unsigned int dummy1 : 10; 162} reg_iop_sap_out_rw_bus_hi_oe; 163#define REG_RD_ADDR_iop_sap_out_rw_bus_hi_oe 12 164#define REG_WR_ADDR_iop_sap_out_rw_bus_hi_oe 12 165 166#define STRIDE_iop_sap_out_rw_gio 4 167/* Register rw_gio, scope iop_sap_out, type rw */ 168typedef struct { 169 unsigned int out_clk_sel : 3; 170 unsigned int out_clk_ext : 2; 171 unsigned int out_gated_clk : 1; 172 unsigned int out_clk_inv : 1; 173 unsigned int out_delay : 1; 174 unsigned int out_logic : 2; 175 unsigned int out_logic_src : 2; 176 unsigned int oe_clk_sel : 3; 177 unsigned int oe_clk_ext : 2; 178 unsigned int oe_gated_clk : 1; 179 unsigned int oe_clk_inv : 1; 180 unsigned int oe_delay : 1; 181 unsigned int oe_logic : 2; 182 unsigned int oe_logic_src : 2; 183 unsigned int dummy1 : 8; 184} reg_iop_sap_out_rw_gio; 185#define REG_RD_ADDR_iop_sap_out_rw_gio 16 186#define REG_WR_ADDR_iop_sap_out_rw_gio 16 187 188 189/* Constants */ 190enum { 191 regk_iop_sap_out_always = 0x00000001, 192 regk_iop_sap_out_and = 0x00000002, 193 regk_iop_sap_out_clk0 = 0x00000000, 194 regk_iop_sap_out_clk1 = 0x00000001, 195 regk_iop_sap_out_clk12 = 0x00000004, 196 regk_iop_sap_out_clk200 = 0x00000000, 197 regk_iop_sap_out_ext = 0x00000002, 198 regk_iop_sap_out_gated = 0x00000003, 199 regk_iop_sap_out_gio0 = 0x00000000, 200 regk_iop_sap_out_gio1 = 0x00000000, 201 regk_iop_sap_out_gio16 = 0x00000002, 202 regk_iop_sap_out_gio17 = 0x00000002, 203 regk_iop_sap_out_gio24 = 0x00000003, 204 regk_iop_sap_out_gio25 = 0x00000003, 205 regk_iop_sap_out_gio8 = 0x00000001, 206 regk_iop_sap_out_gio9 = 0x00000001, 207 regk_iop_sap_out_gio_out10 = 0x00000005, 208 regk_iop_sap_out_gio_out18 = 0x00000006, 209 regk_iop_sap_out_gio_out2 = 0x00000004, 210 regk_iop_sap_out_gio_out26 = 0x00000007, 211 regk_iop_sap_out_inv = 0x00000001, 212 regk_iop_sap_out_nand = 0x00000003, 213 regk_iop_sap_out_no = 0x00000000, 214 regk_iop_sap_out_none = 0x00000000, 215 regk_iop_sap_out_one = 0x00000001, 216 regk_iop_sap_out_rw_bus_default = 0x00000000, 217 regk_iop_sap_out_rw_bus_hi_oe_default = 0x00000000, 218 regk_iop_sap_out_rw_bus_lo_oe_default = 0x00000000, 219 regk_iop_sap_out_rw_gen_gated_default = 0x00000000, 220 regk_iop_sap_out_rw_gio_default = 0x00000000, 221 regk_iop_sap_out_rw_gio_size = 0x00000020, 222 regk_iop_sap_out_spu_gio6 = 0x00000002, 223 regk_iop_sap_out_spu_gio7 = 0x00000003, 224 regk_iop_sap_out_timer_grp0_tmr2 = 0x00000000, 225 regk_iop_sap_out_timer_grp0_tmr3 = 0x00000001, 226 regk_iop_sap_out_timer_grp1_tmr2 = 0x00000002, 227 regk_iop_sap_out_timer_grp1_tmr3 = 0x00000003, 228 regk_iop_sap_out_tmr200 = 0x00000001, 229 regk_iop_sap_out_yes = 0x00000001 230}; 231#endif /* __iop_sap_out_defs_h */ 232