1#ifndef __iop_sw_mpu_defs_asm_h 2#define __iop_sw_mpu_defs_asm_h 3 4/* 5 * This file is autogenerated from 6 * file: iop_sw_mpu.r 7 * 8 * by ../../../tools/rdesc/bin/rdes2c -asm -outfile iop_sw_mpu_defs_asm.h iop_sw_mpu.r 9 * Any changes here will be lost. 10 * 11 * -*- buffer-read-only: t -*- 12 */ 13 14#ifndef REG_FIELD 15#define REG_FIELD( scope, reg, field, value ) \ 16 REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) 17#define REG_FIELD_X_( value, shift ) ((value) << shift) 18#endif 19 20#ifndef REG_STATE 21#define REG_STATE( scope, reg, field, symbolic_value ) \ 22 REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) 23#define REG_STATE_X_( k, shift ) (k << shift) 24#endif 25 26#ifndef REG_MASK 27#define REG_MASK( scope, reg, field ) \ 28 REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) 29#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) 30#endif 31 32#ifndef REG_LSB 33#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb 34#endif 35 36#ifndef REG_BIT 37#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit 38#endif 39 40#ifndef REG_ADDR 41#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) 42#define REG_ADDR_X_( inst, offs ) ((inst) + offs) 43#endif 44 45#ifndef REG_ADDR_VECT 46#define REG_ADDR_VECT( scope, inst, reg, index ) \ 47 REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ 48 STRIDE_##scope##_##reg ) 49#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ 50 ((inst) + offs + (index) * stride) 51#endif 52 53/* Register rw_sw_cfg_owner, scope iop_sw_mpu, type rw */ 54#define reg_iop_sw_mpu_rw_sw_cfg_owner___cfg___lsb 0 55#define reg_iop_sw_mpu_rw_sw_cfg_owner___cfg___width 2 56#define reg_iop_sw_mpu_rw_sw_cfg_owner_offset 0 57 58/* Register r_spu_trace, scope iop_sw_mpu, type r */ 59#define reg_iop_sw_mpu_r_spu_trace_offset 4 60 61/* Register r_spu_fsm_trace, scope iop_sw_mpu, type r */ 62#define reg_iop_sw_mpu_r_spu_fsm_trace_offset 8 63 64/* Register rw_mc_ctrl, scope iop_sw_mpu, type rw */ 65#define reg_iop_sw_mpu_rw_mc_ctrl___keep_owner___lsb 0 66#define reg_iop_sw_mpu_rw_mc_ctrl___keep_owner___width 1 67#define reg_iop_sw_mpu_rw_mc_ctrl___keep_owner___bit 0 68#define reg_iop_sw_mpu_rw_mc_ctrl___cmd___lsb 1 69#define reg_iop_sw_mpu_rw_mc_ctrl___cmd___width 2 70#define reg_iop_sw_mpu_rw_mc_ctrl___size___lsb 3 71#define reg_iop_sw_mpu_rw_mc_ctrl___size___width 3 72#define reg_iop_sw_mpu_rw_mc_ctrl___wr_spu_mem___lsb 6 73#define reg_iop_sw_mpu_rw_mc_ctrl___wr_spu_mem___width 1 74#define reg_iop_sw_mpu_rw_mc_ctrl___wr_spu_mem___bit 6 75#define reg_iop_sw_mpu_rw_mc_ctrl_offset 12 76 77/* Register rw_mc_data, scope iop_sw_mpu, type rw */ 78#define reg_iop_sw_mpu_rw_mc_data___val___lsb 0 79#define reg_iop_sw_mpu_rw_mc_data___val___width 32 80#define reg_iop_sw_mpu_rw_mc_data_offset 16 81 82/* Register rw_mc_addr, scope iop_sw_mpu, type rw */ 83#define reg_iop_sw_mpu_rw_mc_addr_offset 20 84 85/* Register rs_mc_data, scope iop_sw_mpu, type rs */ 86#define reg_iop_sw_mpu_rs_mc_data_offset 24 87 88/* Register r_mc_data, scope iop_sw_mpu, type r */ 89#define reg_iop_sw_mpu_r_mc_data_offset 28 90 91/* Register r_mc_stat, scope iop_sw_mpu, type r */ 92#define reg_iop_sw_mpu_r_mc_stat___busy_cpu___lsb 0 93#define reg_iop_sw_mpu_r_mc_stat___busy_cpu___width 1 94#define reg_iop_sw_mpu_r_mc_stat___busy_cpu___bit 0 95#define reg_iop_sw_mpu_r_mc_stat___busy_mpu___lsb 1 96#define reg_iop_sw_mpu_r_mc_stat___busy_mpu___width 1 97#define reg_iop_sw_mpu_r_mc_stat___busy_mpu___bit 1 98#define reg_iop_sw_mpu_r_mc_stat___busy_spu___lsb 2 99#define reg_iop_sw_mpu_r_mc_stat___busy_spu___width 1 100#define reg_iop_sw_mpu_r_mc_stat___busy_spu___bit 2 101#define reg_iop_sw_mpu_r_mc_stat___owned_by_cpu___lsb 3 102#define reg_iop_sw_mpu_r_mc_stat___owned_by_cpu___width 1 103#define reg_iop_sw_mpu_r_mc_stat___owned_by_cpu___bit 3 104#define reg_iop_sw_mpu_r_mc_stat___owned_by_mpu___lsb 4 105#define reg_iop_sw_mpu_r_mc_stat___owned_by_mpu___width 1 106#define reg_iop_sw_mpu_r_mc_stat___owned_by_mpu___bit 4 107#define reg_iop_sw_mpu_r_mc_stat___owned_by_spu___lsb 5 108#define reg_iop_sw_mpu_r_mc_stat___owned_by_spu___width 1 109#define reg_iop_sw_mpu_r_mc_stat___owned_by_spu___bit 5 110#define reg_iop_sw_mpu_r_mc_stat_offset 32 111 112/* Register rw_bus_clr_mask, scope iop_sw_mpu, type rw */ 113#define reg_iop_sw_mpu_rw_bus_clr_mask___byte0___lsb 0 114#define reg_iop_sw_mpu_rw_bus_clr_mask___byte0___width 8 115#define reg_iop_sw_mpu_rw_bus_clr_mask___byte1___lsb 8 116#define reg_iop_sw_mpu_rw_bus_clr_mask___byte1___width 8 117#define reg_iop_sw_mpu_rw_bus_clr_mask___byte2___lsb 16 118#define reg_iop_sw_mpu_rw_bus_clr_mask___byte2___width 8 119#define reg_iop_sw_mpu_rw_bus_clr_mask___byte3___lsb 24 120#define reg_iop_sw_mpu_rw_bus_clr_mask___byte3___width 8 121#define reg_iop_sw_mpu_rw_bus_clr_mask_offset 36 122 123/* Register rw_bus_set_mask, scope iop_sw_mpu, type rw */ 124#define reg_iop_sw_mpu_rw_bus_set_mask___byte0___lsb 0 125#define reg_iop_sw_mpu_rw_bus_set_mask___byte0___width 8 126#define reg_iop_sw_mpu_rw_bus_set_mask___byte1___lsb 8 127#define reg_iop_sw_mpu_rw_bus_set_mask___byte1___width 8 128#define reg_iop_sw_mpu_rw_bus_set_mask___byte2___lsb 16 129#define reg_iop_sw_mpu_rw_bus_set_mask___byte2___width 8 130#define reg_iop_sw_mpu_rw_bus_set_mask___byte3___lsb 24 131#define reg_iop_sw_mpu_rw_bus_set_mask___byte3___width 8 132#define reg_iop_sw_mpu_rw_bus_set_mask_offset 40 133 134/* Register rw_bus_oe_clr_mask, scope iop_sw_mpu, type rw */ 135#define reg_iop_sw_mpu_rw_bus_oe_clr_mask___byte0___lsb 0 136#define reg_iop_sw_mpu_rw_bus_oe_clr_mask___byte0___width 1 137#define reg_iop_sw_mpu_rw_bus_oe_clr_mask___byte0___bit 0 138#define reg_iop_sw_mpu_rw_bus_oe_clr_mask___byte1___lsb 1 139#define reg_iop_sw_mpu_rw_bus_oe_clr_mask___byte1___width 1 140#define reg_iop_sw_mpu_rw_bus_oe_clr_mask___byte1___bit 1 141#define reg_iop_sw_mpu_rw_bus_oe_clr_mask___byte2___lsb 2 142#define reg_iop_sw_mpu_rw_bus_oe_clr_mask___byte2___width 1 143#define reg_iop_sw_mpu_rw_bus_oe_clr_mask___byte2___bit 2 144#define reg_iop_sw_mpu_rw_bus_oe_clr_mask___byte3___lsb 3 145#define reg_iop_sw_mpu_rw_bus_oe_clr_mask___byte3___width 1 146#define reg_iop_sw_mpu_rw_bus_oe_clr_mask___byte3___bit 3 147#define reg_iop_sw_mpu_rw_bus_oe_clr_mask_offset 44 148 149/* Register rw_bus_oe_set_mask, scope iop_sw_mpu, type rw */ 150#define reg_iop_sw_mpu_rw_bus_oe_set_mask___byte0___lsb 0 151#define reg_iop_sw_mpu_rw_bus_oe_set_mask___byte0___width 1 152#define reg_iop_sw_mpu_rw_bus_oe_set_mask___byte0___bit 0 153#define reg_iop_sw_mpu_rw_bus_oe_set_mask___byte1___lsb 1 154#define reg_iop_sw_mpu_rw_bus_oe_set_mask___byte1___width 1 155#define reg_iop_sw_mpu_rw_bus_oe_set_mask___byte1___bit 1 156#define reg_iop_sw_mpu_rw_bus_oe_set_mask___byte2___lsb 2 157#define reg_iop_sw_mpu_rw_bus_oe_set_mask___byte2___width 1 158#define reg_iop_sw_mpu_rw_bus_oe_set_mask___byte2___bit 2 159#define reg_iop_sw_mpu_rw_bus_oe_set_mask___byte3___lsb 3 160#define reg_iop_sw_mpu_rw_bus_oe_set_mask___byte3___width 1 161#define reg_iop_sw_mpu_rw_bus_oe_set_mask___byte3___bit 3 162#define reg_iop_sw_mpu_rw_bus_oe_set_mask_offset 48 163 164/* Register r_bus_in, scope iop_sw_mpu, type r */ 165#define reg_iop_sw_mpu_r_bus_in_offset 52 166 167/* Register rw_gio_clr_mask, scope iop_sw_mpu, type rw */ 168#define reg_iop_sw_mpu_rw_gio_clr_mask___val___lsb 0 169#define reg_iop_sw_mpu_rw_gio_clr_mask___val___width 32 170#define reg_iop_sw_mpu_rw_gio_clr_mask_offset 56 171 172/* Register rw_gio_set_mask, scope iop_sw_mpu, type rw */ 173#define reg_iop_sw_mpu_rw_gio_set_mask___val___lsb 0 174#define reg_iop_sw_mpu_rw_gio_set_mask___val___width 32 175#define reg_iop_sw_mpu_rw_gio_set_mask_offset 60 176 177/* Register rw_gio_oe_clr_mask, scope iop_sw_mpu, type rw */ 178#define reg_iop_sw_mpu_rw_gio_oe_clr_mask___val___lsb 0 179#define reg_iop_sw_mpu_rw_gio_oe_clr_mask___val___width 32 180#define reg_iop_sw_mpu_rw_gio_oe_clr_mask_offset 64 181 182/* Register rw_gio_oe_set_mask, scope iop_sw_mpu, type rw */ 183#define reg_iop_sw_mpu_rw_gio_oe_set_mask___val___lsb 0 184#define reg_iop_sw_mpu_rw_gio_oe_set_mask___val___width 32 185#define reg_iop_sw_mpu_rw_gio_oe_set_mask_offset 68 186 187/* Register r_gio_in, scope iop_sw_mpu, type r */ 188#define reg_iop_sw_mpu_r_gio_in_offset 72 189 190/* Register rw_cpu_intr, scope iop_sw_mpu, type rw */ 191#define reg_iop_sw_mpu_rw_cpu_intr___intr0___lsb 0 192#define reg_iop_sw_mpu_rw_cpu_intr___intr0___width 1 193#define reg_iop_sw_mpu_rw_cpu_intr___intr0___bit 0 194#define reg_iop_sw_mpu_rw_cpu_intr___intr1___lsb 1 195#define reg_iop_sw_mpu_rw_cpu_intr___intr1___width 1 196#define reg_iop_sw_mpu_rw_cpu_intr___intr1___bit 1 197#define reg_iop_sw_mpu_rw_cpu_intr___intr2___lsb 2 198#define reg_iop_sw_mpu_rw_cpu_intr___intr2___width 1 199#define reg_iop_sw_mpu_rw_cpu_intr___intr2___bit 2 200#define reg_iop_sw_mpu_rw_cpu_intr___intr3___lsb 3 201#define reg_iop_sw_mpu_rw_cpu_intr___intr3___width 1 202#define reg_iop_sw_mpu_rw_cpu_intr___intr3___bit 3 203#define reg_iop_sw_mpu_rw_cpu_intr___intr4___lsb 4 204#define reg_iop_sw_mpu_rw_cpu_intr___intr4___width 1 205#define reg_iop_sw_mpu_rw_cpu_intr___intr4___bit 4 206#define reg_iop_sw_mpu_rw_cpu_intr___intr5___lsb 5 207#define reg_iop_sw_mpu_rw_cpu_intr___intr5___width 1 208#define reg_iop_sw_mpu_rw_cpu_intr___intr5___bit 5 209#define reg_iop_sw_mpu_rw_cpu_intr___intr6___lsb 6 210#define reg_iop_sw_mpu_rw_cpu_intr___intr6___width 1 211#define reg_iop_sw_mpu_rw_cpu_intr___intr6___bit 6 212#define reg_iop_sw_mpu_rw_cpu_intr___intr7___lsb 7 213#define reg_iop_sw_mpu_rw_cpu_intr___intr7___width 1 214#define reg_iop_sw_mpu_rw_cpu_intr___intr7___bit 7 215#define reg_iop_sw_mpu_rw_cpu_intr___intr8___lsb 8 216#define reg_iop_sw_mpu_rw_cpu_intr___intr8___width 1 217#define reg_iop_sw_mpu_rw_cpu_intr___intr8___bit 8 218#define reg_iop_sw_mpu_rw_cpu_intr___intr9___lsb 9 219#define reg_iop_sw_mpu_rw_cpu_intr___intr9___width 1 220#define reg_iop_sw_mpu_rw_cpu_intr___intr9___bit 9 221#define reg_iop_sw_mpu_rw_cpu_intr___intr10___lsb 10 222#define reg_iop_sw_mpu_rw_cpu_intr___intr10___width 1 223#define reg_iop_sw_mpu_rw_cpu_intr___intr10___bit 10 224#define reg_iop_sw_mpu_rw_cpu_intr___intr11___lsb 11 225#define reg_iop_sw_mpu_rw_cpu_intr___intr11___width 1 226#define reg_iop_sw_mpu_rw_cpu_intr___intr11___bit 11 227#define reg_iop_sw_mpu_rw_cpu_intr___intr12___lsb 12 228#define reg_iop_sw_mpu_rw_cpu_intr___intr12___width 1 229#define reg_iop_sw_mpu_rw_cpu_intr___intr12___bit 12 230#define reg_iop_sw_mpu_rw_cpu_intr___intr13___lsb 13 231#define reg_iop_sw_mpu_rw_cpu_intr___intr13___width 1 232#define reg_iop_sw_mpu_rw_cpu_intr___intr13___bit 13 233#define reg_iop_sw_mpu_rw_cpu_intr___intr14___lsb 14 234#define reg_iop_sw_mpu_rw_cpu_intr___intr14___width 1 235#define reg_iop_sw_mpu_rw_cpu_intr___intr14___bit 14 236#define reg_iop_sw_mpu_rw_cpu_intr___intr15___lsb 15 237#define reg_iop_sw_mpu_rw_cpu_intr___intr15___width 1 238#define reg_iop_sw_mpu_rw_cpu_intr___intr15___bit 15 239#define reg_iop_sw_mpu_rw_cpu_intr___intr16___lsb 16 240#define reg_iop_sw_mpu_rw_cpu_intr___intr16___width 1 241#define reg_iop_sw_mpu_rw_cpu_intr___intr16___bit 16 242#define reg_iop_sw_mpu_rw_cpu_intr___intr17___lsb 17 243#define reg_iop_sw_mpu_rw_cpu_intr___intr17___width 1 244#define reg_iop_sw_mpu_rw_cpu_intr___intr17___bit 17 245#define reg_iop_sw_mpu_rw_cpu_intr___intr18___lsb 18 246#define reg_iop_sw_mpu_rw_cpu_intr___intr18___width 1 247#define reg_iop_sw_mpu_rw_cpu_intr___intr18___bit 18 248#define reg_iop_sw_mpu_rw_cpu_intr___intr19___lsb 19 249#define reg_iop_sw_mpu_rw_cpu_intr___intr19___width 1 250#define reg_iop_sw_mpu_rw_cpu_intr___intr19___bit 19 251#define reg_iop_sw_mpu_rw_cpu_intr___intr20___lsb 20 252#define reg_iop_sw_mpu_rw_cpu_intr___intr20___width 1 253#define reg_iop_sw_mpu_rw_cpu_intr___intr20___bit 20 254#define reg_iop_sw_mpu_rw_cpu_intr___intr21___lsb 21 255#define reg_iop_sw_mpu_rw_cpu_intr___intr21___width 1 256#define reg_iop_sw_mpu_rw_cpu_intr___intr21___bit 21 257#define reg_iop_sw_mpu_rw_cpu_intr___intr22___lsb 22 258#define reg_iop_sw_mpu_rw_cpu_intr___intr22___width 1 259#define reg_iop_sw_mpu_rw_cpu_intr___intr22___bit 22 260#define reg_iop_sw_mpu_rw_cpu_intr___intr23___lsb 23 261#define reg_iop_sw_mpu_rw_cpu_intr___intr23___width 1 262#define reg_iop_sw_mpu_rw_cpu_intr___intr23___bit 23 263#define reg_iop_sw_mpu_rw_cpu_intr___intr24___lsb 24 264#define reg_iop_sw_mpu_rw_cpu_intr___intr24___width 1 265#define reg_iop_sw_mpu_rw_cpu_intr___intr24___bit 24 266#define reg_iop_sw_mpu_rw_cpu_intr___intr25___lsb 25 267#define reg_iop_sw_mpu_rw_cpu_intr___intr25___width 1 268#define reg_iop_sw_mpu_rw_cpu_intr___intr25___bit 25 269#define reg_iop_sw_mpu_rw_cpu_intr___intr26___lsb 26 270#define reg_iop_sw_mpu_rw_cpu_intr___intr26___width 1 271#define reg_iop_sw_mpu_rw_cpu_intr___intr26___bit 26 272#define reg_iop_sw_mpu_rw_cpu_intr___intr27___lsb 27 273#define reg_iop_sw_mpu_rw_cpu_intr___intr27___width 1 274#define reg_iop_sw_mpu_rw_cpu_intr___intr27___bit 27 275#define reg_iop_sw_mpu_rw_cpu_intr___intr28___lsb 28 276#define reg_iop_sw_mpu_rw_cpu_intr___intr28___width 1 277#define reg_iop_sw_mpu_rw_cpu_intr___intr28___bit 28 278#define reg_iop_sw_mpu_rw_cpu_intr___intr29___lsb 29 279#define reg_iop_sw_mpu_rw_cpu_intr___intr29___width 1 280#define reg_iop_sw_mpu_rw_cpu_intr___intr29___bit 29 281#define reg_iop_sw_mpu_rw_cpu_intr___intr30___lsb 30 282#define reg_iop_sw_mpu_rw_cpu_intr___intr30___width 1 283#define reg_iop_sw_mpu_rw_cpu_intr___intr30___bit 30 284#define reg_iop_sw_mpu_rw_cpu_intr___intr31___lsb 31 285#define reg_iop_sw_mpu_rw_cpu_intr___intr31___width 1 286#define reg_iop_sw_mpu_rw_cpu_intr___intr31___bit 31 287#define reg_iop_sw_mpu_rw_cpu_intr_offset 76 288 289/* Register r_cpu_intr, scope iop_sw_mpu, type r */ 290#define reg_iop_sw_mpu_r_cpu_intr___intr0___lsb 0 291#define reg_iop_sw_mpu_r_cpu_intr___intr0___width 1 292#define reg_iop_sw_mpu_r_cpu_intr___intr0___bit 0 293#define reg_iop_sw_mpu_r_cpu_intr___intr1___lsb 1 294#define reg_iop_sw_mpu_r_cpu_intr___intr1___width 1 295#define reg_iop_sw_mpu_r_cpu_intr___intr1___bit 1 296#define reg_iop_sw_mpu_r_cpu_intr___intr2___lsb 2 297#define reg_iop_sw_mpu_r_cpu_intr___intr2___width 1 298#define reg_iop_sw_mpu_r_cpu_intr___intr2___bit 2 299#define reg_iop_sw_mpu_r_cpu_intr___intr3___lsb 3 300#define reg_iop_sw_mpu_r_cpu_intr___intr3___width 1 301#define reg_iop_sw_mpu_r_cpu_intr___intr3___bit 3 302#define reg_iop_sw_mpu_r_cpu_intr___intr4___lsb 4 303#define reg_iop_sw_mpu_r_cpu_intr___intr4___width 1 304#define reg_iop_sw_mpu_r_cpu_intr___intr4___bit 4 305#define reg_iop_sw_mpu_r_cpu_intr___intr5___lsb 5 306#define reg_iop_sw_mpu_r_cpu_intr___intr5___width 1 307#define reg_iop_sw_mpu_r_cpu_intr___intr5___bit 5 308#define reg_iop_sw_mpu_r_cpu_intr___intr6___lsb 6 309#define reg_iop_sw_mpu_r_cpu_intr___intr6___width 1 310#define reg_iop_sw_mpu_r_cpu_intr___intr6___bit 6 311#define reg_iop_sw_mpu_r_cpu_intr___intr7___lsb 7 312#define reg_iop_sw_mpu_r_cpu_intr___intr7___width 1 313#define reg_iop_sw_mpu_r_cpu_intr___intr7___bit 7 314#define reg_iop_sw_mpu_r_cpu_intr___intr8___lsb 8 315#define reg_iop_sw_mpu_r_cpu_intr___intr8___width 1 316#define reg_iop_sw_mpu_r_cpu_intr___intr8___bit 8 317#define reg_iop_sw_mpu_r_cpu_intr___intr9___lsb 9 318#define reg_iop_sw_mpu_r_cpu_intr___intr9___width 1 319#define reg_iop_sw_mpu_r_cpu_intr___intr9___bit 9 320#define reg_iop_sw_mpu_r_cpu_intr___intr10___lsb 10 321#define reg_iop_sw_mpu_r_cpu_intr___intr10___width 1 322#define reg_iop_sw_mpu_r_cpu_intr___intr10___bit 10 323#define reg_iop_sw_mpu_r_cpu_intr___intr11___lsb 11 324#define reg_iop_sw_mpu_r_cpu_intr___intr11___width 1 325#define reg_iop_sw_mpu_r_cpu_intr___intr11___bit 11 326#define reg_iop_sw_mpu_r_cpu_intr___intr12___lsb 12 327#define reg_iop_sw_mpu_r_cpu_intr___intr12___width 1 328#define reg_iop_sw_mpu_r_cpu_intr___intr12___bit 12 329#define reg_iop_sw_mpu_r_cpu_intr___intr13___lsb 13 330#define reg_iop_sw_mpu_r_cpu_intr___intr13___width 1 331#define reg_iop_sw_mpu_r_cpu_intr___intr13___bit 13 332#define reg_iop_sw_mpu_r_cpu_intr___intr14___lsb 14 333#define reg_iop_sw_mpu_r_cpu_intr___intr14___width 1 334#define reg_iop_sw_mpu_r_cpu_intr___intr14___bit 14 335#define reg_iop_sw_mpu_r_cpu_intr___intr15___lsb 15 336#define reg_iop_sw_mpu_r_cpu_intr___intr15___width 1 337#define reg_iop_sw_mpu_r_cpu_intr___intr15___bit 15 338#define reg_iop_sw_mpu_r_cpu_intr___intr16___lsb 16 339#define reg_iop_sw_mpu_r_cpu_intr___intr16___width 1 340#define reg_iop_sw_mpu_r_cpu_intr___intr16___bit 16 341#define reg_iop_sw_mpu_r_cpu_intr___intr17___lsb 17 342#define reg_iop_sw_mpu_r_cpu_intr___intr17___width 1 343#define reg_iop_sw_mpu_r_cpu_intr___intr17___bit 17 344#define reg_iop_sw_mpu_r_cpu_intr___intr18___lsb 18 345#define reg_iop_sw_mpu_r_cpu_intr___intr18___width 1 346#define reg_iop_sw_mpu_r_cpu_intr___intr18___bit 18 347#define reg_iop_sw_mpu_r_cpu_intr___intr19___lsb 19 348#define reg_iop_sw_mpu_r_cpu_intr___intr19___width 1 349#define reg_iop_sw_mpu_r_cpu_intr___intr19___bit 19 350#define reg_iop_sw_mpu_r_cpu_intr___intr20___lsb 20 351#define reg_iop_sw_mpu_r_cpu_intr___intr20___width 1 352#define reg_iop_sw_mpu_r_cpu_intr___intr20___bit 20 353#define reg_iop_sw_mpu_r_cpu_intr___intr21___lsb 21 354#define reg_iop_sw_mpu_r_cpu_intr___intr21___width 1 355#define reg_iop_sw_mpu_r_cpu_intr___intr21___bit 21 356#define reg_iop_sw_mpu_r_cpu_intr___intr22___lsb 22 357#define reg_iop_sw_mpu_r_cpu_intr___intr22___width 1 358#define reg_iop_sw_mpu_r_cpu_intr___intr22___bit 22 359#define reg_iop_sw_mpu_r_cpu_intr___intr23___lsb 23 360#define reg_iop_sw_mpu_r_cpu_intr___intr23___width 1 361#define reg_iop_sw_mpu_r_cpu_intr___intr23___bit 23 362#define reg_iop_sw_mpu_r_cpu_intr___intr24___lsb 24 363#define reg_iop_sw_mpu_r_cpu_intr___intr24___width 1 364#define reg_iop_sw_mpu_r_cpu_intr___intr24___bit 24 365#define reg_iop_sw_mpu_r_cpu_intr___intr25___lsb 25 366#define reg_iop_sw_mpu_r_cpu_intr___intr25___width 1 367#define reg_iop_sw_mpu_r_cpu_intr___intr25___bit 25 368#define reg_iop_sw_mpu_r_cpu_intr___intr26___lsb 26 369#define reg_iop_sw_mpu_r_cpu_intr___intr26___width 1 370#define reg_iop_sw_mpu_r_cpu_intr___intr26___bit 26 371#define reg_iop_sw_mpu_r_cpu_intr___intr27___lsb 27 372#define reg_iop_sw_mpu_r_cpu_intr___intr27___width 1 373#define reg_iop_sw_mpu_r_cpu_intr___intr27___bit 27 374#define reg_iop_sw_mpu_r_cpu_intr___intr28___lsb 28 375#define reg_iop_sw_mpu_r_cpu_intr___intr28___width 1 376#define reg_iop_sw_mpu_r_cpu_intr___intr28___bit 28 377#define reg_iop_sw_mpu_r_cpu_intr___intr29___lsb 29 378#define reg_iop_sw_mpu_r_cpu_intr___intr29___width 1 379#define reg_iop_sw_mpu_r_cpu_intr___intr29___bit 29 380#define reg_iop_sw_mpu_r_cpu_intr___intr30___lsb 30 381#define reg_iop_sw_mpu_r_cpu_intr___intr30___width 1 382#define reg_iop_sw_mpu_r_cpu_intr___intr30___bit 30 383#define reg_iop_sw_mpu_r_cpu_intr___intr31___lsb 31 384#define reg_iop_sw_mpu_r_cpu_intr___intr31___width 1 385#define reg_iop_sw_mpu_r_cpu_intr___intr31___bit 31 386#define reg_iop_sw_mpu_r_cpu_intr_offset 80 387 388/* Register rw_intr_grp0_mask, scope iop_sw_mpu, type rw */ 389#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu_intr0___lsb 0 390#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu_intr0___width 1 391#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu_intr0___bit 0 392#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp0___lsb 1 393#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp0___width 1 394#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp0___bit 1 395#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp0___lsb 2 396#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp0___width 1 397#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp0___bit 2 398#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out___lsb 3 399#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out___width 1 400#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out___bit 3 401#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu_intr1___lsb 4 402#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu_intr1___width 1 403#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu_intr1___bit 4 404#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp1___lsb 5 405#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp1___width 1 406#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp1___bit 5 407#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp1___lsb 6 408#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp1___width 1 409#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp1___bit 6 410#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in___lsb 7 411#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in___width 1 412#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in___bit 7 413#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu_intr2___lsb 8 414#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu_intr2___width 1 415#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu_intr2___bit 8 416#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp2___lsb 9 417#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp2___width 1 418#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp2___bit 9 419#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out_extra___lsb 10 420#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out_extra___width 1 421#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out_extra___bit 10 422#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_out___lsb 11 423#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_out___width 1 424#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_out___bit 11 425#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu_intr3___lsb 12 426#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu_intr3___width 1 427#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu_intr3___bit 12 428#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp3___lsb 13 429#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp3___width 1 430#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp3___bit 13 431#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in_extra___lsb 14 432#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in_extra___width 1 433#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in_extra___bit 14 434#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_in___lsb 15 435#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_in___width 1 436#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_in___bit 15 437#define reg_iop_sw_mpu_rw_intr_grp0_mask_offset 84 438 439/* Register rw_ack_intr_grp0, scope iop_sw_mpu, type rw */ 440#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu_intr0___lsb 0 441#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu_intr0___width 1 442#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu_intr0___bit 0 443#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu_intr1___lsb 4 444#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu_intr1___width 1 445#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu_intr1___bit 4 446#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu_intr2___lsb 8 447#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu_intr2___width 1 448#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu_intr2___bit 8 449#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu_intr3___lsb 12 450#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu_intr3___width 1 451#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu_intr3___bit 12 452#define reg_iop_sw_mpu_rw_ack_intr_grp0_offset 88 453 454/* Register r_intr_grp0, scope iop_sw_mpu, type r */ 455#define reg_iop_sw_mpu_r_intr_grp0___spu_intr0___lsb 0 456#define reg_iop_sw_mpu_r_intr_grp0___spu_intr0___width 1 457#define reg_iop_sw_mpu_r_intr_grp0___spu_intr0___bit 0 458#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp0___lsb 1 459#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp0___width 1 460#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp0___bit 1 461#define reg_iop_sw_mpu_r_intr_grp0___timer_grp0___lsb 2 462#define reg_iop_sw_mpu_r_intr_grp0___timer_grp0___width 1 463#define reg_iop_sw_mpu_r_intr_grp0___timer_grp0___bit 2 464#define reg_iop_sw_mpu_r_intr_grp0___fifo_out___lsb 3 465#define reg_iop_sw_mpu_r_intr_grp0___fifo_out___width 1 466#define reg_iop_sw_mpu_r_intr_grp0___fifo_out___bit 3 467#define reg_iop_sw_mpu_r_intr_grp0___spu_intr1___lsb 4 468#define reg_iop_sw_mpu_r_intr_grp0___spu_intr1___width 1 469#define reg_iop_sw_mpu_r_intr_grp0___spu_intr1___bit 4 470#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp1___lsb 5 471#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp1___width 1 472#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp1___bit 5 473#define reg_iop_sw_mpu_r_intr_grp0___timer_grp1___lsb 6 474#define reg_iop_sw_mpu_r_intr_grp0___timer_grp1___width 1 475#define reg_iop_sw_mpu_r_intr_grp0___timer_grp1___bit 6 476#define reg_iop_sw_mpu_r_intr_grp0___fifo_in___lsb 7 477#define reg_iop_sw_mpu_r_intr_grp0___fifo_in___width 1 478#define reg_iop_sw_mpu_r_intr_grp0___fifo_in___bit 7 479#define reg_iop_sw_mpu_r_intr_grp0___spu_intr2___lsb 8 480#define reg_iop_sw_mpu_r_intr_grp0___spu_intr2___width 1 481#define reg_iop_sw_mpu_r_intr_grp0___spu_intr2___bit 8 482#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp2___lsb 9 483#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp2___width 1 484#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp2___bit 9 485#define reg_iop_sw_mpu_r_intr_grp0___fifo_out_extra___lsb 10 486#define reg_iop_sw_mpu_r_intr_grp0___fifo_out_extra___width 1 487#define reg_iop_sw_mpu_r_intr_grp0___fifo_out_extra___bit 10 488#define reg_iop_sw_mpu_r_intr_grp0___dmc_out___lsb 11 489#define reg_iop_sw_mpu_r_intr_grp0___dmc_out___width 1 490#define reg_iop_sw_mpu_r_intr_grp0___dmc_out___bit 11 491#define reg_iop_sw_mpu_r_intr_grp0___spu_intr3___lsb 12 492#define reg_iop_sw_mpu_r_intr_grp0___spu_intr3___width 1 493#define reg_iop_sw_mpu_r_intr_grp0___spu_intr3___bit 12 494#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp3___lsb 13 495#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp3___width 1 496#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp3___bit 13 497#define reg_iop_sw_mpu_r_intr_grp0___fifo_in_extra___lsb 14 498#define reg_iop_sw_mpu_r_intr_grp0___fifo_in_extra___width 1 499#define reg_iop_sw_mpu_r_intr_grp0___fifo_in_extra___bit 14 500#define reg_iop_sw_mpu_r_intr_grp0___dmc_in___lsb 15 501#define reg_iop_sw_mpu_r_intr_grp0___dmc_in___width 1 502#define reg_iop_sw_mpu_r_intr_grp0___dmc_in___bit 15 503#define reg_iop_sw_mpu_r_intr_grp0_offset 92 504 505/* Register r_masked_intr_grp0, scope iop_sw_mpu, type r */ 506#define reg_iop_sw_mpu_r_masked_intr_grp0___spu_intr0___lsb 0 507#define reg_iop_sw_mpu_r_masked_intr_grp0___spu_intr0___width 1 508#define reg_iop_sw_mpu_r_masked_intr_grp0___spu_intr0___bit 0 509#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp0___lsb 1 510#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp0___width 1 511#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp0___bit 1 512#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp0___lsb 2 513#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp0___width 1 514#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp0___bit 2 515#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out___lsb 3 516#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out___width 1 517#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out___bit 3 518#define reg_iop_sw_mpu_r_masked_intr_grp0___spu_intr1___lsb 4 519#define reg_iop_sw_mpu_r_masked_intr_grp0___spu_intr1___width 1 520#define reg_iop_sw_mpu_r_masked_intr_grp0___spu_intr1___bit 4 521#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp1___lsb 5 522#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp1___width 1 523#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp1___bit 5 524#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp1___lsb 6 525#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp1___width 1 526#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp1___bit 6 527#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in___lsb 7 528#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in___width 1 529#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in___bit 7 530#define reg_iop_sw_mpu_r_masked_intr_grp0___spu_intr2___lsb 8 531#define reg_iop_sw_mpu_r_masked_intr_grp0___spu_intr2___width 1 532#define reg_iop_sw_mpu_r_masked_intr_grp0___spu_intr2___bit 8 533#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp2___lsb 9 534#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp2___width 1 535#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp2___bit 9 536#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out_extra___lsb 10 537#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out_extra___width 1 538#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out_extra___bit 10 539#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_out___lsb 11 540#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_out___width 1 541#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_out___bit 11 542#define reg_iop_sw_mpu_r_masked_intr_grp0___spu_intr3___lsb 12 543#define reg_iop_sw_mpu_r_masked_intr_grp0___spu_intr3___width 1 544#define reg_iop_sw_mpu_r_masked_intr_grp0___spu_intr3___bit 12 545#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp3___lsb 13 546#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp3___width 1 547#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp3___bit 13 548#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in_extra___lsb 14 549#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in_extra___width 1 550#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in_extra___bit 14 551#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_in___lsb 15 552#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_in___width 1 553#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_in___bit 15 554#define reg_iop_sw_mpu_r_masked_intr_grp0_offset 96 555 556/* Register rw_intr_grp1_mask, scope iop_sw_mpu, type rw */ 557#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu_intr4___lsb 0 558#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu_intr4___width 1 559#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu_intr4___bit 0 560#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp4___lsb 1 561#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp4___width 1 562#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp4___bit 1 563#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out_extra___lsb 2 564#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out_extra___width 1 565#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out_extra___bit 2 566#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_out___lsb 3 567#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_out___width 1 568#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_out___bit 3 569#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu_intr5___lsb 4 570#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu_intr5___width 1 571#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu_intr5___bit 4 572#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp5___lsb 5 573#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp5___width 1 574#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp5___bit 5 575#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in_extra___lsb 6 576#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in_extra___width 1 577#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in_extra___bit 6 578#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_in___lsb 7 579#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_in___width 1 580#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_in___bit 7 581#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu_intr6___lsb 8 582#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu_intr6___width 1 583#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu_intr6___bit 8 584#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp6___lsb 9 585#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp6___width 1 586#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp6___bit 9 587#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp0___lsb 10 588#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp0___width 1 589#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp0___bit 10 590#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out___lsb 11 591#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out___width 1 592#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out___bit 11 593#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu_intr7___lsb 12 594#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu_intr7___width 1 595#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu_intr7___bit 12 596#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp7___lsb 13 597#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp7___width 1 598#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp7___bit 13 599#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp1___lsb 14 600#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp1___width 1 601#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp1___bit 14 602#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in___lsb 15 603#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in___width 1 604#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in___bit 15 605#define reg_iop_sw_mpu_rw_intr_grp1_mask_offset 100 606 607/* Register rw_ack_intr_grp1, scope iop_sw_mpu, type rw */ 608#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu_intr4___lsb 0 609#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu_intr4___width 1 610#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu_intr4___bit 0 611#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu_intr5___lsb 4 612#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu_intr5___width 1 613#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu_intr5___bit 4 614#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu_intr6___lsb 8 615#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu_intr6___width 1 616#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu_intr6___bit 8 617#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu_intr7___lsb 12 618#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu_intr7___width 1 619#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu_intr7___bit 12 620#define reg_iop_sw_mpu_rw_ack_intr_grp1_offset 104 621 622/* Register r_intr_grp1, scope iop_sw_mpu, type r */ 623#define reg_iop_sw_mpu_r_intr_grp1___spu_intr4___lsb 0 624#define reg_iop_sw_mpu_r_intr_grp1___spu_intr4___width 1 625#define reg_iop_sw_mpu_r_intr_grp1___spu_intr4___bit 0 626#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp4___lsb 1 627#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp4___width 1 628#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp4___bit 1 629#define reg_iop_sw_mpu_r_intr_grp1___fifo_out_extra___lsb 2 630#define reg_iop_sw_mpu_r_intr_grp1___fifo_out_extra___width 1 631#define reg_iop_sw_mpu_r_intr_grp1___fifo_out_extra___bit 2 632#define reg_iop_sw_mpu_r_intr_grp1___dmc_out___lsb 3 633#define reg_iop_sw_mpu_r_intr_grp1___dmc_out___width 1 634#define reg_iop_sw_mpu_r_intr_grp1___dmc_out___bit 3 635#define reg_iop_sw_mpu_r_intr_grp1___spu_intr5___lsb 4 636#define reg_iop_sw_mpu_r_intr_grp1___spu_intr5___width 1 637#define reg_iop_sw_mpu_r_intr_grp1___spu_intr5___bit 4 638#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp5___lsb 5 639#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp5___width 1 640#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp5___bit 5 641#define reg_iop_sw_mpu_r_intr_grp1___fifo_in_extra___lsb 6 642#define reg_iop_sw_mpu_r_intr_grp1___fifo_in_extra___width 1 643#define reg_iop_sw_mpu_r_intr_grp1___fifo_in_extra___bit 6 644#define reg_iop_sw_mpu_r_intr_grp1___dmc_in___lsb 7 645#define reg_iop_sw_mpu_r_intr_grp1___dmc_in___width 1 646#define reg_iop_sw_mpu_r_intr_grp1___dmc_in___bit 7 647#define reg_iop_sw_mpu_r_intr_grp1___spu_intr6___lsb 8 648#define reg_iop_sw_mpu_r_intr_grp1___spu_intr6___width 1 649#define reg_iop_sw_mpu_r_intr_grp1___spu_intr6___bit 8 650#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp6___lsb 9 651#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp6___width 1 652#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp6___bit 9 653#define reg_iop_sw_mpu_r_intr_grp1___timer_grp0___lsb 10 654#define reg_iop_sw_mpu_r_intr_grp1___timer_grp0___width 1 655#define reg_iop_sw_mpu_r_intr_grp1___timer_grp0___bit 10 656#define reg_iop_sw_mpu_r_intr_grp1___fifo_out___lsb 11 657#define reg_iop_sw_mpu_r_intr_grp1___fifo_out___width 1 658#define reg_iop_sw_mpu_r_intr_grp1___fifo_out___bit 11 659#define reg_iop_sw_mpu_r_intr_grp1___spu_intr7___lsb 12 660#define reg_iop_sw_mpu_r_intr_grp1___spu_intr7___width 1 661#define reg_iop_sw_mpu_r_intr_grp1___spu_intr7___bit 12 662#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp7___lsb 13 663#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp7___width 1 664#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp7___bit 13 665#define reg_iop_sw_mpu_r_intr_grp1___timer_grp1___lsb 14 666#define reg_iop_sw_mpu_r_intr_grp1___timer_grp1___width 1 667#define reg_iop_sw_mpu_r_intr_grp1___timer_grp1___bit 14 668#define reg_iop_sw_mpu_r_intr_grp1___fifo_in___lsb 15 669#define reg_iop_sw_mpu_r_intr_grp1___fifo_in___width 1 670#define reg_iop_sw_mpu_r_intr_grp1___fifo_in___bit 15 671#define reg_iop_sw_mpu_r_intr_grp1_offset 108 672 673/* Register r_masked_intr_grp1, scope iop_sw_mpu, type r */ 674#define reg_iop_sw_mpu_r_masked_intr_grp1___spu_intr4___lsb 0 675#define reg_iop_sw_mpu_r_masked_intr_grp1___spu_intr4___width 1 676#define reg_iop_sw_mpu_r_masked_intr_grp1___spu_intr4___bit 0 677#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp4___lsb 1 678#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp4___width 1 679#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp4___bit 1 680#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out_extra___lsb 2 681#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out_extra___width 1 682#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out_extra___bit 2 683#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_out___lsb 3 684#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_out___width 1 685#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_out___bit 3 686#define reg_iop_sw_mpu_r_masked_intr_grp1___spu_intr5___lsb 4 687#define reg_iop_sw_mpu_r_masked_intr_grp1___spu_intr5___width 1 688#define reg_iop_sw_mpu_r_masked_intr_grp1___spu_intr5___bit 4 689#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp5___lsb 5 690#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp5___width 1 691#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp5___bit 5 692#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in_extra___lsb 6 693#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in_extra___width 1 694#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in_extra___bit 6 695#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_in___lsb 7 696#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_in___width 1 697#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_in___bit 7 698#define reg_iop_sw_mpu_r_masked_intr_grp1___spu_intr6___lsb 8 699#define reg_iop_sw_mpu_r_masked_intr_grp1___spu_intr6___width 1 700#define reg_iop_sw_mpu_r_masked_intr_grp1___spu_intr6___bit 8 701#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp6___lsb 9 702#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp6___width 1 703#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp6___bit 9 704#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp0___lsb 10 705#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp0___width 1 706#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp0___bit 10 707#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out___lsb 11 708#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out___width 1 709#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out___bit 11 710#define reg_iop_sw_mpu_r_masked_intr_grp1___spu_intr7___lsb 12 711#define reg_iop_sw_mpu_r_masked_intr_grp1___spu_intr7___width 1 712#define reg_iop_sw_mpu_r_masked_intr_grp1___spu_intr7___bit 12 713#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp7___lsb 13 714#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp7___width 1 715#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp7___bit 13 716#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp1___lsb 14 717#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp1___width 1 718#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp1___bit 14 719#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in___lsb 15 720#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in___width 1 721#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in___bit 15 722#define reg_iop_sw_mpu_r_masked_intr_grp1_offset 112 723 724/* Register rw_intr_grp2_mask, scope iop_sw_mpu, type rw */ 725#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu_intr8___lsb 0 726#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu_intr8___width 1 727#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu_intr8___bit 0 728#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp0___lsb 1 729#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp0___width 1 730#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp0___bit 1 731#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp0___lsb 2 732#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp0___width 1 733#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp0___bit 2 734#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out___lsb 3 735#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out___width 1 736#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out___bit 3 737#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu_intr9___lsb 4 738#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu_intr9___width 1 739#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu_intr9___bit 4 740#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp1___lsb 5 741#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp1___width 1 742#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp1___bit 5 743#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp1___lsb 6 744#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp1___width 1 745#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp1___bit 6 746#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in___lsb 7 747#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in___width 1 748#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in___bit 7 749#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu_intr10___lsb 8 750#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu_intr10___width 1 751#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu_intr10___bit 8 752#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp2___lsb 9 753#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp2___width 1 754#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp2___bit 9 755#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out_extra___lsb 10 756#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out_extra___width 1 757#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out_extra___bit 10 758#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_out___lsb 11 759#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_out___width 1 760#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_out___bit 11 761#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu_intr11___lsb 12 762#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu_intr11___width 1 763#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu_intr11___bit 12 764#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp3___lsb 13 765#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp3___width 1 766#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp3___bit 13 767#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in_extra___lsb 14 768#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in_extra___width 1 769#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in_extra___bit 14 770#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_in___lsb 15 771#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_in___width 1 772#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_in___bit 15 773#define reg_iop_sw_mpu_rw_intr_grp2_mask_offset 116 774 775/* Register rw_ack_intr_grp2, scope iop_sw_mpu, type rw */ 776#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu_intr8___lsb 0 777#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu_intr8___width 1 778#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu_intr8___bit 0 779#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu_intr9___lsb 4 780#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu_intr9___width 1 781#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu_intr9___bit 4 782#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu_intr10___lsb 8 783#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu_intr10___width 1 784#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu_intr10___bit 8 785#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu_intr11___lsb 12 786#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu_intr11___width 1 787#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu_intr11___bit 12 788#define reg_iop_sw_mpu_rw_ack_intr_grp2_offset 120 789 790/* Register r_intr_grp2, scope iop_sw_mpu, type r */ 791#define reg_iop_sw_mpu_r_intr_grp2___spu_intr8___lsb 0 792#define reg_iop_sw_mpu_r_intr_grp2___spu_intr8___width 1 793#define reg_iop_sw_mpu_r_intr_grp2___spu_intr8___bit 0 794#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp0___lsb 1 795#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp0___width 1 796#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp0___bit 1 797#define reg_iop_sw_mpu_r_intr_grp2___timer_grp0___lsb 2 798#define reg_iop_sw_mpu_r_intr_grp2___timer_grp0___width 1 799#define reg_iop_sw_mpu_r_intr_grp2___timer_grp0___bit 2 800#define reg_iop_sw_mpu_r_intr_grp2___fifo_out___lsb 3 801#define reg_iop_sw_mpu_r_intr_grp2___fifo_out___width 1 802#define reg_iop_sw_mpu_r_intr_grp2___fifo_out___bit 3 803#define reg_iop_sw_mpu_r_intr_grp2___spu_intr9___lsb 4 804#define reg_iop_sw_mpu_r_intr_grp2___spu_intr9___width 1 805#define reg_iop_sw_mpu_r_intr_grp2___spu_intr9___bit 4 806#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp1___lsb 5 807#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp1___width 1 808#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp1___bit 5 809#define reg_iop_sw_mpu_r_intr_grp2___timer_grp1___lsb 6 810#define reg_iop_sw_mpu_r_intr_grp2___timer_grp1___width 1 811#define reg_iop_sw_mpu_r_intr_grp2___timer_grp1___bit 6 812#define reg_iop_sw_mpu_r_intr_grp2___fifo_in___lsb 7 813#define reg_iop_sw_mpu_r_intr_grp2___fifo_in___width 1 814#define reg_iop_sw_mpu_r_intr_grp2___fifo_in___bit 7 815#define reg_iop_sw_mpu_r_intr_grp2___spu_intr10___lsb 8 816#define reg_iop_sw_mpu_r_intr_grp2___spu_intr10___width 1 817#define reg_iop_sw_mpu_r_intr_grp2___spu_intr10___bit 8 818#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp2___lsb 9 819#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp2___width 1 820#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp2___bit 9 821#define reg_iop_sw_mpu_r_intr_grp2___fifo_out_extra___lsb 10 822#define reg_iop_sw_mpu_r_intr_grp2___fifo_out_extra___width 1 823#define reg_iop_sw_mpu_r_intr_grp2___fifo_out_extra___bit 10 824#define reg_iop_sw_mpu_r_intr_grp2___dmc_out___lsb 11 825#define reg_iop_sw_mpu_r_intr_grp2___dmc_out___width 1 826#define reg_iop_sw_mpu_r_intr_grp2___dmc_out___bit 11 827#define reg_iop_sw_mpu_r_intr_grp2___spu_intr11___lsb 12 828#define reg_iop_sw_mpu_r_intr_grp2___spu_intr11___width 1 829#define reg_iop_sw_mpu_r_intr_grp2___spu_intr11___bit 12 830#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp3___lsb 13 831#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp3___width 1 832#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp3___bit 13 833#define reg_iop_sw_mpu_r_intr_grp2___fifo_in_extra___lsb 14 834#define reg_iop_sw_mpu_r_intr_grp2___fifo_in_extra___width 1 835#define reg_iop_sw_mpu_r_intr_grp2___fifo_in_extra___bit 14 836#define reg_iop_sw_mpu_r_intr_grp2___dmc_in___lsb 15 837#define reg_iop_sw_mpu_r_intr_grp2___dmc_in___width 1 838#define reg_iop_sw_mpu_r_intr_grp2___dmc_in___bit 15 839#define reg_iop_sw_mpu_r_intr_grp2_offset 124 840 841/* Register r_masked_intr_grp2, scope iop_sw_mpu, type r */ 842#define reg_iop_sw_mpu_r_masked_intr_grp2___spu_intr8___lsb 0 843#define reg_iop_sw_mpu_r_masked_intr_grp2___spu_intr8___width 1 844#define reg_iop_sw_mpu_r_masked_intr_grp2___spu_intr8___bit 0 845#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp0___lsb 1 846#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp0___width 1 847#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp0___bit 1 848#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp0___lsb 2 849#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp0___width 1 850#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp0___bit 2 851#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out___lsb 3 852#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out___width 1 853#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out___bit 3 854#define reg_iop_sw_mpu_r_masked_intr_grp2___spu_intr9___lsb 4 855#define reg_iop_sw_mpu_r_masked_intr_grp2___spu_intr9___width 1 856#define reg_iop_sw_mpu_r_masked_intr_grp2___spu_intr9___bit 4 857#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp1___lsb 5 858#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp1___width 1 859#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp1___bit 5 860#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp1___lsb 6 861#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp1___width 1 862#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp1___bit 6 863#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in___lsb 7 864#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in___width 1 865#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in___bit 7 866#define reg_iop_sw_mpu_r_masked_intr_grp2___spu_intr10___lsb 8 867#define reg_iop_sw_mpu_r_masked_intr_grp2___spu_intr10___width 1 868#define reg_iop_sw_mpu_r_masked_intr_grp2___spu_intr10___bit 8 869#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp2___lsb 9 870#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp2___width 1 871#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp2___bit 9 872#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out_extra___lsb 10 873#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out_extra___width 1 874#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out_extra___bit 10 875#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_out___lsb 11 876#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_out___width 1 877#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_out___bit 11 878#define reg_iop_sw_mpu_r_masked_intr_grp2___spu_intr11___lsb 12 879#define reg_iop_sw_mpu_r_masked_intr_grp2___spu_intr11___width 1 880#define reg_iop_sw_mpu_r_masked_intr_grp2___spu_intr11___bit 12 881#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp3___lsb 13 882#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp3___width 1 883#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp3___bit 13 884#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in_extra___lsb 14 885#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in_extra___width 1 886#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in_extra___bit 14 887#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_in___lsb 15 888#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_in___width 1 889#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_in___bit 15 890#define reg_iop_sw_mpu_r_masked_intr_grp2_offset 128 891 892/* Register rw_intr_grp3_mask, scope iop_sw_mpu, type rw */ 893#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu_intr12___lsb 0 894#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu_intr12___width 1 895#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu_intr12___bit 0 896#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp4___lsb 1 897#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp4___width 1 898#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp4___bit 1 899#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out_extra___lsb 2 900#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out_extra___width 1 901#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out_extra___bit 2 902#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_out___lsb 3 903#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_out___width 1 904#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_out___bit 3 905#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu_intr13___lsb 4 906#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu_intr13___width 1 907#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu_intr13___bit 4 908#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp5___lsb 5 909#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp5___width 1 910#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp5___bit 5 911#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in_extra___lsb 6 912#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in_extra___width 1 913#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in_extra___bit 6 914#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_in___lsb 7 915#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_in___width 1 916#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_in___bit 7 917#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu_intr14___lsb 8 918#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu_intr14___width 1 919#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu_intr14___bit 8 920#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp6___lsb 9 921#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp6___width 1 922#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp6___bit 9 923#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp0___lsb 10 924#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp0___width 1 925#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp0___bit 10 926#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out___lsb 11 927#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out___width 1 928#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out___bit 11 929#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu_intr15___lsb 12 930#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu_intr15___width 1 931#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu_intr15___bit 12 932#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp7___lsb 13 933#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp7___width 1 934#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp7___bit 13 935#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp1___lsb 14 936#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp1___width 1 937#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp1___bit 14 938#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in___lsb 15 939#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in___width 1 940#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in___bit 15 941#define reg_iop_sw_mpu_rw_intr_grp3_mask_offset 132 942 943/* Register rw_ack_intr_grp3, scope iop_sw_mpu, type rw */ 944#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu_intr12___lsb 0 945#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu_intr12___width 1 946#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu_intr12___bit 0 947#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu_intr13___lsb 4 948#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu_intr13___width 1 949#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu_intr13___bit 4 950#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu_intr14___lsb 8 951#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu_intr14___width 1 952#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu_intr14___bit 8 953#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu_intr15___lsb 12 954#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu_intr15___width 1 955#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu_intr15___bit 12 956#define reg_iop_sw_mpu_rw_ack_intr_grp3_offset 136 957 958/* Register r_intr_grp3, scope iop_sw_mpu, type r */ 959#define reg_iop_sw_mpu_r_intr_grp3___spu_intr12___lsb 0 960#define reg_iop_sw_mpu_r_intr_grp3___spu_intr12___width 1 961#define reg_iop_sw_mpu_r_intr_grp3___spu_intr12___bit 0 962#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp4___lsb 1 963#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp4___width 1 964#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp4___bit 1 965#define reg_iop_sw_mpu_r_intr_grp3___fifo_out_extra___lsb 2 966#define reg_iop_sw_mpu_r_intr_grp3___fifo_out_extra___width 1 967#define reg_iop_sw_mpu_r_intr_grp3___fifo_out_extra___bit 2 968#define reg_iop_sw_mpu_r_intr_grp3___dmc_out___lsb 3 969#define reg_iop_sw_mpu_r_intr_grp3___dmc_out___width 1 970#define reg_iop_sw_mpu_r_intr_grp3___dmc_out___bit 3 971#define reg_iop_sw_mpu_r_intr_grp3___spu_intr13___lsb 4 972#define reg_iop_sw_mpu_r_intr_grp3___spu_intr13___width 1 973#define reg_iop_sw_mpu_r_intr_grp3___spu_intr13___bit 4 974#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp5___lsb 5 975#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp5___width 1 976#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp5___bit 5 977#define reg_iop_sw_mpu_r_intr_grp3___fifo_in_extra___lsb 6 978#define reg_iop_sw_mpu_r_intr_grp3___fifo_in_extra___width 1 979#define reg_iop_sw_mpu_r_intr_grp3___fifo_in_extra___bit 6 980#define reg_iop_sw_mpu_r_intr_grp3___dmc_in___lsb 7 981#define reg_iop_sw_mpu_r_intr_grp3___dmc_in___width 1 982#define reg_iop_sw_mpu_r_intr_grp3___dmc_in___bit 7 983#define reg_iop_sw_mpu_r_intr_grp3___spu_intr14___lsb 8 984#define reg_iop_sw_mpu_r_intr_grp3___spu_intr14___width 1 985#define reg_iop_sw_mpu_r_intr_grp3___spu_intr14___bit 8 986#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp6___lsb 9 987#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp6___width 1 988#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp6___bit 9 989#define reg_iop_sw_mpu_r_intr_grp3___timer_grp0___lsb 10 990#define reg_iop_sw_mpu_r_intr_grp3___timer_grp0___width 1 991#define reg_iop_sw_mpu_r_intr_grp3___timer_grp0___bit 10 992#define reg_iop_sw_mpu_r_intr_grp3___fifo_out___lsb 11 993#define reg_iop_sw_mpu_r_intr_grp3___fifo_out___width 1 994#define reg_iop_sw_mpu_r_intr_grp3___fifo_out___bit 11 995#define reg_iop_sw_mpu_r_intr_grp3___spu_intr15___lsb 12 996#define reg_iop_sw_mpu_r_intr_grp3___spu_intr15___width 1 997#define reg_iop_sw_mpu_r_intr_grp3___spu_intr15___bit 12 998#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp7___lsb 13 999#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp7___width 1 1000#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp7___bit 13 1001#define reg_iop_sw_mpu_r_intr_grp3___timer_grp1___lsb 14 1002#define reg_iop_sw_mpu_r_intr_grp3___timer_grp1___width 1 1003#define reg_iop_sw_mpu_r_intr_grp3___timer_grp1___bit 14 1004#define reg_iop_sw_mpu_r_intr_grp3___fifo_in___lsb 15 1005#define reg_iop_sw_mpu_r_intr_grp3___fifo_in___width 1 1006#define reg_iop_sw_mpu_r_intr_grp3___fifo_in___bit 15 1007#define reg_iop_sw_mpu_r_intr_grp3_offset 140 1008 1009/* Register r_masked_intr_grp3, scope iop_sw_mpu, type r */ 1010#define reg_iop_sw_mpu_r_masked_intr_grp3___spu_intr12___lsb 0 1011#define reg_iop_sw_mpu_r_masked_intr_grp3___spu_intr12___width 1 1012#define reg_iop_sw_mpu_r_masked_intr_grp3___spu_intr12___bit 0 1013#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp4___lsb 1 1014#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp4___width 1 1015#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp4___bit 1 1016#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out_extra___lsb 2 1017#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out_extra___width 1 1018#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out_extra___bit 2 1019#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_out___lsb 3 1020#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_out___width 1 1021#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_out___bit 3 1022#define reg_iop_sw_mpu_r_masked_intr_grp3___spu_intr13___lsb 4 1023#define reg_iop_sw_mpu_r_masked_intr_grp3___spu_intr13___width 1 1024#define reg_iop_sw_mpu_r_masked_intr_grp3___spu_intr13___bit 4 1025#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp5___lsb 5 1026#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp5___width 1 1027#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp5___bit 5 1028#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in_extra___lsb 6 1029#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in_extra___width 1 1030#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in_extra___bit 6 1031#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_in___lsb 7 1032#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_in___width 1 1033#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_in___bit 7 1034#define reg_iop_sw_mpu_r_masked_intr_grp3___spu_intr14___lsb 8 1035#define reg_iop_sw_mpu_r_masked_intr_grp3___spu_intr14___width 1 1036#define reg_iop_sw_mpu_r_masked_intr_grp3___spu_intr14___bit 8 1037#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp6___lsb 9 1038#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp6___width 1 1039#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp6___bit 9 1040#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp0___lsb 10 1041#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp0___width 1 1042#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp0___bit 10 1043#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out___lsb 11 1044#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out___width 1 1045#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out___bit 11 1046#define reg_iop_sw_mpu_r_masked_intr_grp3___spu_intr15___lsb 12 1047#define reg_iop_sw_mpu_r_masked_intr_grp3___spu_intr15___width 1 1048#define reg_iop_sw_mpu_r_masked_intr_grp3___spu_intr15___bit 12 1049#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp7___lsb 13 1050#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp7___width 1 1051#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp7___bit 13 1052#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp1___lsb 14 1053#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp1___width 1 1054#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp1___bit 14 1055#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in___lsb 15 1056#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in___width 1 1057#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in___bit 15 1058#define reg_iop_sw_mpu_r_masked_intr_grp3_offset 144 1059 1060 1061/* Constants */ 1062#define regk_iop_sw_mpu_copy 0x00000000 1063#define regk_iop_sw_mpu_cpu 0x00000000 1064#define regk_iop_sw_mpu_mpu 0x00000001 1065#define regk_iop_sw_mpu_no 0x00000000 1066#define regk_iop_sw_mpu_nop 0x00000000 1067#define regk_iop_sw_mpu_rd 0x00000002 1068#define regk_iop_sw_mpu_reg_copy 0x00000001 1069#define regk_iop_sw_mpu_rw_bus_clr_mask_default 0x00000000 1070#define regk_iop_sw_mpu_rw_bus_oe_clr_mask_default 0x00000000 1071#define regk_iop_sw_mpu_rw_bus_oe_set_mask_default 0x00000000 1072#define regk_iop_sw_mpu_rw_bus_set_mask_default 0x00000000 1073#define regk_iop_sw_mpu_rw_gio_clr_mask_default 0x00000000 1074#define regk_iop_sw_mpu_rw_gio_oe_clr_mask_default 0x00000000 1075#define regk_iop_sw_mpu_rw_gio_oe_set_mask_default 0x00000000 1076#define regk_iop_sw_mpu_rw_gio_set_mask_default 0x00000000 1077#define regk_iop_sw_mpu_rw_intr_grp0_mask_default 0x00000000 1078#define regk_iop_sw_mpu_rw_intr_grp1_mask_default 0x00000000 1079#define regk_iop_sw_mpu_rw_intr_grp2_mask_default 0x00000000 1080#define regk_iop_sw_mpu_rw_intr_grp3_mask_default 0x00000000 1081#define regk_iop_sw_mpu_rw_sw_cfg_owner_default 0x00000000 1082#define regk_iop_sw_mpu_set 0x00000001 1083#define regk_iop_sw_mpu_spu 0x00000002 1084#define regk_iop_sw_mpu_wr 0x00000003 1085#define regk_iop_sw_mpu_yes 0x00000001 1086#endif /* __iop_sw_mpu_defs_asm_h */ 1087