1#ifndef __pio_defs_asm_h 2#define __pio_defs_asm_h 3 4/* 5 * This file is autogenerated from 6 * file: pio.r 7 * 8 * by ../../../tools/rdesc/bin/rdes2c -asm -outfile pio_defs_asm.h pio.r 9 * Any changes here will be lost. 10 * 11 * -*- buffer-read-only: t -*- 12 */ 13 14#ifndef REG_FIELD 15#define REG_FIELD( scope, reg, field, value ) \ 16 REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) 17#define REG_FIELD_X_( value, shift ) ((value) << shift) 18#endif 19 20#ifndef REG_STATE 21#define REG_STATE( scope, reg, field, symbolic_value ) \ 22 REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) 23#define REG_STATE_X_( k, shift ) (k << shift) 24#endif 25 26#ifndef REG_MASK 27#define REG_MASK( scope, reg, field ) \ 28 REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) 29#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) 30#endif 31 32#ifndef REG_LSB 33#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb 34#endif 35 36#ifndef REG_BIT 37#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit 38#endif 39 40#ifndef REG_ADDR 41#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) 42#define REG_ADDR_X_( inst, offs ) ((inst) + offs) 43#endif 44 45#ifndef REG_ADDR_VECT 46#define REG_ADDR_VECT( scope, inst, reg, index ) \ 47 REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ 48 STRIDE_##scope##_##reg ) 49#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ 50 ((inst) + offs + (index) * stride) 51#endif 52 53/* Register rw_data, scope pio, type rw */ 54#define reg_pio_rw_data_offset 64 55 56/* Register rw_io_access0, scope pio, type rw */ 57#define reg_pio_rw_io_access0___data___lsb 0 58#define reg_pio_rw_io_access0___data___width 8 59#define reg_pio_rw_io_access0_offset 0 60 61/* Register rw_io_access1, scope pio, type rw */ 62#define reg_pio_rw_io_access1___data___lsb 0 63#define reg_pio_rw_io_access1___data___width 8 64#define reg_pio_rw_io_access1_offset 4 65 66/* Register rw_io_access2, scope pio, type rw */ 67#define reg_pio_rw_io_access2___data___lsb 0 68#define reg_pio_rw_io_access2___data___width 8 69#define reg_pio_rw_io_access2_offset 8 70 71/* Register rw_io_access3, scope pio, type rw */ 72#define reg_pio_rw_io_access3___data___lsb 0 73#define reg_pio_rw_io_access3___data___width 8 74#define reg_pio_rw_io_access3_offset 12 75 76/* Register rw_io_access4, scope pio, type rw */ 77#define reg_pio_rw_io_access4___data___lsb 0 78#define reg_pio_rw_io_access4___data___width 8 79#define reg_pio_rw_io_access4_offset 16 80 81/* Register rw_io_access5, scope pio, type rw */ 82#define reg_pio_rw_io_access5___data___lsb 0 83#define reg_pio_rw_io_access5___data___width 8 84#define reg_pio_rw_io_access5_offset 20 85 86/* Register rw_io_access6, scope pio, type rw */ 87#define reg_pio_rw_io_access6___data___lsb 0 88#define reg_pio_rw_io_access6___data___width 8 89#define reg_pio_rw_io_access6_offset 24 90 91/* Register rw_io_access7, scope pio, type rw */ 92#define reg_pio_rw_io_access7___data___lsb 0 93#define reg_pio_rw_io_access7___data___width 8 94#define reg_pio_rw_io_access7_offset 28 95 96/* Register rw_io_access8, scope pio, type rw */ 97#define reg_pio_rw_io_access8___data___lsb 0 98#define reg_pio_rw_io_access8___data___width 8 99#define reg_pio_rw_io_access8_offset 32 100 101/* Register rw_io_access9, scope pio, type rw */ 102#define reg_pio_rw_io_access9___data___lsb 0 103#define reg_pio_rw_io_access9___data___width 8 104#define reg_pio_rw_io_access9_offset 36 105 106/* Register rw_io_access10, scope pio, type rw */ 107#define reg_pio_rw_io_access10___data___lsb 0 108#define reg_pio_rw_io_access10___data___width 8 109#define reg_pio_rw_io_access10_offset 40 110 111/* Register rw_io_access11, scope pio, type rw */ 112#define reg_pio_rw_io_access11___data___lsb 0 113#define reg_pio_rw_io_access11___data___width 8 114#define reg_pio_rw_io_access11_offset 44 115 116/* Register rw_io_access12, scope pio, type rw */ 117#define reg_pio_rw_io_access12___data___lsb 0 118#define reg_pio_rw_io_access12___data___width 8 119#define reg_pio_rw_io_access12_offset 48 120 121/* Register rw_io_access13, scope pio, type rw */ 122#define reg_pio_rw_io_access13___data___lsb 0 123#define reg_pio_rw_io_access13___data___width 8 124#define reg_pio_rw_io_access13_offset 52 125 126/* Register rw_io_access14, scope pio, type rw */ 127#define reg_pio_rw_io_access14___data___lsb 0 128#define reg_pio_rw_io_access14___data___width 8 129#define reg_pio_rw_io_access14_offset 56 130 131/* Register rw_io_access15, scope pio, type rw */ 132#define reg_pio_rw_io_access15___data___lsb 0 133#define reg_pio_rw_io_access15___data___width 8 134#define reg_pio_rw_io_access15_offset 60 135 136/* Register rw_ce0_cfg, scope pio, type rw */ 137#define reg_pio_rw_ce0_cfg___lw___lsb 0 138#define reg_pio_rw_ce0_cfg___lw___width 6 139#define reg_pio_rw_ce0_cfg___ew___lsb 6 140#define reg_pio_rw_ce0_cfg___ew___width 3 141#define reg_pio_rw_ce0_cfg___zw___lsb 9 142#define reg_pio_rw_ce0_cfg___zw___width 3 143#define reg_pio_rw_ce0_cfg___aw___lsb 12 144#define reg_pio_rw_ce0_cfg___aw___width 2 145#define reg_pio_rw_ce0_cfg___mode___lsb 14 146#define reg_pio_rw_ce0_cfg___mode___width 2 147#define reg_pio_rw_ce0_cfg_offset 68 148 149/* Register rw_ce1_cfg, scope pio, type rw */ 150#define reg_pio_rw_ce1_cfg___lw___lsb 0 151#define reg_pio_rw_ce1_cfg___lw___width 6 152#define reg_pio_rw_ce1_cfg___ew___lsb 6 153#define reg_pio_rw_ce1_cfg___ew___width 3 154#define reg_pio_rw_ce1_cfg___zw___lsb 9 155#define reg_pio_rw_ce1_cfg___zw___width 3 156#define reg_pio_rw_ce1_cfg___aw___lsb 12 157#define reg_pio_rw_ce1_cfg___aw___width 2 158#define reg_pio_rw_ce1_cfg___mode___lsb 14 159#define reg_pio_rw_ce1_cfg___mode___width 2 160#define reg_pio_rw_ce1_cfg_offset 72 161 162/* Register rw_ce2_cfg, scope pio, type rw */ 163#define reg_pio_rw_ce2_cfg___lw___lsb 0 164#define reg_pio_rw_ce2_cfg___lw___width 6 165#define reg_pio_rw_ce2_cfg___ew___lsb 6 166#define reg_pio_rw_ce2_cfg___ew___width 3 167#define reg_pio_rw_ce2_cfg___zw___lsb 9 168#define reg_pio_rw_ce2_cfg___zw___width 3 169#define reg_pio_rw_ce2_cfg___aw___lsb 12 170#define reg_pio_rw_ce2_cfg___aw___width 2 171#define reg_pio_rw_ce2_cfg___mode___lsb 14 172#define reg_pio_rw_ce2_cfg___mode___width 2 173#define reg_pio_rw_ce2_cfg_offset 76 174 175/* Register rw_dout, scope pio, type rw */ 176#define reg_pio_rw_dout___data___lsb 0 177#define reg_pio_rw_dout___data___width 8 178#define reg_pio_rw_dout___rd_n___lsb 8 179#define reg_pio_rw_dout___rd_n___width 1 180#define reg_pio_rw_dout___rd_n___bit 8 181#define reg_pio_rw_dout___wr_n___lsb 9 182#define reg_pio_rw_dout___wr_n___width 1 183#define reg_pio_rw_dout___wr_n___bit 9 184#define reg_pio_rw_dout___a0___lsb 10 185#define reg_pio_rw_dout___a0___width 1 186#define reg_pio_rw_dout___a0___bit 10 187#define reg_pio_rw_dout___a1___lsb 11 188#define reg_pio_rw_dout___a1___width 1 189#define reg_pio_rw_dout___a1___bit 11 190#define reg_pio_rw_dout___ce0_n___lsb 12 191#define reg_pio_rw_dout___ce0_n___width 1 192#define reg_pio_rw_dout___ce0_n___bit 12 193#define reg_pio_rw_dout___ce1_n___lsb 13 194#define reg_pio_rw_dout___ce1_n___width 1 195#define reg_pio_rw_dout___ce1_n___bit 13 196#define reg_pio_rw_dout___ce2_n___lsb 14 197#define reg_pio_rw_dout___ce2_n___width 1 198#define reg_pio_rw_dout___ce2_n___bit 14 199#define reg_pio_rw_dout___rdy___lsb 15 200#define reg_pio_rw_dout___rdy___width 1 201#define reg_pio_rw_dout___rdy___bit 15 202#define reg_pio_rw_dout_offset 80 203 204/* Register rw_oe, scope pio, type rw */ 205#define reg_pio_rw_oe___data___lsb 0 206#define reg_pio_rw_oe___data___width 8 207#define reg_pio_rw_oe___rd_n___lsb 8 208#define reg_pio_rw_oe___rd_n___width 1 209#define reg_pio_rw_oe___rd_n___bit 8 210#define reg_pio_rw_oe___wr_n___lsb 9 211#define reg_pio_rw_oe___wr_n___width 1 212#define reg_pio_rw_oe___wr_n___bit 9 213#define reg_pio_rw_oe___a0___lsb 10 214#define reg_pio_rw_oe___a0___width 1 215#define reg_pio_rw_oe___a0___bit 10 216#define reg_pio_rw_oe___a1___lsb 11 217#define reg_pio_rw_oe___a1___width 1 218#define reg_pio_rw_oe___a1___bit 11 219#define reg_pio_rw_oe___ce0_n___lsb 12 220#define reg_pio_rw_oe___ce0_n___width 1 221#define reg_pio_rw_oe___ce0_n___bit 12 222#define reg_pio_rw_oe___ce1_n___lsb 13 223#define reg_pio_rw_oe___ce1_n___width 1 224#define reg_pio_rw_oe___ce1_n___bit 13 225#define reg_pio_rw_oe___ce2_n___lsb 14 226#define reg_pio_rw_oe___ce2_n___width 1 227#define reg_pio_rw_oe___ce2_n___bit 14 228#define reg_pio_rw_oe___rdy___lsb 15 229#define reg_pio_rw_oe___rdy___width 1 230#define reg_pio_rw_oe___rdy___bit 15 231#define reg_pio_rw_oe_offset 84 232 233/* Register rw_man_ctrl, scope pio, type rw */ 234#define reg_pio_rw_man_ctrl___data___lsb 0 235#define reg_pio_rw_man_ctrl___data___width 8 236#define reg_pio_rw_man_ctrl___rd_n___lsb 8 237#define reg_pio_rw_man_ctrl___rd_n___width 1 238#define reg_pio_rw_man_ctrl___rd_n___bit 8 239#define reg_pio_rw_man_ctrl___wr_n___lsb 9 240#define reg_pio_rw_man_ctrl___wr_n___width 1 241#define reg_pio_rw_man_ctrl___wr_n___bit 9 242#define reg_pio_rw_man_ctrl___a0___lsb 10 243#define reg_pio_rw_man_ctrl___a0___width 1 244#define reg_pio_rw_man_ctrl___a0___bit 10 245#define reg_pio_rw_man_ctrl___a1___lsb 11 246#define reg_pio_rw_man_ctrl___a1___width 1 247#define reg_pio_rw_man_ctrl___a1___bit 11 248#define reg_pio_rw_man_ctrl___ce0_n___lsb 12 249#define reg_pio_rw_man_ctrl___ce0_n___width 1 250#define reg_pio_rw_man_ctrl___ce0_n___bit 12 251#define reg_pio_rw_man_ctrl___ce1_n___lsb 13 252#define reg_pio_rw_man_ctrl___ce1_n___width 1 253#define reg_pio_rw_man_ctrl___ce1_n___bit 13 254#define reg_pio_rw_man_ctrl___ce2_n___lsb 14 255#define reg_pio_rw_man_ctrl___ce2_n___width 1 256#define reg_pio_rw_man_ctrl___ce2_n___bit 14 257#define reg_pio_rw_man_ctrl___rdy___lsb 15 258#define reg_pio_rw_man_ctrl___rdy___width 1 259#define reg_pio_rw_man_ctrl___rdy___bit 15 260#define reg_pio_rw_man_ctrl_offset 88 261 262/* Register r_din, scope pio, type r */ 263#define reg_pio_r_din___data___lsb 0 264#define reg_pio_r_din___data___width 8 265#define reg_pio_r_din___rd_n___lsb 8 266#define reg_pio_r_din___rd_n___width 1 267#define reg_pio_r_din___rd_n___bit 8 268#define reg_pio_r_din___wr_n___lsb 9 269#define reg_pio_r_din___wr_n___width 1 270#define reg_pio_r_din___wr_n___bit 9 271#define reg_pio_r_din___a0___lsb 10 272#define reg_pio_r_din___a0___width 1 273#define reg_pio_r_din___a0___bit 10 274#define reg_pio_r_din___a1___lsb 11 275#define reg_pio_r_din___a1___width 1 276#define reg_pio_r_din___a1___bit 11 277#define reg_pio_r_din___ce0_n___lsb 12 278#define reg_pio_r_din___ce0_n___width 1 279#define reg_pio_r_din___ce0_n___bit 12 280#define reg_pio_r_din___ce1_n___lsb 13 281#define reg_pio_r_din___ce1_n___width 1 282#define reg_pio_r_din___ce1_n___bit 13 283#define reg_pio_r_din___ce2_n___lsb 14 284#define reg_pio_r_din___ce2_n___width 1 285#define reg_pio_r_din___ce2_n___bit 14 286#define reg_pio_r_din___rdy___lsb 15 287#define reg_pio_r_din___rdy___width 1 288#define reg_pio_r_din___rdy___bit 15 289#define reg_pio_r_din_offset 92 290 291/* Register r_stat, scope pio, type r */ 292#define reg_pio_r_stat___busy___lsb 0 293#define reg_pio_r_stat___busy___width 1 294#define reg_pio_r_stat___busy___bit 0 295#define reg_pio_r_stat_offset 96 296 297/* Register rw_intr_mask, scope pio, type rw */ 298#define reg_pio_rw_intr_mask___rdy___lsb 0 299#define reg_pio_rw_intr_mask___rdy___width 1 300#define reg_pio_rw_intr_mask___rdy___bit 0 301#define reg_pio_rw_intr_mask_offset 100 302 303/* Register rw_ack_intr, scope pio, type rw */ 304#define reg_pio_rw_ack_intr___rdy___lsb 0 305#define reg_pio_rw_ack_intr___rdy___width 1 306#define reg_pio_rw_ack_intr___rdy___bit 0 307#define reg_pio_rw_ack_intr_offset 104 308 309/* Register r_intr, scope pio, type r */ 310#define reg_pio_r_intr___rdy___lsb 0 311#define reg_pio_r_intr___rdy___width 1 312#define reg_pio_r_intr___rdy___bit 0 313#define reg_pio_r_intr_offset 108 314 315/* Register r_masked_intr, scope pio, type r */ 316#define reg_pio_r_masked_intr___rdy___lsb 0 317#define reg_pio_r_masked_intr___rdy___width 1 318#define reg_pio_r_masked_intr___rdy___bit 0 319#define reg_pio_r_masked_intr_offset 112 320 321 322/* Constants */ 323#define regk_pio_a2 0x00000003 324#define regk_pio_no 0x00000000 325#define regk_pio_normal 0x00000000 326#define regk_pio_rd 0x00000001 327#define regk_pio_rw_ce0_cfg_default 0x00000000 328#define regk_pio_rw_ce1_cfg_default 0x00000000 329#define regk_pio_rw_ce2_cfg_default 0x00000000 330#define regk_pio_rw_intr_mask_default 0x00000000 331#define regk_pio_rw_man_ctrl_default 0x00000000 332#define regk_pio_rw_oe_default 0x00000000 333#define regk_pio_wr 0x00000002 334#define regk_pio_wr_ce2 0x00000003 335#define regk_pio_yes 0x00000001 336#define regk_pio_yes_all 0x000000ff 337#endif /* __pio_defs_asm_h */ 338