1/* 2 * Simple synchronous serial port driver for ETRAX 100LX. 3 * 4 * Synchronous serial ports are used for continuous streamed data like audio. 5 * The default setting for this driver is compatible with the STA 013 MP3 6 * decoder. The driver can easily be tuned to fit other audio encoder/decoders 7 * and SPI 8 * 9 * Copyright (c) 2001-2008 Axis Communications AB 10 * 11 * Author: Mikael Starvik, Johan Adolfsson 12 * 13 */ 14#include <linux/module.h> 15#include <linux/kernel.h> 16#include <linux/types.h> 17#include <linux/errno.h> 18#include <linux/major.h> 19#include <linux/sched.h> 20#include <linux/interrupt.h> 21#include <linux/poll.h> 22#include <linux/init.h> 23#include <linux/smp_lock.h> 24#include <linux/timer.h> 25#include <asm/irq.h> 26#include <asm/dma.h> 27#include <asm/io.h> 28#include <arch/svinto.h> 29#include <asm/uaccess.h> 30#include <asm/system.h> 31#include <asm/sync_serial.h> 32#include <arch/io_interface_mux.h> 33 34/* The receiver is a bit tricky beacuse of the continuous stream of data.*/ 35/* */ 36/* Three DMA descriptors are linked together. Each DMA descriptor is */ 37/* responsible for port->bufchunk of a common buffer. */ 38/* */ 39/* +---------------------------------------------+ */ 40/* | +----------+ +----------+ +----------+ | */ 41/* +-> | Descr[0] |-->| Descr[1] |-->| Descr[2] |-+ */ 42/* +----------+ +----------+ +----------+ */ 43/* | | | */ 44/* v v v */ 45/* +-------------------------------------+ */ 46/* | BUFFER | */ 47/* +-------------------------------------+ */ 48/* |<- data_avail ->| */ 49/* readp writep */ 50/* */ 51/* If the application keeps up the pace readp will be right after writep.*/ 52/* If the application can't keep the pace we have to throw away data. */ 53/* The idea is that readp should be ready with the data pointed out by */ 54/* Descr[i] when the DMA has filled in Descr[i+1]. */ 55/* Otherwise we will discard */ 56/* the rest of the data pointed out by Descr1 and set readp to the start */ 57/* of Descr2 */ 58 59#define SYNC_SERIAL_MAJOR 125 60 61/* IN_BUFFER_SIZE should be a multiple of 6 to make sure that 24 bit */ 62/* words can be handled */ 63#define IN_BUFFER_SIZE 12288 64#define IN_DESCR_SIZE 256 65#define NUM_IN_DESCR (IN_BUFFER_SIZE/IN_DESCR_SIZE) 66#define OUT_BUFFER_SIZE 4096 67 68#define DEFAULT_FRAME_RATE 0 69#define DEFAULT_WORD_RATE 7 70 71/* NOTE: Enabling some debug will likely cause overrun or underrun, 72 * especially if manual mode is use. 73 */ 74#define DEBUG(x) 75#define DEBUGREAD(x) 76#define DEBUGWRITE(x) 77#define DEBUGPOLL(x) 78#define DEBUGRXINT(x) 79#define DEBUGTXINT(x) 80 81/* Define some macros to access ETRAX 100 registers */ 82#define SETF(var, reg, field, val) \ 83 do { \ 84 var = (var & ~IO_MASK_(reg##_, field##_)) | \ 85 IO_FIELD_(reg##_, field##_, val); \ 86 } while (0) 87 88#define SETS(var, reg, field, val) \ 89 do { \ 90 var = (var & ~IO_MASK_(reg##_, field##_)) | \ 91 IO_STATE_(reg##_, field##_, _##val); \ 92 } while (0) 93 94struct sync_port { 95 /* Etrax registers and bits*/ 96 const volatile unsigned *const status; 97 volatile unsigned *const ctrl_data; 98 volatile unsigned *const output_dma_first; 99 volatile unsigned char *const output_dma_cmd; 100 volatile unsigned char *const output_dma_clr_irq; 101 volatile unsigned *const input_dma_first; 102 volatile unsigned char *const input_dma_cmd; 103 volatile unsigned *const input_dma_descr; 104 /* 8*4 */ 105 volatile unsigned char *const input_dma_clr_irq; 106 volatile unsigned *const data_out; 107 const volatile unsigned *const data_in; 108 char data_avail_bit; /* In R_IRQ_MASK1_RD/SET/CLR */ 109 char transmitter_ready_bit; /* In R_IRQ_MASK1_RD/SET/CLR */ 110 char input_dma_descr_bit; /* In R_IRQ_MASK2_RD */ 111 112 char output_dma_bit; /* In R_IRQ_MASK2_RD */ 113 /* End of fields initialised in array */ 114 char started; /* 1 if port has been started */ 115 char port_nbr; /* Port 0 or 1 */ 116 char busy; /* 1 if port is busy */ 117 118 char enabled; /* 1 if port is enabled */ 119 char use_dma; /* 1 if port uses dma */ 120 char tr_running; 121 122 char init_irqs; 123 124 /* Register shadow */ 125 unsigned int ctrl_data_shadow; 126 /* Remaining bytes for current transfer */ 127 volatile unsigned int out_count; 128 /* Current position in out_buffer */ 129 unsigned char *outp; 130 /* 16*4 */ 131 /* Next byte to be read by application */ 132 volatile unsigned char *volatile readp; 133 /* Next byte to be written by etrax */ 134 volatile unsigned char *volatile writep; 135 136 unsigned int in_buffer_size; 137 unsigned int inbufchunk; 138 struct etrax_dma_descr out_descr __attribute__ ((aligned(32))); 139 struct etrax_dma_descr in_descr[NUM_IN_DESCR] __attribute__ ((aligned(32))); 140 unsigned char out_buffer[OUT_BUFFER_SIZE] __attribute__ ((aligned(32))); 141 unsigned char in_buffer[IN_BUFFER_SIZE]__attribute__ ((aligned(32))); 142 unsigned char flip[IN_BUFFER_SIZE] __attribute__ ((aligned(32))); 143 struct etrax_dma_descr *next_rx_desc; 144 struct etrax_dma_descr *prev_rx_desc; 145 int full; 146 147 wait_queue_head_t out_wait_q; 148 wait_queue_head_t in_wait_q; 149}; 150 151 152static int etrax_sync_serial_init(void); 153static void initialize_port(int portnbr); 154static inline int sync_data_avail(struct sync_port *port); 155 156static int sync_serial_open(struct inode *inode, struct file *file); 157static int sync_serial_release(struct inode *inode, struct file *file); 158static unsigned int sync_serial_poll(struct file *filp, poll_table *wait); 159 160static int sync_serial_ioctl(struct file *file, 161 unsigned int cmd, unsigned long arg); 162static ssize_t sync_serial_write(struct file *file, const char *buf, 163 size_t count, loff_t *ppos); 164static ssize_t sync_serial_read(struct file *file, char *buf, 165 size_t count, loff_t *ppos); 166 167#if ((defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL_PORT0) && \ 168 defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL0_DMA)) || \ 169 (defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL_PORT1) && \ 170 defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL1_DMA))) 171#define SYNC_SER_DMA 172#endif 173 174static void send_word(struct sync_port *port); 175static void start_dma(struct sync_port *port, const char *data, int count); 176static void start_dma_in(struct sync_port *port); 177#ifdef SYNC_SER_DMA 178static irqreturn_t tr_interrupt(int irq, void *dev_id); 179static irqreturn_t rx_interrupt(int irq, void *dev_id); 180#endif 181#if ((defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL_PORT0) && \ 182 !defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL0_DMA)) || \ 183 (defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL_PORT1) && \ 184 !defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL1_DMA))) 185#define SYNC_SER_MANUAL 186#endif 187#ifdef SYNC_SER_MANUAL 188static irqreturn_t manual_interrupt(int irq, void *dev_id); 189#endif 190 191/* The ports */ 192static struct sync_port ports[] = { 193 { 194 .status = R_SYNC_SERIAL1_STATUS, 195 .ctrl_data = R_SYNC_SERIAL1_CTRL, 196 .output_dma_first = R_DMA_CH8_FIRST, 197 .output_dma_cmd = R_DMA_CH8_CMD, 198 .output_dma_clr_irq = R_DMA_CH8_CLR_INTR, 199 .input_dma_first = R_DMA_CH9_FIRST, 200 .input_dma_cmd = R_DMA_CH9_CMD, 201 .input_dma_descr = R_DMA_CH9_DESCR, 202 .input_dma_clr_irq = R_DMA_CH9_CLR_INTR, 203 .data_out = R_SYNC_SERIAL1_TR_DATA, 204 .data_in = R_SYNC_SERIAL1_REC_DATA, 205 .data_avail_bit = IO_BITNR(R_IRQ_MASK1_RD, ser1_data), 206 .transmitter_ready_bit = IO_BITNR(R_IRQ_MASK1_RD, ser1_ready), 207 .input_dma_descr_bit = IO_BITNR(R_IRQ_MASK2_RD, dma9_descr), 208 .output_dma_bit = IO_BITNR(R_IRQ_MASK2_RD, dma8_eop), 209 .init_irqs = 1, 210#if defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL0_DMA) 211 .use_dma = 1, 212#else 213 .use_dma = 0, 214#endif 215 }, 216 { 217 .status = R_SYNC_SERIAL3_STATUS, 218 .ctrl_data = R_SYNC_SERIAL3_CTRL, 219 .output_dma_first = R_DMA_CH4_FIRST, 220 .output_dma_cmd = R_DMA_CH4_CMD, 221 .output_dma_clr_irq = R_DMA_CH4_CLR_INTR, 222 .input_dma_first = R_DMA_CH5_FIRST, 223 .input_dma_cmd = R_DMA_CH5_CMD, 224 .input_dma_descr = R_DMA_CH5_DESCR, 225 .input_dma_clr_irq = R_DMA_CH5_CLR_INTR, 226 .data_out = R_SYNC_SERIAL3_TR_DATA, 227 .data_in = R_SYNC_SERIAL3_REC_DATA, 228 .data_avail_bit = IO_BITNR(R_IRQ_MASK1_RD, ser3_data), 229 .transmitter_ready_bit = IO_BITNR(R_IRQ_MASK1_RD, ser3_ready), 230 .input_dma_descr_bit = IO_BITNR(R_IRQ_MASK2_RD, dma5_descr), 231 .output_dma_bit = IO_BITNR(R_IRQ_MASK2_RD, dma4_eop), 232 .init_irqs = 1, 233#if defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL1_DMA) 234 .use_dma = 1, 235#else 236 .use_dma = 0, 237#endif 238 } 239}; 240 241/* Register shadows */ 242static unsigned sync_serial_prescale_shadow; 243 244#define NUMBER_OF_PORTS 2 245 246static const struct file_operations sync_serial_fops = { 247 .owner = THIS_MODULE, 248 .write = sync_serial_write, 249 .read = sync_serial_read, 250 .poll = sync_serial_poll, 251 .unlocked_ioctl = sync_serial_ioctl, 252 .open = sync_serial_open, 253 .release = sync_serial_release 254}; 255 256static int __init etrax_sync_serial_init(void) 257{ 258 ports[0].enabled = 0; 259 ports[1].enabled = 0; 260 261#if defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL_PORT0) 262 if (cris_request_io_interface(if_sync_serial_1, "sync_ser1")) { 263 printk(KERN_CRIT "ETRAX100LX sync_serial: " 264 "Could not allocate IO group for port %d\n", 0); 265 return -EBUSY; 266 } 267#endif 268#if defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL_PORT1) 269 if (cris_request_io_interface(if_sync_serial_3, "sync_ser3")) { 270#if defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL_PORT0) 271 cris_free_io_interface(if_sync_serial_1); 272#endif 273 printk(KERN_CRIT "ETRAX100LX sync_serial: " 274 "Could not allocate IO group for port %d\n", 1); 275 return -EBUSY; 276 } 277#endif 278 279 if (register_chrdev(SYNC_SERIAL_MAJOR, "sync serial", 280 &sync_serial_fops) < 0) { 281#if defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL_PORT1) 282 cris_free_io_interface(if_sync_serial_3); 283#endif 284#if defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL_PORT0) 285 cris_free_io_interface(if_sync_serial_1); 286#endif 287 printk("unable to get major for synchronous serial port\n"); 288 return -EBUSY; 289 } 290 291 /* Deselect synchronous serial ports while configuring. */ 292 SETS(gen_config_ii_shadow, R_GEN_CONFIG_II, sermode1, async); 293 SETS(gen_config_ii_shadow, R_GEN_CONFIG_II, sermode3, async); 294 *R_GEN_CONFIG_II = gen_config_ii_shadow; 295 296 /* Initialize Ports */ 297#if defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL_PORT0) 298 ports[0].enabled = 1; 299 SETS(port_pb_i2c_shadow, R_PORT_PB_I2C, syncser1, ss1extra); 300 SETS(gen_config_ii_shadow, R_GEN_CONFIG_II, sermode1, sync); 301#if defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL0_DMA) 302 ports[0].use_dma = 1; 303#else 304 ports[0].use_dma = 0; 305#endif 306 initialize_port(0); 307#endif 308 309#if defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL_PORT1) 310 ports[1].enabled = 1; 311 SETS(port_pb_i2c_shadow, R_PORT_PB_I2C, syncser3, ss3extra); 312 SETS(gen_config_ii_shadow, R_GEN_CONFIG_II, sermode3, sync); 313#if defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL1_DMA) 314 ports[1].use_dma = 1; 315#else 316 ports[1].use_dma = 0; 317#endif 318 initialize_port(1); 319#endif 320 321 *R_PORT_PB_I2C = port_pb_i2c_shadow; /* Use PB4/PB7 */ 322 323 /* Set up timing */ 324 *R_SYNC_SERIAL_PRESCALE = sync_serial_prescale_shadow = ( 325 IO_STATE(R_SYNC_SERIAL_PRESCALE, clk_sel_u1, codec) | 326 IO_STATE(R_SYNC_SERIAL_PRESCALE, word_stb_sel_u1, external) | 327 IO_STATE(R_SYNC_SERIAL_PRESCALE, clk_sel_u3, codec) | 328 IO_STATE(R_SYNC_SERIAL_PRESCALE, word_stb_sel_u3, external) | 329 IO_STATE(R_SYNC_SERIAL_PRESCALE, prescaler, div4) | 330 IO_FIELD(R_SYNC_SERIAL_PRESCALE, frame_rate, 331 DEFAULT_FRAME_RATE) | 332 IO_FIELD(R_SYNC_SERIAL_PRESCALE, word_rate, DEFAULT_WORD_RATE) | 333 IO_STATE(R_SYNC_SERIAL_PRESCALE, warp_mode, normal)); 334 335 /* Select synchronous ports */ 336 *R_GEN_CONFIG_II = gen_config_ii_shadow; 337 338 printk(KERN_INFO "ETRAX 100LX synchronous serial port driver\n"); 339 return 0; 340} 341 342static void __init initialize_port(int portnbr) 343{ 344 struct sync_port *port = &ports[portnbr]; 345 346 DEBUG(printk(KERN_DEBUG "Init sync serial port %d\n", portnbr)); 347 348 port->started = 0; 349 port->port_nbr = portnbr; 350 port->busy = 0; 351 port->tr_running = 0; 352 353 port->out_count = 0; 354 port->outp = port->out_buffer; 355 356 port->readp = port->flip; 357 port->writep = port->flip; 358 port->in_buffer_size = IN_BUFFER_SIZE; 359 port->inbufchunk = IN_DESCR_SIZE; 360 port->next_rx_desc = &port->in_descr[0]; 361 port->prev_rx_desc = &port->in_descr[NUM_IN_DESCR-1]; 362 port->prev_rx_desc->ctrl = d_eol; 363 364 init_waitqueue_head(&port->out_wait_q); 365 init_waitqueue_head(&port->in_wait_q); 366 367 port->ctrl_data_shadow = 368 IO_STATE(R_SYNC_SERIAL1_CTRL, tr_baud, c115k2Hz) | 369 IO_STATE(R_SYNC_SERIAL1_CTRL, mode, master_output) | 370 IO_STATE(R_SYNC_SERIAL1_CTRL, error, ignore) | 371 IO_STATE(R_SYNC_SERIAL1_CTRL, rec_enable, disable) | 372 IO_STATE(R_SYNC_SERIAL1_CTRL, f_synctype, normal) | 373 IO_STATE(R_SYNC_SERIAL1_CTRL, f_syncsize, word) | 374 IO_STATE(R_SYNC_SERIAL1_CTRL, f_sync, on) | 375 IO_STATE(R_SYNC_SERIAL1_CTRL, clk_mode, normal) | 376 IO_STATE(R_SYNC_SERIAL1_CTRL, clk_halt, stopped) | 377 IO_STATE(R_SYNC_SERIAL1_CTRL, bitorder, msb) | 378 IO_STATE(R_SYNC_SERIAL1_CTRL, tr_enable, disable) | 379 IO_STATE(R_SYNC_SERIAL1_CTRL, wordsize, size8bit) | 380 IO_STATE(R_SYNC_SERIAL1_CTRL, buf_empty, lmt_8) | 381 IO_STATE(R_SYNC_SERIAL1_CTRL, buf_full, lmt_8) | 382 IO_STATE(R_SYNC_SERIAL1_CTRL, flow_ctrl, enabled) | 383 IO_STATE(R_SYNC_SERIAL1_CTRL, clk_polarity, neg) | 384 IO_STATE(R_SYNC_SERIAL1_CTRL, frame_polarity, normal)| 385 IO_STATE(R_SYNC_SERIAL1_CTRL, status_polarity, inverted)| 386 IO_STATE(R_SYNC_SERIAL1_CTRL, clk_driver, normal) | 387 IO_STATE(R_SYNC_SERIAL1_CTRL, frame_driver, normal) | 388 IO_STATE(R_SYNC_SERIAL1_CTRL, status_driver, normal)| 389 IO_STATE(R_SYNC_SERIAL1_CTRL, def_out0, high); 390 391 if (port->use_dma) 392 port->ctrl_data_shadow |= IO_STATE(R_SYNC_SERIAL1_CTRL, 393 dma_enable, on); 394 else 395 port->ctrl_data_shadow |= IO_STATE(R_SYNC_SERIAL1_CTRL, 396 dma_enable, off); 397 398 *port->ctrl_data = port->ctrl_data_shadow; 399} 400 401static inline int sync_data_avail(struct sync_port *port) 402{ 403 int avail; 404 unsigned char *start; 405 unsigned char *end; 406 407 start = (unsigned char *)port->readp; /* cast away volatile */ 408 end = (unsigned char *)port->writep; /* cast away volatile */ 409 /* 0123456789 0123456789 410 * ----- - ----- 411 * ^rp ^wp ^wp ^rp 412 */ 413 if (end >= start) 414 avail = end - start; 415 else 416 avail = port->in_buffer_size - (start - end); 417 return avail; 418} 419 420static inline int sync_data_avail_to_end(struct sync_port *port) 421{ 422 int avail; 423 unsigned char *start; 424 unsigned char *end; 425 426 start = (unsigned char *)port->readp; /* cast away volatile */ 427 end = (unsigned char *)port->writep; /* cast away volatile */ 428 /* 0123456789 0123456789 429 * ----- ----- 430 * ^rp ^wp ^wp ^rp 431 */ 432 433 if (end >= start) 434 avail = end - start; 435 else 436 avail = port->flip + port->in_buffer_size - start; 437 return avail; 438} 439 440 441static int sync_serial_open(struct inode *inode, struct file *file) 442{ 443 int dev = MINOR(inode->i_rdev); 444 struct sync_port *port; 445 int mode; 446 int err = -EBUSY; 447 448 lock_kernel(); 449 DEBUG(printk(KERN_DEBUG "Open sync serial port %d\n", dev)); 450 451 if (dev < 0 || dev >= NUMBER_OF_PORTS || !ports[dev].enabled) { 452 DEBUG(printk(KERN_DEBUG "Invalid minor %d\n", dev)); 453 err = -ENODEV; 454 goto out; 455 } 456 port = &ports[dev]; 457 /* Allow open this device twice (assuming one reader and one writer) */ 458 if (port->busy == 2) { 459 DEBUG(printk(KERN_DEBUG "Device is busy.. \n")); 460 goto out; 461 } 462 if (port->init_irqs) { 463 if (port->use_dma) { 464 if (port == &ports[0]) { 465#ifdef SYNC_SER_DMA 466 if (request_irq(24, tr_interrupt, 0, 467 "synchronous serial 1 dma tr", 468 &ports[0])) { 469 printk(KERN_CRIT "Can't alloc " 470 "sync serial port 1 IRQ"); 471 goto out; 472 } else if (request_irq(25, rx_interrupt, 0, 473 "synchronous serial 1 dma rx", 474 &ports[0])) { 475 free_irq(24, &port[0]); 476 printk(KERN_CRIT "Can't alloc " 477 "sync serial port 1 IRQ"); 478 goto out; 479 } else if (cris_request_dma(8, 480 "synchronous serial 1 dma tr", 481 DMA_VERBOSE_ON_ERROR, 482 dma_ser1)) { 483 free_irq(24, &port[0]); 484 free_irq(25, &port[0]); 485 printk(KERN_CRIT "Can't alloc " 486 "sync serial port 1 " 487 "TX DMA channel"); 488 goto out; 489 } else if (cris_request_dma(9, 490 "synchronous serial 1 dma rec", 491 DMA_VERBOSE_ON_ERROR, 492 dma_ser1)) { 493 cris_free_dma(8, NULL); 494 free_irq(24, &port[0]); 495 free_irq(25, &port[0]); 496 printk(KERN_CRIT "Can't alloc " 497 "sync serial port 1 " 498 "RX DMA channel"); 499 goto out; 500 } 501#endif 502 RESET_DMA(8); WAIT_DMA(8); 503 RESET_DMA(9); WAIT_DMA(9); 504 *R_DMA_CH8_CLR_INTR = 505 IO_STATE(R_DMA_CH8_CLR_INTR, clr_eop, 506 do) | 507 IO_STATE(R_DMA_CH8_CLR_INTR, clr_descr, 508 do); 509 *R_DMA_CH9_CLR_INTR = 510 IO_STATE(R_DMA_CH9_CLR_INTR, clr_eop, 511 do) | 512 IO_STATE(R_DMA_CH9_CLR_INTR, clr_descr, 513 do); 514 *R_IRQ_MASK2_SET = 515 IO_STATE(R_IRQ_MASK2_SET, dma8_eop, 516 set) | 517 IO_STATE(R_IRQ_MASK2_SET, dma9_descr, 518 set); 519 } else if (port == &ports[1]) { 520#ifdef SYNC_SER_DMA 521 if (request_irq(20, tr_interrupt, 0, 522 "synchronous serial 3 dma tr", 523 &ports[1])) { 524 printk(KERN_CRIT "Can't alloc " 525 "sync serial port 3 IRQ"); 526 goto out; 527 } else if (request_irq(21, rx_interrupt, 0, 528 "synchronous serial 3 dma rx", 529 &ports[1])) { 530 free_irq(20, &ports[1]); 531 printk(KERN_CRIT "Can't alloc " 532 "sync serial port 3 IRQ"); 533 goto out; 534 } else if (cris_request_dma(4, 535 "synchronous serial 3 dma tr", 536 DMA_VERBOSE_ON_ERROR, 537 dma_ser3)) { 538 free_irq(21, &ports[1]); 539 free_irq(20, &ports[1]); 540 printk(KERN_CRIT "Can't alloc " 541 "sync serial port 3 " 542 "TX DMA channel"); 543 goto out; 544 } else if (cris_request_dma(5, 545 "synchronous serial 3 dma rec", 546 DMA_VERBOSE_ON_ERROR, 547 dma_ser3)) { 548 cris_free_dma(4, NULL); 549 free_irq(21, &ports[1]); 550 free_irq(20, &ports[1]); 551 printk(KERN_CRIT "Can't alloc " 552 "sync serial port 3 " 553 "RX DMA channel"); 554 goto out; 555 } 556#endif 557 RESET_DMA(4); WAIT_DMA(4); 558 RESET_DMA(5); WAIT_DMA(5); 559 *R_DMA_CH4_CLR_INTR = 560 IO_STATE(R_DMA_CH4_CLR_INTR, clr_eop, 561 do) | 562 IO_STATE(R_DMA_CH4_CLR_INTR, clr_descr, 563 do); 564 *R_DMA_CH5_CLR_INTR = 565 IO_STATE(R_DMA_CH5_CLR_INTR, clr_eop, 566 do) | 567 IO_STATE(R_DMA_CH5_CLR_INTR, clr_descr, 568 do); 569 *R_IRQ_MASK2_SET = 570 IO_STATE(R_IRQ_MASK2_SET, dma4_eop, 571 set) | 572 IO_STATE(R_IRQ_MASK2_SET, dma5_descr, 573 set); 574 } 575 start_dma_in(port); 576 port->init_irqs = 0; 577 } else { /* !port->use_dma */ 578#ifdef SYNC_SER_MANUAL 579 if (port == &ports[0]) { 580 if (request_irq(8, 581 manual_interrupt, 582 IRQF_SHARED | IRQF_DISABLED, 583 "synchronous serial manual irq", 584 &ports[0])) { 585 printk(KERN_CRIT "Can't alloc " 586 "sync serial manual irq"); 587 goto out; 588 } 589 } else if (port == &ports[1]) { 590 if (request_irq(8, 591 manual_interrupt, 592 IRQF_SHARED | IRQF_DISABLED, 593 "synchronous serial manual irq", 594 &ports[1])) { 595 printk(KERN_CRIT "Can't alloc " 596 "sync serial manual irq"); 597 goto out; 598 } 599 } 600 port->init_irqs = 0; 601#else 602 panic("sync_serial: Manual mode not supported.\n"); 603#endif /* SYNC_SER_MANUAL */ 604 } 605 } /* port->init_irqs */ 606 607 port->busy++; 608 /* Start port if we use it as input */ 609 mode = IO_EXTRACT(R_SYNC_SERIAL1_CTRL, mode, port->ctrl_data_shadow); 610 if (mode == IO_STATE_VALUE(R_SYNC_SERIAL1_CTRL, mode, master_input) || 611 mode == IO_STATE_VALUE(R_SYNC_SERIAL1_CTRL, mode, slave_input) || 612 mode == IO_STATE_VALUE(R_SYNC_SERIAL1_CTRL, mode, master_bidir) || 613 mode == IO_STATE_VALUE(R_SYNC_SERIAL1_CTRL, mode, slave_bidir)) { 614 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, clk_halt, 615 running); 616 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, tr_enable, 617 enable); 618 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, rec_enable, 619 enable); 620 port->started = 1; 621 *port->ctrl_data = port->ctrl_data_shadow; 622 if (!port->use_dma) 623 *R_IRQ_MASK1_SET = 1 << port->data_avail_bit; 624 DEBUG(printk(KERN_DEBUG "sser%d rec started\n", dev)); 625 } 626 ret = 0; 627 628out: 629 unlock_kernel(); 630 return ret; 631} 632 633static int sync_serial_release(struct inode *inode, struct file *file) 634{ 635 int dev = MINOR(inode->i_rdev); 636 struct sync_port *port; 637 638 if (dev < 0 || dev >= NUMBER_OF_PORTS || !ports[dev].enabled) { 639 DEBUG(printk(KERN_DEBUG "Invalid minor %d\n", dev)); 640 return -ENODEV; 641 } 642 port = &ports[dev]; 643 if (port->busy) 644 port->busy--; 645 if (!port->busy) 646 *R_IRQ_MASK1_CLR = ((1 << port->data_avail_bit) | 647 (1 << port->transmitter_ready_bit)); 648 649 return 0; 650} 651 652 653 654static unsigned int sync_serial_poll(struct file *file, poll_table *wait) 655{ 656 int dev = MINOR(file->f_dentry->d_inode->i_rdev); 657 unsigned int mask = 0; 658 struct sync_port *port; 659 DEBUGPOLL(static unsigned int prev_mask = 0); 660 661 port = &ports[dev]; 662 poll_wait(file, &port->out_wait_q, wait); 663 poll_wait(file, &port->in_wait_q, wait); 664 /* Some room to write */ 665 if (port->out_count < OUT_BUFFER_SIZE) 666 mask |= POLLOUT | POLLWRNORM; 667 /* At least an inbufchunk of data */ 668 if (sync_data_avail(port) >= port->inbufchunk) 669 mask |= POLLIN | POLLRDNORM; 670 671 DEBUGPOLL(if (mask != prev_mask) 672 printk(KERN_DEBUG "sync_serial_poll: mask 0x%08X %s %s\n", 673 mask, 674 mask & POLLOUT ? "POLLOUT" : "", 675 mask & POLLIN ? "POLLIN" : ""); 676 prev_mask = mask; 677 ); 678 return mask; 679} 680 681static int sync_serial_ioctl_unlocked(struct file *file, 682 unsigned int cmd, unsigned long arg) 683{ 684 int return_val = 0; 685 unsigned long flags; 686 687 int dev = MINOR(file->f_dentry->d_inode->i_rdev); 688 struct sync_port *port; 689 690 if (dev < 0 || dev >= NUMBER_OF_PORTS || !ports[dev].enabled) { 691 DEBUG(printk(KERN_DEBUG "Invalid minor %d\n", dev)); 692 return -1; 693 } 694 port = &ports[dev]; 695 696 local_irq_save(flags); 697 /* Disable port while changing config */ 698 if (dev) { 699 if (port->use_dma) { 700 RESET_DMA(4); WAIT_DMA(4); 701 port->tr_running = 0; 702 port->out_count = 0; 703 port->outp = port->out_buffer; 704 *R_DMA_CH4_CLR_INTR = 705 IO_STATE(R_DMA_CH4_CLR_INTR, clr_eop, do) | 706 IO_STATE(R_DMA_CH4_CLR_INTR, clr_descr, do); 707 } 708 SETS(gen_config_ii_shadow, R_GEN_CONFIG_II, sermode3, async); 709 } else { 710 if (port->use_dma) { 711 RESET_DMA(8); WAIT_DMA(8); 712 port->tr_running = 0; 713 port->out_count = 0; 714 port->outp = port->out_buffer; 715 *R_DMA_CH8_CLR_INTR = 716 IO_STATE(R_DMA_CH8_CLR_INTR, clr_eop, do) | 717 IO_STATE(R_DMA_CH8_CLR_INTR, clr_descr, do); 718 } 719 SETS(gen_config_ii_shadow, R_GEN_CONFIG_II, sermode1, async); 720 } 721 *R_GEN_CONFIG_II = gen_config_ii_shadow; 722 local_irq_restore(flags); 723 724 switch (cmd) { 725 case SSP_SPEED: 726 if (GET_SPEED(arg) == CODEC) { 727 if (dev) 728 SETS(sync_serial_prescale_shadow, 729 R_SYNC_SERIAL_PRESCALE, clk_sel_u3, 730 codec); 731 else 732 SETS(sync_serial_prescale_shadow, 733 R_SYNC_SERIAL_PRESCALE, clk_sel_u1, 734 codec); 735 736 SETF(sync_serial_prescale_shadow, 737 R_SYNC_SERIAL_PRESCALE, prescaler, 738 GET_FREQ(arg)); 739 SETF(sync_serial_prescale_shadow, 740 R_SYNC_SERIAL_PRESCALE, frame_rate, 741 GET_FRAME_RATE(arg)); 742 SETF(sync_serial_prescale_shadow, 743 R_SYNC_SERIAL_PRESCALE, word_rate, 744 GET_WORD_RATE(arg)); 745 } else { 746 SETF(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, 747 tr_baud, GET_SPEED(arg)); 748 if (dev) 749 SETS(sync_serial_prescale_shadow, 750 R_SYNC_SERIAL_PRESCALE, clk_sel_u3, 751 baudrate); 752 else 753 SETS(sync_serial_prescale_shadow, 754 R_SYNC_SERIAL_PRESCALE, clk_sel_u1, 755 baudrate); 756 } 757 break; 758 case SSP_MODE: 759 if (arg > 5) 760 return -EINVAL; 761 if (arg == MASTER_OUTPUT || arg == SLAVE_OUTPUT) 762 *R_IRQ_MASK1_CLR = 1 << port->data_avail_bit; 763 else if (!port->use_dma) 764 *R_IRQ_MASK1_SET = 1 << port->data_avail_bit; 765 SETF(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, mode, arg); 766 break; 767 case SSP_FRAME_SYNC: 768 if (arg & NORMAL_SYNC) 769 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, 770 f_synctype, normal); 771 else if (arg & EARLY_SYNC) 772 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, 773 f_synctype, early); 774 775 if (arg & BIT_SYNC) 776 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, 777 f_syncsize, bit); 778 else if (arg & WORD_SYNC) 779 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, 780 f_syncsize, word); 781 else if (arg & EXTENDED_SYNC) 782 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, 783 f_syncsize, extended); 784 785 if (arg & SYNC_ON) 786 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, 787 f_sync, on); 788 else if (arg & SYNC_OFF) 789 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, 790 f_sync, off); 791 792 if (arg & WORD_SIZE_8) 793 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, 794 wordsize, size8bit); 795 else if (arg & WORD_SIZE_12) 796 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, 797 wordsize, size12bit); 798 else if (arg & WORD_SIZE_16) 799 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, 800 wordsize, size16bit); 801 else if (arg & WORD_SIZE_24) 802 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, 803 wordsize, size24bit); 804 else if (arg & WORD_SIZE_32) 805 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, 806 wordsize, size32bit); 807 808 if (arg & BIT_ORDER_MSB) 809 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, 810 bitorder, msb); 811 else if (arg & BIT_ORDER_LSB) 812 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, 813 bitorder, lsb); 814 815 if (arg & FLOW_CONTROL_ENABLE) 816 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, 817 flow_ctrl, enabled); 818 else if (arg & FLOW_CONTROL_DISABLE) 819 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, 820 flow_ctrl, disabled); 821 822 if (arg & CLOCK_NOT_GATED) 823 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, 824 clk_mode, normal); 825 else if (arg & CLOCK_GATED) 826 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, 827 clk_mode, gated); 828 829 break; 830 case SSP_IPOLARITY: 831 /* NOTE!! negedge is considered NORMAL */ 832 if (arg & CLOCK_NORMAL) 833 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, 834 clk_polarity, neg); 835 else if (arg & CLOCK_INVERT) 836 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, 837 clk_polarity, pos); 838 839 if (arg & FRAME_NORMAL) 840 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, 841 frame_polarity, normal); 842 else if (arg & FRAME_INVERT) 843 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, 844 frame_polarity, inverted); 845 846 if (arg & STATUS_NORMAL) 847 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, 848 status_polarity, normal); 849 else if (arg & STATUS_INVERT) 850 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, 851 status_polarity, inverted); 852 break; 853 case SSP_OPOLARITY: 854 if (arg & CLOCK_NORMAL) 855 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, 856 clk_driver, normal); 857 else if (arg & CLOCK_INVERT) 858 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, 859 clk_driver, inverted); 860 861 if (arg & FRAME_NORMAL) 862 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, 863 frame_driver, normal); 864 else if (arg & FRAME_INVERT) 865 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, 866 frame_driver, inverted); 867 868 if (arg & STATUS_NORMAL) 869 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, 870 status_driver, normal); 871 else if (arg & STATUS_INVERT) 872 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, 873 status_driver, inverted); 874 break; 875 case SSP_SPI: 876 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, flow_ctrl, 877 disabled); 878 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, bitorder, 879 msb); 880 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, wordsize, 881 size8bit); 882 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, f_sync, on); 883 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, f_syncsize, 884 word); 885 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, f_synctype, 886 normal); 887 if (arg & SPI_SLAVE) { 888 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, 889 frame_polarity, inverted); 890 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, 891 clk_polarity, neg); 892 SETF(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, 893 mode, SLAVE_INPUT); 894 } else { 895 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, 896 frame_driver, inverted); 897 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, 898 clk_driver, inverted); 899 SETF(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, 900 mode, MASTER_OUTPUT); 901 } 902 break; 903 case SSP_INBUFCHUNK: 904 break; 905 default: 906 return_val = -1; 907 } 908 /* Make sure we write the config without interruption */ 909 local_irq_save(flags); 910 /* Set config and enable port */ 911 *port->ctrl_data = port->ctrl_data_shadow; 912 nop(); nop(); nop(); nop(); 913 *R_SYNC_SERIAL_PRESCALE = sync_serial_prescale_shadow; 914 nop(); nop(); nop(); nop(); 915 if (dev) 916 SETS(gen_config_ii_shadow, R_GEN_CONFIG_II, sermode3, sync); 917 else 918 SETS(gen_config_ii_shadow, R_GEN_CONFIG_II, sermode1, sync); 919 920 *R_GEN_CONFIG_II = gen_config_ii_shadow; 921 /* Reset DMA. At readout from serial port the data could be shifted 922 * one byte if not resetting DMA. 923 */ 924 if (port->use_dma) { 925 if (port->port_nbr == 0) { 926 RESET_DMA(9); 927 WAIT_DMA(9); 928 } else { 929 RESET_DMA(5); 930 WAIT_DMA(5); 931 } 932 start_dma_in(port); 933 } 934 local_irq_restore(flags); 935 return return_val; 936} 937 938static long sync_serial_ioctl(struct file *file, 939 unsigned int cmd, unsigned long arg) 940{ 941 long ret; 942 943 lock_kernel(); 944 ret = sync_serial_ioctl_unlocked(file, cmd, arg); 945 unlock_kernel(); 946 947 return ret; 948} 949 950 951static ssize_t sync_serial_write(struct file *file, const char *buf, 952 size_t count, loff_t *ppos) 953{ 954 int dev = MINOR(file->f_dentry->d_inode->i_rdev); 955 DECLARE_WAITQUEUE(wait, current); 956 struct sync_port *port; 957 unsigned long flags; 958 unsigned long c, c1; 959 unsigned long free_outp; 960 unsigned long outp; 961 unsigned long out_buffer; 962 963 if (dev < 0 || dev >= NUMBER_OF_PORTS || !ports[dev].enabled) { 964 DEBUG(printk(KERN_DEBUG "Invalid minor %d\n", dev)); 965 return -ENODEV; 966 } 967 port = &ports[dev]; 968 969 DEBUGWRITE(printk(KERN_DEBUG "W d%d c %lu (%d/%d)\n", 970 port->port_nbr, count, port->out_count, OUT_BUFFER_SIZE)); 971 /* Space to end of buffer */ 972 /* 973 * out_buffer <c1>012345<- c ->OUT_BUFFER_SIZE 974 * outp^ +out_count 975 * ^free_outp 976 * out_buffer 45<- c ->0123OUT_BUFFER_SIZE 977 * +out_count outp^ 978 * free_outp 979 * 980 */ 981 982 /* Read variables that may be updated by interrupts */ 983 local_irq_save(flags); 984 if (count > OUT_BUFFER_SIZE - port->out_count) 985 count = OUT_BUFFER_SIZE - port->out_count; 986 987 outp = (unsigned long)port->outp; 988 free_outp = outp + port->out_count; 989 local_irq_restore(flags); 990 out_buffer = (unsigned long)port->out_buffer; 991 992 /* Find out where and how much to write */ 993 if (free_outp >= out_buffer + OUT_BUFFER_SIZE) 994 free_outp -= OUT_BUFFER_SIZE; 995 if (free_outp >= outp) 996 c = out_buffer + OUT_BUFFER_SIZE - free_outp; 997 else 998 c = outp - free_outp; 999 if (c > count) 1000 c = count; 1001 1002 DEBUGWRITE(printk(KERN_DEBUG "w op %08lX fop %08lX c %lu\n", 1003 outp, free_outp, c)); 1004 if (copy_from_user((void *)free_outp, buf, c)) 1005 return -EFAULT; 1006 1007 if (c != count) { 1008 buf += c; 1009 c1 = count - c; 1010 DEBUGWRITE(printk(KERN_DEBUG "w2 fi %lu c %lu c1 %lu\n", 1011 free_outp-out_buffer, c, c1)); 1012 if (copy_from_user((void *)out_buffer, buf, c1)) 1013 return -EFAULT; 1014 } 1015 local_irq_save(flags); 1016 port->out_count += count; 1017 local_irq_restore(flags); 1018 1019 /* Make sure transmitter/receiver is running */ 1020 if (!port->started) { 1021 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, clk_halt, 1022 running); 1023 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, tr_enable, 1024 enable); 1025 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, rec_enable, 1026 enable); 1027 port->started = 1; 1028 } 1029 1030 *port->ctrl_data = port->ctrl_data_shadow; 1031 1032 if (file->f_flags & O_NONBLOCK) { 1033 local_irq_save(flags); 1034 if (!port->tr_running) { 1035 if (!port->use_dma) { 1036 /* Start sender by writing data */ 1037 send_word(port); 1038 /* and enable transmitter ready IRQ */ 1039 *R_IRQ_MASK1_SET = 1 << 1040 port->transmitter_ready_bit; 1041 } else 1042 start_dma(port, 1043 (unsigned char *volatile)port->outp, c); 1044 } 1045 local_irq_restore(flags); 1046 DEBUGWRITE(printk(KERN_DEBUG "w d%d c %lu NB\n", 1047 port->port_nbr, count)); 1048 return count; 1049 } 1050 1051 /* Sleep until all sent */ 1052 add_wait_queue(&port->out_wait_q, &wait); 1053 set_current_state(TASK_INTERRUPTIBLE); 1054 local_irq_save(flags); 1055 if (!port->tr_running) { 1056 if (!port->use_dma) { 1057 /* Start sender by writing data */ 1058 send_word(port); 1059 /* and enable transmitter ready IRQ */ 1060 *R_IRQ_MASK1_SET = 1 << port->transmitter_ready_bit; 1061 } else 1062 start_dma(port, port->outp, c); 1063 } 1064 local_irq_restore(flags); 1065 schedule(); 1066 set_current_state(TASK_RUNNING); 1067 remove_wait_queue(&port->out_wait_q, &wait); 1068 if (signal_pending(current)) 1069 return -EINTR; 1070 1071 DEBUGWRITE(printk(KERN_DEBUG "w d%d c %lu\n", port->port_nbr, count)); 1072 return count; 1073} 1074 1075static ssize_t sync_serial_read(struct file *file, char *buf, 1076 size_t count, loff_t *ppos) 1077{ 1078 int dev = MINOR(file->f_dentry->d_inode->i_rdev); 1079 int avail; 1080 struct sync_port *port; 1081 unsigned char *start; 1082 unsigned char *end; 1083 unsigned long flags; 1084 1085 if (dev < 0 || dev >= NUMBER_OF_PORTS || !ports[dev].enabled) { 1086 DEBUG(printk(KERN_DEBUG "Invalid minor %d\n", dev)); 1087 return -ENODEV; 1088 } 1089 port = &ports[dev]; 1090 1091 DEBUGREAD(printk(KERN_DEBUG "R%d c %d ri %lu wi %lu /%lu\n", 1092 dev, count, port->readp - port->flip, 1093 port->writep - port->flip, port->in_buffer_size)); 1094 1095 if (!port->started) { 1096 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, clk_halt, 1097 running); 1098 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, tr_enable, 1099 enable); 1100 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, rec_enable, 1101 enable); 1102 port->started = 1; 1103 } 1104 *port->ctrl_data = port->ctrl_data_shadow; 1105 1106 /* Calculate number of available bytes */ 1107 /* Save pointers to avoid that they are modified by interrupt */ 1108 local_irq_save(flags); 1109 start = (unsigned char *)port->readp; /* cast away volatile */ 1110 end = (unsigned char *)port->writep; /* cast away volatile */ 1111 local_irq_restore(flags); 1112 while (start == end && !port->full) { 1113 /* No data */ 1114 if (file->f_flags & O_NONBLOCK) 1115 return -EAGAIN; 1116 1117 interruptible_sleep_on(&port->in_wait_q); 1118 if (signal_pending(current)) 1119 return -EINTR; 1120 1121 local_irq_save(flags); 1122 start = (unsigned char *)port->readp; /* cast away volatile */ 1123 end = (unsigned char *)port->writep; /* cast away volatile */ 1124 local_irq_restore(flags); 1125 } 1126 1127 /* Lazy read, never return wrapped data. */ 1128 if (port->full) 1129 avail = port->in_buffer_size; 1130 else if (end > start) 1131 avail = end - start; 1132 else 1133 avail = port->flip + port->in_buffer_size - start; 1134 1135 count = count > avail ? avail : count; 1136 if (copy_to_user(buf, start, count)) 1137 return -EFAULT; 1138 /* Disable interrupts while updating readp */ 1139 local_irq_save(flags); 1140 port->readp += count; 1141 if (port->readp >= port->flip + port->in_buffer_size) /* Wrap? */ 1142 port->readp = port->flip; 1143 port->full = 0; 1144 local_irq_restore(flags); 1145 DEBUGREAD(printk(KERN_DEBUG "r %d\n", count)); 1146 return count; 1147} 1148 1149static void send_word(struct sync_port *port) 1150{ 1151 switch (IO_EXTRACT(R_SYNC_SERIAL1_CTRL, wordsize, 1152 port->ctrl_data_shadow)) { 1153 case IO_STATE_VALUE(R_SYNC_SERIAL1_CTRL, wordsize, size8bit): 1154 port->out_count--; 1155 *port->data_out = *port->outp++; 1156 if (port->outp >= port->out_buffer + OUT_BUFFER_SIZE) 1157 port->outp = port->out_buffer; 1158 break; 1159 case IO_STATE_VALUE(R_SYNC_SERIAL1_CTRL, wordsize, size12bit): 1160 { 1161 int data = (*port->outp++) << 8; 1162 data |= *port->outp++; 1163 port->out_count -= 2; 1164 *port->data_out = data; 1165 if (port->outp >= port->out_buffer + OUT_BUFFER_SIZE) 1166 port->outp = port->out_buffer; 1167 break; 1168 } 1169 case IO_STATE_VALUE(R_SYNC_SERIAL1_CTRL, wordsize, size16bit): 1170 port->out_count -= 2; 1171 *port->data_out = *(unsigned short *)port->outp; 1172 port->outp += 2; 1173 if (port->outp >= port->out_buffer + OUT_BUFFER_SIZE) 1174 port->outp = port->out_buffer; 1175 break; 1176 case IO_STATE_VALUE(R_SYNC_SERIAL1_CTRL, wordsize, size24bit): 1177 port->out_count -= 3; 1178 *port->data_out = *(unsigned int *)port->outp; 1179 port->outp += 3; 1180 if (port->outp >= port->out_buffer + OUT_BUFFER_SIZE) 1181 port->outp = port->out_buffer; 1182 break; 1183 case IO_STATE_VALUE(R_SYNC_SERIAL1_CTRL, wordsize, size32bit): 1184 port->out_count -= 4; 1185 *port->data_out = *(unsigned int *)port->outp; 1186 port->outp += 4; 1187 if (port->outp >= port->out_buffer + OUT_BUFFER_SIZE) 1188 port->outp = port->out_buffer; 1189 break; 1190 } 1191} 1192 1193 1194static void start_dma(struct sync_port *port, const char *data, int count) 1195{ 1196 port->tr_running = 1; 1197 port->out_descr.hw_len = 0; 1198 port->out_descr.next = 0; 1199 port->out_descr.ctrl = d_eol | d_eop; /* No d_wait to avoid glitches */ 1200 port->out_descr.sw_len = count; 1201 port->out_descr.buf = virt_to_phys(data); 1202 port->out_descr.status = 0; 1203 1204 *port->output_dma_first = virt_to_phys(&port->out_descr); 1205 *port->output_dma_cmd = IO_STATE(R_DMA_CH0_CMD, cmd, start); 1206 DEBUGTXINT(printk(KERN_DEBUG "dma %08lX c %d\n", 1207 (unsigned long)data, count)); 1208} 1209 1210static void start_dma_in(struct sync_port *port) 1211{ 1212 int i; 1213 unsigned long buf; 1214 port->writep = port->flip; 1215 1216 if (port->writep > port->flip + port->in_buffer_size) { 1217 panic("Offset too large in sync serial driver\n"); 1218 return; 1219 } 1220 buf = virt_to_phys(port->in_buffer); 1221 for (i = 0; i < NUM_IN_DESCR; i++) { 1222 port->in_descr[i].sw_len = port->inbufchunk; 1223 port->in_descr[i].ctrl = d_int; 1224 port->in_descr[i].next = virt_to_phys(&port->in_descr[i+1]); 1225 port->in_descr[i].buf = buf; 1226 port->in_descr[i].hw_len = 0; 1227 port->in_descr[i].status = 0; 1228 port->in_descr[i].fifo_len = 0; 1229 buf += port->inbufchunk; 1230 prepare_rx_descriptor(&port->in_descr[i]); 1231 } 1232 /* Link the last descriptor to the first */ 1233 port->in_descr[i-1].next = virt_to_phys(&port->in_descr[0]); 1234 port->in_descr[i-1].ctrl |= d_eol; 1235 port->next_rx_desc = &port->in_descr[0]; 1236 port->prev_rx_desc = &port->in_descr[NUM_IN_DESCR - 1]; 1237 *port->input_dma_first = virt_to_phys(port->next_rx_desc); 1238 *port->input_dma_cmd = IO_STATE(R_DMA_CH0_CMD, cmd, start); 1239} 1240 1241#ifdef SYNC_SER_DMA 1242static irqreturn_t tr_interrupt(int irq, void *dev_id) 1243{ 1244 unsigned long ireg = *R_IRQ_MASK2_RD; 1245 struct etrax_dma_descr *descr; 1246 unsigned int sentl; 1247 int handled = 0; 1248 int i; 1249 1250 for (i = 0; i < NUMBER_OF_PORTS; i++) { 1251 struct sync_port *port = &ports[i]; 1252 if (!port->enabled || !port->use_dma) 1253 continue; 1254 1255 /* IRQ active for the port? */ 1256 if (!(ireg & (1 << port->output_dma_bit))) 1257 continue; 1258 1259 handled = 1; 1260 1261 /* Clear IRQ */ 1262 *port->output_dma_clr_irq = 1263 IO_STATE(R_DMA_CH0_CLR_INTR, clr_eop, do) | 1264 IO_STATE(R_DMA_CH0_CLR_INTR, clr_descr, do); 1265 1266 descr = &port->out_descr; 1267 if (!(descr->status & d_stop)) 1268 sentl = descr->sw_len; 1269 else 1270 /* Otherwise find amount of data sent here */ 1271 sentl = descr->hw_len; 1272 1273 port->out_count -= sentl; 1274 port->outp += sentl; 1275 if (port->outp >= port->out_buffer + OUT_BUFFER_SIZE) 1276 port->outp = port->out_buffer; 1277 if (port->out_count) { 1278 int c = port->out_buffer + OUT_BUFFER_SIZE - port->outp; 1279 if (c > port->out_count) 1280 c = port->out_count; 1281 DEBUGTXINT(printk(KERN_DEBUG 1282 "tx_int DMAWRITE %i %i\n", sentl, c)); 1283 start_dma(port, port->outp, c); 1284 } else { 1285 DEBUGTXINT(printk(KERN_DEBUG 1286 "tx_int DMA stop %i\n", sentl)); 1287 port->tr_running = 0; 1288 } 1289 /* wake up the waiting process */ 1290 wake_up_interruptible(&port->out_wait_q); 1291 } 1292 return IRQ_RETVAL(handled); 1293} /* tr_interrupt */ 1294 1295static irqreturn_t rx_interrupt(int irq, void *dev_id) 1296{ 1297 unsigned long ireg = *R_IRQ_MASK2_RD; 1298 int i; 1299 int handled = 0; 1300 1301 for (i = 0; i < NUMBER_OF_PORTS; i++) { 1302 struct sync_port *port = &ports[i]; 1303 1304 if (!port->enabled || !port->use_dma) 1305 continue; 1306 1307 if (!(ireg & (1 << port->input_dma_descr_bit))) 1308 continue; 1309 1310 /* Descriptor interrupt */ 1311 handled = 1; 1312 while (*port->input_dma_descr != 1313 virt_to_phys(port->next_rx_desc)) { 1314 if (port->writep + port->inbufchunk > port->flip + 1315 port->in_buffer_size) { 1316 int first_size = port->flip + 1317 port->in_buffer_size - port->writep; 1318 memcpy(port->writep, 1319 phys_to_virt(port->next_rx_desc->buf), 1320 first_size); 1321 memcpy(port->flip, 1322 phys_to_virt(port->next_rx_desc->buf + 1323 first_size), 1324 port->inbufchunk - first_size); 1325 port->writep = port->flip + 1326 port->inbufchunk - first_size; 1327 } else { 1328 memcpy(port->writep, 1329 phys_to_virt(port->next_rx_desc->buf), 1330 port->inbufchunk); 1331 port->writep += port->inbufchunk; 1332 if (port->writep >= port->flip 1333 + port->in_buffer_size) 1334 port->writep = port->flip; 1335 } 1336 if (port->writep == port->readp) 1337 port->full = 1; 1338 prepare_rx_descriptor(port->next_rx_desc); 1339 port->next_rx_desc->ctrl |= d_eol; 1340 port->prev_rx_desc->ctrl &= ~d_eol; 1341 port->prev_rx_desc = phys_to_virt((unsigned) 1342 port->next_rx_desc); 1343 port->next_rx_desc = phys_to_virt((unsigned) 1344 port->next_rx_desc->next); 1345 /* Wake up the waiting process */ 1346 wake_up_interruptible(&port->in_wait_q); 1347 *port->input_dma_cmd = IO_STATE(R_DMA_CH1_CMD, 1348 cmd, restart); 1349 /* DMA has reached end of descriptor */ 1350 *port->input_dma_clr_irq = IO_STATE(R_DMA_CH0_CLR_INTR, 1351 clr_descr, do); 1352 } 1353 } 1354 return IRQ_RETVAL(handled); 1355} /* rx_interrupt */ 1356#endif /* SYNC_SER_DMA */ 1357 1358#ifdef SYNC_SER_MANUAL 1359static irqreturn_t manual_interrupt(int irq, void *dev_id) 1360{ 1361 int i; 1362 int handled = 0; 1363 1364 for (i = 0; i < NUMBER_OF_PORTS; i++) { 1365 struct sync_port *port = &ports[i]; 1366 1367 if (!port->enabled || port->use_dma) 1368 continue; 1369 1370 /* Data received? */ 1371 if (*R_IRQ_MASK1_RD & (1 << port->data_avail_bit)) { 1372 handled = 1; 1373 /* Read data */ 1374 switch (port->ctrl_data_shadow & 1375 IO_MASK(R_SYNC_SERIAL1_CTRL, wordsize)) { 1376 case IO_STATE(R_SYNC_SERIAL1_CTRL, wordsize, size8bit): 1377 *port->writep++ = 1378 *(volatile char *)port->data_in; 1379 break; 1380 case IO_STATE(R_SYNC_SERIAL1_CTRL, wordsize, size12bit): 1381 { 1382 int data = *(unsigned short *)port->data_in; 1383 *port->writep = (data & 0x0ff0) >> 4; 1384 *(port->writep + 1) = data & 0x0f; 1385 port->writep += 2; 1386 break; 1387 } 1388 case IO_STATE(R_SYNC_SERIAL1_CTRL, wordsize, size16bit): 1389 *(unsigned short *)port->writep = 1390 *(volatile unsigned short *)port->data_in; 1391 port->writep += 2; 1392 break; 1393 case IO_STATE(R_SYNC_SERIAL1_CTRL, wordsize, size24bit): 1394 *(unsigned int *)port->writep = *port->data_in; 1395 port->writep += 3; 1396 break; 1397 case IO_STATE(R_SYNC_SERIAL1_CTRL, wordsize, size32bit): 1398 *(unsigned int *)port->writep = *port->data_in; 1399 port->writep += 4; 1400 break; 1401 } 1402 1403 /* Wrap? */ 1404 if (port->writep >= port->flip + port->in_buffer_size) 1405 port->writep = port->flip; 1406 if (port->writep == port->readp) { 1407 /* Receive buffer overrun, discard oldest */ 1408 port->readp++; 1409 /* Wrap? */ 1410 if (port->readp >= port->flip + 1411 port->in_buffer_size) 1412 port->readp = port->flip; 1413 } 1414 if (sync_data_avail(port) >= port->inbufchunk) { 1415 /* Wake up application */ 1416 wake_up_interruptible(&port->in_wait_q); 1417 } 1418 } 1419 1420 /* Transmitter ready? */ 1421 if (*R_IRQ_MASK1_RD & (1 << port->transmitter_ready_bit)) { 1422 if (port->out_count > 0) { 1423 /* More data to send */ 1424 send_word(port); 1425 } else { 1426 /* Transmission finished */ 1427 /* Turn off IRQ */ 1428 *R_IRQ_MASK1_CLR = 1 << 1429 port->transmitter_ready_bit; 1430 /* Wake up application */ 1431 wake_up_interruptible(&port->out_wait_q); 1432 } 1433 } 1434 } 1435 return IRQ_RETVAL(handled); 1436} 1437#endif 1438 1439module_init(etrax_sync_serial_init); 1440