1# 2# For a description of the syntax of this configuration file, 3# see Documentation/kbuild/kconfig-language.txt. 4# 5 6mainmenu "Blackfin Kernel Configuration" 7 8config SYMBOL_PREFIX 9 string 10 default "_" 11 12config MMU 13 def_bool n 14 15config FPU 16 def_bool n 17 18config RWSEM_GENERIC_SPINLOCK 19 def_bool y 20 21config RWSEM_XCHGADD_ALGORITHM 22 def_bool n 23 24config BLACKFIN 25 def_bool y 26 select HAVE_ARCH_KGDB 27 select HAVE_ARCH_TRACEHOOK 28 select HAVE_DYNAMIC_FTRACE 29 select HAVE_FTRACE_MCOUNT_RECORD 30 select HAVE_FUNCTION_GRAPH_TRACER 31 select HAVE_FUNCTION_TRACER 32 select HAVE_FUNCTION_TRACE_MCOUNT_TEST 33 select HAVE_IDE 34 select HAVE_KERNEL_GZIP if RAMKERNEL 35 select HAVE_KERNEL_BZIP2 if RAMKERNEL 36 select HAVE_KERNEL_LZMA if RAMKERNEL 37 select HAVE_KERNEL_LZO if RAMKERNEL 38 select HAVE_OPROFILE 39 select ARCH_WANT_OPTIONAL_GPIOLIB 40 41config GENERIC_CSUM 42 def_bool y 43 44config GENERIC_BUG 45 def_bool y 46 depends on BUG 47 48config ZONE_DMA 49 def_bool y 50 51config GENERIC_FIND_NEXT_BIT 52 def_bool y 53 54config GENERIC_HARDIRQS 55 def_bool y 56 57config GENERIC_IRQ_PROBE 58 def_bool y 59 60config GENERIC_HARDIRQS_NO__DO_IRQ 61 def_bool y 62 63config GENERIC_GPIO 64 def_bool y 65 66config FORCE_MAX_ZONEORDER 67 int 68 default "14" 69 70config GENERIC_CALIBRATE_DELAY 71 def_bool y 72 73config LOCKDEP_SUPPORT 74 def_bool y 75 76config STACKTRACE_SUPPORT 77 def_bool y 78 79config TRACE_IRQFLAGS_SUPPORT 80 def_bool y 81 82source "init/Kconfig" 83 84source "kernel/Kconfig.preempt" 85 86source "kernel/Kconfig.freezer" 87 88menu "Blackfin Processor Options" 89 90comment "Processor and Board Settings" 91 92choice 93 prompt "CPU" 94 default BF533 95 96config BF512 97 bool "BF512" 98 help 99 BF512 Processor Support. 100 101config BF514 102 bool "BF514" 103 help 104 BF514 Processor Support. 105 106config BF516 107 bool "BF516" 108 help 109 BF516 Processor Support. 110 111config BF518 112 bool "BF518" 113 help 114 BF518 Processor Support. 115 116config BF522 117 bool "BF522" 118 help 119 BF522 Processor Support. 120 121config BF523 122 bool "BF523" 123 help 124 BF523 Processor Support. 125 126config BF524 127 bool "BF524" 128 help 129 BF524 Processor Support. 130 131config BF525 132 bool "BF525" 133 help 134 BF525 Processor Support. 135 136config BF526 137 bool "BF526" 138 help 139 BF526 Processor Support. 140 141config BF527 142 bool "BF527" 143 help 144 BF527 Processor Support. 145 146config BF531 147 bool "BF531" 148 help 149 BF531 Processor Support. 150 151config BF532 152 bool "BF532" 153 help 154 BF532 Processor Support. 155 156config BF533 157 bool "BF533" 158 help 159 BF533 Processor Support. 160 161config BF534 162 bool "BF534" 163 help 164 BF534 Processor Support. 165 166config BF536 167 bool "BF536" 168 help 169 BF536 Processor Support. 170 171config BF537 172 bool "BF537" 173 help 174 BF537 Processor Support. 175 176config BF538 177 bool "BF538" 178 help 179 BF538 Processor Support. 180 181config BF539 182 bool "BF539" 183 help 184 BF539 Processor Support. 185 186config BF542_std 187 bool "BF542" 188 help 189 BF542 Processor Support. 190 191config BF542M 192 bool "BF542m" 193 help 194 BF542 Processor Support. 195 196config BF544_std 197 bool "BF544" 198 help 199 BF544 Processor Support. 200 201config BF544M 202 bool "BF544m" 203 help 204 BF544 Processor Support. 205 206config BF547_std 207 bool "BF547" 208 help 209 BF547 Processor Support. 210 211config BF547M 212 bool "BF547m" 213 help 214 BF547 Processor Support. 215 216config BF548_std 217 bool "BF548" 218 help 219 BF548 Processor Support. 220 221config BF548M 222 bool "BF548m" 223 help 224 BF548 Processor Support. 225 226config BF549_std 227 bool "BF549" 228 help 229 BF549 Processor Support. 230 231config BF549M 232 bool "BF549m" 233 help 234 BF549 Processor Support. 235 236config BF561 237 bool "BF561" 238 help 239 BF561 Processor Support. 240 241endchoice 242 243config SMP 244 depends on BF561 245 select TICKSOURCE_CORETMR 246 bool "Symmetric multi-processing support" 247 ---help--- 248 This enables support for systems with more than one CPU, 249 like the dual core BF561. If you have a system with only one 250 CPU, say N. If you have a system with more than one CPU, say Y. 251 252 If you don't know what to do here, say N. 253 254config NR_CPUS 255 int 256 depends on SMP 257 default 2 if BF561 258 259config HOTPLUG_CPU 260 bool "Support for hot-pluggable CPUs" 261 depends on SMP && HOTPLUG 262 default y 263 264config IRQ_PER_CPU 265 bool 266 depends on SMP 267 default y 268 269config HAVE_LEGACY_PER_CPU_AREA 270 def_bool y 271 depends on SMP 272 273config BF_REV_MIN 274 int 275 default 0 if (BF51x || BF52x || (BF54x && !BF54xM)) 276 default 2 if (BF537 || BF536 || BF534) 277 default 3 if (BF561 || BF533 || BF532 || BF531 || BF54xM) 278 default 4 if (BF538 || BF539) 279 280config BF_REV_MAX 281 int 282 default 2 if (BF51x || BF52x || (BF54x && !BF54xM)) 283 default 3 if (BF537 || BF536 || BF534 || BF54xM) 284 default 5 if (BF561 || BF538 || BF539) 285 default 6 if (BF533 || BF532 || BF531) 286 287choice 288 prompt "Silicon Rev" 289 default BF_REV_0_0 if (BF51x || BF52x) 290 default BF_REV_0_2 if (BF534 || BF536 || BF537 || (BF54x && !BF54xM)) 291 default BF_REV_0_3 if (BF531 || BF532 || BF533 || BF54xM || BF561) 292 293config BF_REV_0_0 294 bool "0.0" 295 depends on (BF51x || BF52x || (BF54x && !BF54xM)) 296 297config BF_REV_0_1 298 bool "0.1" 299 depends on (BF51x || BF52x || (BF54x && !BF54xM)) 300 301config BF_REV_0_2 302 bool "0.2" 303 depends on (BF52x || BF537 || BF536 || BF534 || (BF54x && !BF54xM)) 304 305config BF_REV_0_3 306 bool "0.3" 307 depends on (BF54xM || BF561 || BF537 || BF536 || BF534 || BF533 || BF532 || BF531) 308 309config BF_REV_0_4 310 bool "0.4" 311 depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539) 312 313config BF_REV_0_5 314 bool "0.5" 315 depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539) 316 317config BF_REV_0_6 318 bool "0.6" 319 depends on (BF533 || BF532 || BF531) 320 321config BF_REV_ANY 322 bool "any" 323 324config BF_REV_NONE 325 bool "none" 326 327endchoice 328 329config BF53x 330 bool 331 depends on (BF531 || BF532 || BF533 || BF534 || BF536 || BF537) 332 default y 333 334config MEM_MT48LC64M4A2FB_7E 335 bool 336 depends on (BFIN533_STAMP) 337 default y 338 339config MEM_MT48LC16M16A2TG_75 340 bool 341 depends on (BFIN533_EZKIT || BFIN561_EZKIT \ 342 || BFIN533_BLUETECHNIX_CM || BFIN537_BLUETECHNIX_CM_E \ 343 || BFIN537_BLUETECHNIX_CM_U || H8606_HVSISTEMAS \ 344 || BFIN527_BLUETECHNIX_CM) 345 default y 346 347config MEM_MT48LC32M8A2_75 348 bool 349 depends on (BFIN518F_EZBRD || BFIN537_STAMP || PNAV10 || BFIN538_EZKIT) 350 default y 351 352config MEM_MT48LC8M32B2B5_7 353 bool 354 depends on (BFIN561_BLUETECHNIX_CM) 355 default y 356 357config MEM_MT48LC32M16A2TG_75 358 bool 359 depends on (BFIN527_EZKIT || BFIN527_EZKIT_V2 || BFIN532_IP0X || BLACKSTAMP) 360 default y 361 362config MEM_MT48H32M16LFCJ_75 363 bool 364 depends on (BFIN526_EZBRD) 365 default y 366 367source "arch/blackfin/mach-bf518/Kconfig" 368source "arch/blackfin/mach-bf527/Kconfig" 369source "arch/blackfin/mach-bf533/Kconfig" 370source "arch/blackfin/mach-bf561/Kconfig" 371source "arch/blackfin/mach-bf537/Kconfig" 372source "arch/blackfin/mach-bf538/Kconfig" 373source "arch/blackfin/mach-bf548/Kconfig" 374 375menu "Board customizations" 376 377config CMDLINE_BOOL 378 bool "Default bootloader kernel arguments" 379 380config CMDLINE 381 string "Initial kernel command string" 382 depends on CMDLINE_BOOL 383 default "console=ttyBF0,57600" 384 help 385 If you don't have a boot loader capable of passing a command line string 386 to the kernel, you may specify one here. As a minimum, you should specify 387 the memory size and the root device (e.g., mem=8M, root=/dev/nfs). 388 389config BOOT_LOAD 390 hex "Kernel load address for booting" 391 default "0x1000" 392 range 0x1000 0x20000000 393 help 394 This option allows you to set the load address of the kernel. 395 This can be useful if you are on a board which has a small amount 396 of memory or you wish to reserve some memory at the beginning of 397 the address space. 398 399 Note that you need to keep this value above 4k (0x1000) as this 400 memory region is used to capture NULL pointer references as well 401 as some core kernel functions. 402 403config ROM_BASE 404 hex "Kernel ROM Base" 405 depends on ROMKERNEL 406 default "0x20040040" 407 range 0x20000000 0x20400000 if !(BF54x || BF561) 408 range 0x20000000 0x30000000 if (BF54x || BF561) 409 help 410 Make sure your ROM base does not include any file-header 411 information that is prepended to the kernel. 412 413 For example, the bootable U-Boot format (created with 414 mkimage) has a 64 byte header (0x40). So while the image 415 you write to flash might start at say 0x20080000, you have 416 to add 0x40 to get the kernel's ROM base as it will come 417 after the header. 418 419comment "Clock/PLL Setup" 420 421config CLKIN_HZ 422 int "Frequency of the crystal on the board in Hz" 423 default "10000000" if BFIN532_IP0X 424 default "11059200" if BFIN533_STAMP 425 default "24576000" if PNAV10 426 default "25000000" # most people use this 427 default "27000000" if BFIN533_EZKIT 428 default "30000000" if BFIN561_EZKIT 429 help 430 The frequency of CLKIN crystal oscillator on the board in Hz. 431 Warning: This value should match the crystal on the board. Otherwise, 432 peripherals won't work properly. 433 434config BFIN_KERNEL_CLOCK 435 bool "Re-program Clocks while Kernel boots?" 436 default n 437 help 438 This option decides if kernel clocks are re-programed from the 439 bootloader settings. If the clocks are not set, the SDRAM settings 440 are also not changed, and the Bootloader does 100% of the hardware 441 configuration. 442 443config PLL_BYPASS 444 bool "Bypass PLL" 445 depends on BFIN_KERNEL_CLOCK 446 default n 447 448config CLKIN_HALF 449 bool "Half Clock In" 450 depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS) 451 default n 452 help 453 If this is set the clock will be divided by 2, before it goes to the PLL. 454 455config VCO_MULT 456 int "VCO Multiplier" 457 depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS) 458 range 1 64 459 default "22" if BFIN533_EZKIT 460 default "45" if BFIN533_STAMP 461 default "20" if (BFIN537_STAMP || BFIN527_EZKIT || BFIN527_EZKIT_V2 || BFIN548_EZKIT || BFIN548_BLUETECHNIX_CM || BFIN538_EZKIT) 462 default "22" if BFIN533_BLUETECHNIX_CM 463 default "20" if (BFIN537_BLUETECHNIX_CM_E || BFIN537_BLUETECHNIX_CM_U || BFIN527_BLUETECHNIX_CM || BFIN561_BLUETECHNIX_CM) 464 default "20" if BFIN561_EZKIT 465 default "16" if (H8606_HVSISTEMAS || BLACKSTAMP || BFIN526_EZBRD || BFIN518F_EZBRD) 466 help 467 This controls the frequency of the on-chip PLL. This can be between 1 and 64. 468 PLL Frequency = (Crystal Frequency) * (this setting) 469 470choice 471 prompt "Core Clock Divider" 472 depends on BFIN_KERNEL_CLOCK 473 default CCLK_DIV_1 474 help 475 This sets the frequency of the core. It can be 1, 2, 4 or 8 476 Core Frequency = (PLL frequency) / (this setting) 477 478config CCLK_DIV_1 479 bool "1" 480 481config CCLK_DIV_2 482 bool "2" 483 484config CCLK_DIV_4 485 bool "4" 486 487config CCLK_DIV_8 488 bool "8" 489endchoice 490 491config SCLK_DIV 492 int "System Clock Divider" 493 depends on BFIN_KERNEL_CLOCK 494 range 1 15 495 default 5 496 help 497 This sets the frequency of the system clock (including SDRAM or DDR). 498 This can be between 1 and 15 499 System Clock = (PLL frequency) / (this setting) 500 501choice 502 prompt "DDR SDRAM Chip Type" 503 depends on BFIN_KERNEL_CLOCK 504 depends on BF54x 505 default MEM_MT46V32M16_5B 506 507config MEM_MT46V32M16_6T 508 bool "MT46V32M16_6T" 509 510config MEM_MT46V32M16_5B 511 bool "MT46V32M16_5B" 512endchoice 513 514choice 515 prompt "DDR/SDRAM Timing" 516 depends on BFIN_KERNEL_CLOCK 517 default BFIN_KERNEL_CLOCK_MEMINIT_CALC 518 help 519 This option allows you to specify Blackfin SDRAM/DDR Timing parameters 520 The calculated SDRAM timing parameters may not be 100% 521 accurate - This option is therefore marked experimental. 522 523config BFIN_KERNEL_CLOCK_MEMINIT_CALC 524 bool "Calculate Timings (EXPERIMENTAL)" 525 depends on EXPERIMENTAL 526 527config BFIN_KERNEL_CLOCK_MEMINIT_SPEC 528 bool "Provide accurate Timings based on target SCLK" 529 help 530 Please consult the Blackfin Hardware Reference Manuals as well 531 as the memory device datasheet. 532 http://docs.blackfin.uclinux.org/doku.php?id=bfin:sdram 533endchoice 534 535menu "Memory Init Control" 536 depends on BFIN_KERNEL_CLOCK_MEMINIT_SPEC 537 538config MEM_DDRCTL0 539 depends on BF54x 540 hex "DDRCTL0" 541 default 0x0 542 543config MEM_DDRCTL1 544 depends on BF54x 545 hex "DDRCTL1" 546 default 0x0 547 548config MEM_DDRCTL2 549 depends on BF54x 550 hex "DDRCTL2" 551 default 0x0 552 553config MEM_EBIU_DDRQUE 554 depends on BF54x 555 hex "DDRQUE" 556 default 0x0 557 558config MEM_SDRRC 559 depends on !BF54x 560 hex "SDRRC" 561 default 0x0 562 563config MEM_SDGCTL 564 depends on !BF54x 565 hex "SDGCTL" 566 default 0x0 567endmenu 568 569# 570# Max & Min Speeds for various Chips 571# 572config MAX_VCO_HZ 573 int 574 default 400000000 if BF512 575 default 400000000 if BF514 576 default 400000000 if BF516 577 default 400000000 if BF518 578 default 400000000 if BF522 579 default 600000000 if BF523 580 default 400000000 if BF524 581 default 600000000 if BF525 582 default 400000000 if BF526 583 default 600000000 if BF527 584 default 400000000 if BF531 585 default 400000000 if BF532 586 default 750000000 if BF533 587 default 500000000 if BF534 588 default 400000000 if BF536 589 default 600000000 if BF537 590 default 533333333 if BF538 591 default 533333333 if BF539 592 default 600000000 if BF542 593 default 533333333 if BF544 594 default 600000000 if BF547 595 default 600000000 if BF548 596 default 533333333 if BF549 597 default 600000000 if BF561 598 599config MIN_VCO_HZ 600 int 601 default 50000000 602 603config MAX_SCLK_HZ 604 int 605 default 133333333 606 607config MIN_SCLK_HZ 608 int 609 default 27000000 610 611comment "Kernel Timer/Scheduler" 612 613source kernel/Kconfig.hz 614 615config GENERIC_CLOCKEVENTS 616 bool "Generic clock events" 617 default y 618 619menu "Clock event device" 620 depends on GENERIC_CLOCKEVENTS 621config TICKSOURCE_GPTMR0 622 bool "GPTimer0" 623 depends on !SMP 624 select BFIN_GPTIMERS 625 626config TICKSOURCE_CORETMR 627 bool "Core timer" 628 default y 629endmenu 630 631menu "Clock souce" 632 depends on GENERIC_CLOCKEVENTS 633config CYCLES_CLOCKSOURCE 634 bool "CYCLES" 635 default y 636 depends on !BFIN_SCRATCH_REG_CYCLES 637 depends on !SMP 638 help 639 If you say Y here, you will enable support for using the 'cycles' 640 registers as a clock source. Doing so means you will be unable to 641 safely write to the 'cycles' register during runtime. You will 642 still be able to read it (such as for performance monitoring), but 643 writing the registers will most likely crash the kernel. 644 645config GPTMR0_CLOCKSOURCE 646 bool "GPTimer0" 647 select BFIN_GPTIMERS 648 depends on !TICKSOURCE_GPTMR0 649endmenu 650 651config ARCH_USES_GETTIMEOFFSET 652 depends on !GENERIC_CLOCKEVENTS 653 def_bool y 654 655source kernel/time/Kconfig 656 657comment "Misc" 658 659choice 660 prompt "Blackfin Exception Scratch Register" 661 default BFIN_SCRATCH_REG_RETN 662 help 663 Select the resource to reserve for the Exception handler: 664 - RETN: Non-Maskable Interrupt (NMI) 665 - RETE: Exception Return (JTAG/ICE) 666 - CYCLES: Performance counter 667 668 If you are unsure, please select "RETN". 669 670config BFIN_SCRATCH_REG_RETN 671 bool "RETN" 672 help 673 Use the RETN register in the Blackfin exception handler 674 as a stack scratch register. This means you cannot 675 safely use NMI on the Blackfin while running Linux, but 676 you can debug the system with a JTAG ICE and use the 677 CYCLES performance registers. 678 679 If you are unsure, please select "RETN". 680 681config BFIN_SCRATCH_REG_RETE 682 bool "RETE" 683 help 684 Use the RETE register in the Blackfin exception handler 685 as a stack scratch register. This means you cannot 686 safely use a JTAG ICE while debugging a Blackfin board, 687 but you can safely use the CYCLES performance registers 688 and the NMI. 689 690 If you are unsure, please select "RETN". 691 692config BFIN_SCRATCH_REG_CYCLES 693 bool "CYCLES" 694 help 695 Use the CYCLES register in the Blackfin exception handler 696 as a stack scratch register. This means you cannot 697 safely use the CYCLES performance registers on a Blackfin 698 board at anytime, but you can debug the system with a JTAG 699 ICE and use the NMI. 700 701 If you are unsure, please select "RETN". 702 703endchoice 704 705endmenu 706 707 708menu "Blackfin Kernel Optimizations" 709 depends on !SMP 710 711comment "Memory Optimizations" 712 713config I_ENTRY_L1 714 bool "Locate interrupt entry code in L1 Memory" 715 default y 716 help 717 If enabled, interrupt entry code (STORE/RESTORE CONTEXT) is linked 718 into L1 instruction memory. (less latency) 719 720config EXCPT_IRQ_SYSC_L1 721 bool "Locate entire ASM lowlevel exception / interrupt - Syscall and CPLB handler code in L1 Memory" 722 default y 723 help 724 If enabled, the entire ASM lowlevel exception and interrupt entry code 725 (STORE/RESTORE CONTEXT) is linked into L1 instruction memory. 726 (less latency) 727 728config DO_IRQ_L1 729 bool "Locate frequently called do_irq dispatcher function in L1 Memory" 730 default y 731 help 732 If enabled, the frequently called do_irq dispatcher function is linked 733 into L1 instruction memory. (less latency) 734 735config CORE_TIMER_IRQ_L1 736 bool "Locate frequently called timer_interrupt() function in L1 Memory" 737 default y 738 help 739 If enabled, the frequently called timer_interrupt() function is linked 740 into L1 instruction memory. (less latency) 741 742config IDLE_L1 743 bool "Locate frequently idle function in L1 Memory" 744 default y 745 help 746 If enabled, the frequently called idle function is linked 747 into L1 instruction memory. (less latency) 748 749config SCHEDULE_L1 750 bool "Locate kernel schedule function in L1 Memory" 751 default y 752 help 753 If enabled, the frequently called kernel schedule is linked 754 into L1 instruction memory. (less latency) 755 756config ARITHMETIC_OPS_L1 757 bool "Locate kernel owned arithmetic functions in L1 Memory" 758 default y 759 help 760 If enabled, arithmetic functions are linked 761 into L1 instruction memory. (less latency) 762 763config ACCESS_OK_L1 764 bool "Locate access_ok function in L1 Memory" 765 default y 766 help 767 If enabled, the access_ok function is linked 768 into L1 instruction memory. (less latency) 769 770config MEMSET_L1 771 bool "Locate memset function in L1 Memory" 772 default y 773 help 774 If enabled, the memset function is linked 775 into L1 instruction memory. (less latency) 776 777config MEMCPY_L1 778 bool "Locate memcpy function in L1 Memory" 779 default y 780 help 781 If enabled, the memcpy function is linked 782 into L1 instruction memory. (less latency) 783 784config STRCMP_L1 785 bool "locate strcmp function in L1 Memory" 786 default y 787 help 788 If enabled, the strcmp function is linked 789 into L1 instruction memory (less latency). 790 791config STRNCMP_L1 792 bool "locate strncmp function in L1 Memory" 793 default y 794 help 795 If enabled, the strncmp function is linked 796 into L1 instruction memory (less latency). 797 798config STRCPY_L1 799 bool "locate strcpy function in L1 Memory" 800 default y 801 help 802 If enabled, the strcpy function is linked 803 into L1 instruction memory (less latency). 804 805config STRNCPY_L1 806 bool "locate strncpy function in L1 Memory" 807 default y 808 help 809 If enabled, the strncpy function is linked 810 into L1 instruction memory (less latency). 811 812config SYS_BFIN_SPINLOCK_L1 813 bool "Locate sys_bfin_spinlock function in L1 Memory" 814 default y 815 help 816 If enabled, sys_bfin_spinlock function is linked 817 into L1 instruction memory. (less latency) 818 819config IP_CHECKSUM_L1 820 bool "Locate IP Checksum function in L1 Memory" 821 default n 822 help 823 If enabled, the IP Checksum function is linked 824 into L1 instruction memory. (less latency) 825 826config CACHELINE_ALIGNED_L1 827 bool "Locate cacheline_aligned data to L1 Data Memory" 828 default y if !BF54x 829 default n if BF54x 830 depends on !BF531 831 help 832 If enabled, cacheline_aligned data is linked 833 into L1 data memory. (less latency) 834 835config SYSCALL_TAB_L1 836 bool "Locate Syscall Table L1 Data Memory" 837 default n 838 depends on !BF531 839 help 840 If enabled, the Syscall LUT is linked 841 into L1 data memory. (less latency) 842 843config CPLB_SWITCH_TAB_L1 844 bool "Locate CPLB Switch Tables L1 Data Memory" 845 default n 846 depends on !BF531 847 help 848 If enabled, the CPLB Switch Tables are linked 849 into L1 data memory. (less latency) 850 851config CACHE_FLUSH_L1 852 bool "Locate cache flush funcs in L1 Inst Memory" 853 default y 854 help 855 If enabled, the Blackfin cache flushing functions are linked 856 into L1 instruction memory. 857 858 Note that this might be required to address anomalies, but 859 these functions are pretty small, so it shouldn't be too bad. 860 If you are using a processor affected by an anomaly, the build 861 system will double check for you and prevent it. 862 863config APP_STACK_L1 864 bool "Support locating application stack in L1 Scratch Memory" 865 default y 866 help 867 If enabled the application stack can be located in L1 868 scratch memory (less latency). 869 870 Currently only works with FLAT binaries. 871 872config EXCEPTION_L1_SCRATCH 873 bool "Locate exception stack in L1 Scratch Memory" 874 default n 875 depends on !APP_STACK_L1 876 help 877 Whenever an exception occurs, use the L1 Scratch memory for 878 stack storage. You cannot place the stacks of FLAT binaries 879 in L1 when using this option. 880 881 If you don't use L1 Scratch, then you should say Y here. 882 883comment "Speed Optimizations" 884config BFIN_INS_LOWOVERHEAD 885 bool "ins[bwl] low overhead, higher interrupt latency" 886 default y 887 help 888 Reads on the Blackfin are speculative. In Blackfin terms, this means 889 they can be interrupted at any time (even after they have been issued 890 on to the external bus), and re-issued after the interrupt occurs. 891 For memory - this is not a big deal, since memory does not change if 892 it sees a read. 893 894 If a FIFO is sitting on the end of the read, it will see two reads, 895 when the core only sees one since the FIFO receives both the read 896 which is cancelled (and not delivered to the core) and the one which 897 is re-issued (which is delivered to the core). 898 899 To solve this, interrupts are turned off before reads occur to 900 I/O space. This option controls which the overhead/latency of 901 controlling interrupts during this time 902 "n" turns interrupts off every read 903 (higher overhead, but lower interrupt latency) 904 "y" turns interrupts off every loop 905 (low overhead, but longer interrupt latency) 906 907 default behavior is to leave this set to on (type "Y"). If you are experiencing 908 interrupt latency issues, it is safe and OK to turn this off. 909 910endmenu 911 912choice 913 prompt "Kernel executes from" 914 help 915 Choose the memory type that the kernel will be running in. 916 917config RAMKERNEL 918 bool "RAM" 919 help 920 The kernel will be resident in RAM when running. 921 922config ROMKERNEL 923 bool "ROM" 924 help 925 The kernel will be resident in FLASH/ROM when running. 926 927endchoice 928 929source "mm/Kconfig" 930 931config BFIN_GPTIMERS 932 tristate "Enable Blackfin General Purpose Timers API" 933 default n 934 help 935 Enable support for the General Purpose Timers API. If you 936 are unsure, say N. 937 938 To compile this driver as a module, choose M here: the module 939 will be called gptimers. 940 941choice 942 prompt "Uncached DMA region" 943 default DMA_UNCACHED_1M 944config DMA_UNCACHED_4M 945 bool "Enable 4M DMA region" 946config DMA_UNCACHED_2M 947 bool "Enable 2M DMA region" 948config DMA_UNCACHED_1M 949 bool "Enable 1M DMA region" 950config DMA_UNCACHED_512K 951 bool "Enable 512K DMA region" 952config DMA_UNCACHED_256K 953 bool "Enable 256K DMA region" 954config DMA_UNCACHED_128K 955 bool "Enable 128K DMA region" 956config DMA_UNCACHED_NONE 957 bool "Disable DMA region" 958endchoice 959 960 961comment "Cache Support" 962 963config BFIN_ICACHE 964 bool "Enable ICACHE" 965 default y 966config BFIN_EXTMEM_ICACHEABLE 967 bool "Enable ICACHE for external memory" 968 depends on BFIN_ICACHE 969 default y 970config BFIN_L2_ICACHEABLE 971 bool "Enable ICACHE for L2 SRAM" 972 depends on BFIN_ICACHE 973 depends on BF54x || BF561 974 default n 975 976config BFIN_DCACHE 977 bool "Enable DCACHE" 978 default y 979config BFIN_DCACHE_BANKA 980 bool "Enable only 16k BankA DCACHE - BankB is SRAM" 981 depends on BFIN_DCACHE && !BF531 982 default n 983config BFIN_EXTMEM_DCACHEABLE 984 bool "Enable DCACHE for external memory" 985 depends on BFIN_DCACHE 986 default y 987choice 988 prompt "External memory DCACHE policy" 989 depends on BFIN_EXTMEM_DCACHEABLE 990 default BFIN_EXTMEM_WRITEBACK if !SMP 991 default BFIN_EXTMEM_WRITETHROUGH if SMP 992config BFIN_EXTMEM_WRITEBACK 993 bool "Write back" 994 depends on !SMP 995 help 996 Write Back Policy: 997 Cached data will be written back to SDRAM only when needed. 998 This can give a nice increase in performance, but beware of 999 broken drivers that do not properly invalidate/flush their 1000 cache. 1001 1002 Write Through Policy: 1003 Cached data will always be written back to SDRAM when the 1004 cache is updated. This is a completely safe setting, but 1005 performance is worse than Write Back. 1006 1007 If you are unsure of the options and you want to be safe, 1008 then go with Write Through. 1009 1010config BFIN_EXTMEM_WRITETHROUGH 1011 bool "Write through" 1012 help 1013 Write Back Policy: 1014 Cached data will be written back to SDRAM only when needed. 1015 This can give a nice increase in performance, but beware of 1016 broken drivers that do not properly invalidate/flush their 1017 cache. 1018 1019 Write Through Policy: 1020 Cached data will always be written back to SDRAM when the 1021 cache is updated. This is a completely safe setting, but 1022 performance is worse than Write Back. 1023 1024 If you are unsure of the options and you want to be safe, 1025 then go with Write Through. 1026 1027endchoice 1028 1029config BFIN_L2_DCACHEABLE 1030 bool "Enable DCACHE for L2 SRAM" 1031 depends on BFIN_DCACHE 1032 depends on (BF54x || BF561) && !SMP 1033 default n 1034choice 1035 prompt "L2 SRAM DCACHE policy" 1036 depends on BFIN_L2_DCACHEABLE 1037 default BFIN_L2_WRITEBACK 1038config BFIN_L2_WRITEBACK 1039 bool "Write back" 1040 1041config BFIN_L2_WRITETHROUGH 1042 bool "Write through" 1043endchoice 1044 1045 1046comment "Memory Protection Unit" 1047config MPU 1048 bool "Enable the memory protection unit (EXPERIMENTAL)" 1049 default n 1050 help 1051 Use the processor's MPU to protect applications from accessing 1052 memory they do not own. This comes at a performance penalty 1053 and is recommended only for debugging. 1054 1055comment "Asynchronous Memory Configuration" 1056 1057menu "EBIU_AMGCTL Global Control" 1058config C_AMCKEN 1059 bool "Enable CLKOUT" 1060 default y 1061 1062config C_CDPRIO 1063 bool "DMA has priority over core for ext. accesses" 1064 default n 1065 1066config C_B0PEN 1067 depends on BF561 1068 bool "Bank 0 16 bit packing enable" 1069 default y 1070 1071config C_B1PEN 1072 depends on BF561 1073 bool "Bank 1 16 bit packing enable" 1074 default y 1075 1076config C_B2PEN 1077 depends on BF561 1078 bool "Bank 2 16 bit packing enable" 1079 default y 1080 1081config C_B3PEN 1082 depends on BF561 1083 bool "Bank 3 16 bit packing enable" 1084 default n 1085 1086choice 1087 prompt "Enable Asynchronous Memory Banks" 1088 default C_AMBEN_ALL 1089 1090config C_AMBEN 1091 bool "Disable All Banks" 1092 1093config C_AMBEN_B0 1094 bool "Enable Bank 0" 1095 1096config C_AMBEN_B0_B1 1097 bool "Enable Bank 0 & 1" 1098 1099config C_AMBEN_B0_B1_B2 1100 bool "Enable Bank 0 & 1 & 2" 1101 1102config C_AMBEN_ALL 1103 bool "Enable All Banks" 1104endchoice 1105endmenu 1106 1107menu "EBIU_AMBCTL Control" 1108config BANK_0 1109 hex "Bank 0 (AMBCTL0.L)" 1110 default 0x7BB0 1111 help 1112 These are the low 16 bits of the EBIU_AMBCTL0 MMR which are 1113 used to control the Asynchronous Memory Bank 0 settings. 1114 1115config BANK_1 1116 hex "Bank 1 (AMBCTL0.H)" 1117 default 0x7BB0 1118 default 0x5558 if BF54x 1119 help 1120 These are the high 16 bits of the EBIU_AMBCTL0 MMR which are 1121 used to control the Asynchronous Memory Bank 1 settings. 1122 1123config BANK_2 1124 hex "Bank 2 (AMBCTL1.L)" 1125 default 0x7BB0 1126 help 1127 These are the low 16 bits of the EBIU_AMBCTL1 MMR which are 1128 used to control the Asynchronous Memory Bank 2 settings. 1129 1130config BANK_3 1131 hex "Bank 3 (AMBCTL1.H)" 1132 default 0x99B3 1133 help 1134 These are the high 16 bits of the EBIU_AMBCTL1 MMR which are 1135 used to control the Asynchronous Memory Bank 3 settings. 1136 1137endmenu 1138 1139config EBIU_MBSCTLVAL 1140 hex "EBIU Bank Select Control Register" 1141 depends on BF54x 1142 default 0 1143 1144config EBIU_MODEVAL 1145 hex "Flash Memory Mode Control Register" 1146 depends on BF54x 1147 default 1 1148 1149config EBIU_FCTLVAL 1150 hex "Flash Memory Bank Control Register" 1151 depends on BF54x 1152 default 6 1153endmenu 1154 1155############################################################################# 1156menu "Bus options (PCI, PCMCIA, EISA, MCA, ISA)" 1157 1158config PCI 1159 bool "PCI support" 1160 depends on BROKEN 1161 help 1162 Support for PCI bus. 1163 1164source "drivers/pci/Kconfig" 1165 1166source "drivers/pcmcia/Kconfig" 1167 1168source "drivers/pci/hotplug/Kconfig" 1169 1170endmenu 1171 1172menu "Executable file formats" 1173 1174source "fs/Kconfig.binfmt" 1175 1176endmenu 1177 1178menu "Power management options" 1179 1180source "kernel/power/Kconfig" 1181 1182config ARCH_SUSPEND_POSSIBLE 1183 def_bool y 1184 1185choice 1186 prompt "Standby Power Saving Mode" 1187 depends on PM 1188 default PM_BFIN_SLEEP_DEEPER 1189config PM_BFIN_SLEEP_DEEPER 1190 bool "Sleep Deeper" 1191 help 1192 Sleep "Deeper" Mode (High Power Savings) - This mode reduces dynamic 1193 power dissipation by disabling the clock to the processor core (CCLK). 1194 Furthermore, Standby sets the internal power supply voltage (VDDINT) 1195 to 0.85 V to provide the greatest power savings, while preserving the 1196 processor state. 1197 The PLL and system clock (SCLK) continue to operate at a very low 1198 frequency of about 3.3 MHz. To preserve data integrity in the SDRAM, 1199 the SDRAM is put into Self Refresh Mode. Typically an external event 1200 such as GPIO interrupt or RTC activity wakes up the processor. 1201 Various Peripherals such as UART, SPORT, PPI may not function as 1202 normal during Sleep Deeper, due to the reduced SCLK frequency. 1203 When in the sleep mode, system DMA access to L1 memory is not supported. 1204 1205 If unsure, select "Sleep Deeper". 1206 1207config PM_BFIN_SLEEP 1208 bool "Sleep" 1209 help 1210 Sleep Mode (High Power Savings) - The sleep mode reduces power 1211 dissipation by disabling the clock to the processor core (CCLK). 1212 The PLL and system clock (SCLK), however, continue to operate in 1213 this mode. Typically an external event or RTC activity will wake 1214 up the processor. When in the sleep mode, system DMA access to L1 1215 memory is not supported. 1216 1217 If unsure, select "Sleep Deeper". 1218endchoice 1219 1220comment "Possible Suspend Mem / Hibernate Wake-Up Sources" 1221 depends on PM 1222 1223config PM_BFIN_WAKE_PH6 1224 bool "Allow Wake-Up from on-chip PHY or PH6 GP" 1225 depends on PM && (BF51x || BF52x || BF534 || BF536 || BF537) 1226 default n 1227 help 1228 Enable PHY and PH6 GP Wake-Up (Voltage Regulator Power-Up) 1229 1230config PM_BFIN_WAKE_GP 1231 bool "Allow Wake-Up from GPIOs" 1232 depends on PM && BF54x 1233 default n 1234 help 1235 Enable General-Purpose Wake-Up (Voltage Regulator Power-Up) 1236 (all processors, except ADSP-BF549). This option sets 1237 the general-purpose wake-up enable (GPWE) control bit to enable 1238 wake-up upon detection of an active low signal on the /GPW (PH7) pin. 1239 On ADSP-BF549 this option enables the the same functionality on the 1240 /MRXON pin also PH7. 1241 1242endmenu 1243 1244menu "CPU Frequency scaling" 1245 1246source "drivers/cpufreq/Kconfig" 1247 1248config BFIN_CPU_FREQ 1249 bool 1250 depends on CPU_FREQ 1251 select CPU_FREQ_TABLE 1252 default y 1253 1254config CPU_VOLTAGE 1255 bool "CPU Voltage scaling" 1256 depends on EXPERIMENTAL 1257 depends on CPU_FREQ 1258 default n 1259 help 1260 Say Y here if you want CPU voltage scaling according to the CPU frequency. 1261 This option violates the PLL BYPASS recommendation in the Blackfin Processor 1262 manuals. There is a theoretical risk that during VDDINT transitions 1263 the PLL may unlock. 1264 1265endmenu 1266 1267source "net/Kconfig" 1268 1269source "drivers/Kconfig" 1270 1271source "drivers/firmware/Kconfig" 1272 1273source "fs/Kconfig" 1274 1275source "arch/blackfin/Kconfig.debug" 1276 1277source "security/Kconfig" 1278 1279source "crypto/Kconfig" 1280 1281source "lib/Kconfig" 1282