1/* 2 * arch/arm/plat-omap/include/mach/io.h 3 * 4 * IO definitions for TI OMAP processors and boards 5 * 6 * Copied from arch/arm/mach-sa1100/include/mach/io.h 7 * Copyright (C) 1997-1999 Russell King 8 * 9 * Copyright (C) 2009 Texas Instruments 10 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com> 11 * 12 * This program is free software; you can redistribute it and/or modify it 13 * under the terms of the GNU General Public License as published by the 14 * Free Software Foundation; either version 2 of the License, or (at your 15 * option) any later version. 16 * 17 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED 18 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 19 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN 20 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF 23 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 24 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * You should have received a copy of the GNU General Public License along 29 * with this program; if not, write to the Free Software Foundation, Inc., 30 * 675 Mass Ave, Cambridge, MA 02139, USA. 31 * 32 * Modifications: 33 * 06-12-1997 RMK Created. 34 * 07-04-1999 RMK Major cleanup 35 */ 36 37#ifndef __ASM_ARM_ARCH_IO_H 38#define __ASM_ARM_ARCH_IO_H 39 40#include <mach/hardware.h> 41 42#define IO_SPACE_LIMIT 0xffffffff 43 44/* 45 * We don't actually have real ISA nor PCI buses, but there is so many 46 * drivers out there that might just work if we fake them... 47 */ 48#define __io(a) __typesafe_io(a) 49#define __mem_pci(a) (a) 50 51/* 52 * ---------------------------------------------------------------------------- 53 * I/O mapping 54 * ---------------------------------------------------------------------------- 55 */ 56 57#ifdef __ASSEMBLER__ 58#define IOMEM(x) (x) 59#else 60#define IOMEM(x) ((void __force __iomem *)(x)) 61#endif 62 63#define OMAP1_IO_OFFSET 0x01000000 /* Virtual IO = 0xfefb0000 */ 64#define OMAP1_IO_ADDRESS(pa) IOMEM((pa) - OMAP1_IO_OFFSET) 65 66#define OMAP2_L3_IO_OFFSET 0x90000000 67#define OMAP2_L3_IO_ADDRESS(pa) IOMEM((pa) + OMAP2_L3_IO_OFFSET) /* L3 */ 68 69 70#define OMAP2_L4_IO_OFFSET 0xb2000000 71#define OMAP2_L4_IO_ADDRESS(pa) IOMEM((pa) + OMAP2_L4_IO_OFFSET) /* L4 */ 72 73#define OMAP4_L3_IO_OFFSET 0xb4000000 74#define OMAP4_L3_IO_ADDRESS(pa) IOMEM((pa) + OMAP4_L3_IO_OFFSET) /* L3 */ 75 76#define OMAP4_L3_PER_IO_OFFSET 0xb1100000 77#define OMAP4_L3_PER_IO_ADDRESS(pa) IOMEM((pa) + OMAP4_L3_PER_IO_OFFSET) 78 79#define OMAP4_GPMC_IO_OFFSET 0xa9000000 80#define OMAP4_GPMC_IO_ADDRESS(pa) IOMEM((pa) + OMAP4_GPMC_IO_OFFSET) 81 82#define OMAP2_EMU_IO_OFFSET 0xaa800000 /* Emulation */ 83#define OMAP2_EMU_IO_ADDRESS(pa) IOMEM((pa) + OMAP2_EMU_IO_OFFSET) 84 85/* 86 * ---------------------------------------------------------------------------- 87 * Omap1 specific IO mapping 88 * ---------------------------------------------------------------------------- 89 */ 90 91#define OMAP1_IO_PHYS 0xFFFB0000 92#define OMAP1_IO_SIZE 0x40000 93#define OMAP1_IO_VIRT (OMAP1_IO_PHYS - OMAP1_IO_OFFSET) 94 95/* 96 * ---------------------------------------------------------------------------- 97 * Omap2 specific IO mapping 98 * ---------------------------------------------------------------------------- 99 */ 100 101/* We map both L3 and L4 on OMAP2 */ 102#define L3_24XX_PHYS L3_24XX_BASE /* 0x68000000 --> 0xf8000000*/ 103#define L3_24XX_VIRT (L3_24XX_PHYS + OMAP2_L3_IO_OFFSET) 104#define L3_24XX_SIZE SZ_1M /* 44kB of 128MB used, want 1MB sect */ 105#define L4_24XX_PHYS L4_24XX_BASE /* 0x48000000 --> 0xfa000000 */ 106#define L4_24XX_VIRT (L4_24XX_PHYS + OMAP2_L4_IO_OFFSET) 107#define L4_24XX_SIZE SZ_1M /* 1MB of 128MB used, want 1MB sect */ 108 109#define L4_WK_243X_PHYS L4_WK_243X_BASE /* 0x49000000 --> 0xfb000000 */ 110#define L4_WK_243X_VIRT (L4_WK_243X_PHYS + OMAP2_L4_IO_OFFSET) 111#define L4_WK_243X_SIZE SZ_1M 112#define OMAP243X_GPMC_PHYS OMAP243X_GPMC_BASE 113#define OMAP243X_GPMC_VIRT (OMAP243X_GPMC_PHYS + OMAP2_L3_IO_OFFSET) 114 /* 0x6e000000 --> 0xfe000000 */ 115#define OMAP243X_GPMC_SIZE SZ_1M 116#define OMAP243X_SDRC_PHYS OMAP243X_SDRC_BASE 117 /* 0x6D000000 --> 0xfd000000 */ 118#define OMAP243X_SDRC_VIRT (OMAP243X_SDRC_PHYS + OMAP2_L3_IO_OFFSET) 119#define OMAP243X_SDRC_SIZE SZ_1M 120#define OMAP243X_SMS_PHYS OMAP243X_SMS_BASE 121 /* 0x6c000000 --> 0xfc000000 */ 122#define OMAP243X_SMS_VIRT (OMAP243X_SMS_PHYS + OMAP2_L3_IO_OFFSET) 123#define OMAP243X_SMS_SIZE SZ_1M 124 125/* 2420 IVA */ 126#define DSP_MEM_2420_PHYS OMAP2420_DSP_MEM_BASE 127 /* 0x58000000 --> 0xfc100000 */ 128#define DSP_MEM_2420_VIRT 0xfc100000 129#define DSP_MEM_2420_SIZE 0x28000 130#define DSP_IPI_2420_PHYS OMAP2420_DSP_IPI_BASE 131 /* 0x59000000 --> 0xfc128000 */ 132#define DSP_IPI_2420_VIRT 0xfc128000 133#define DSP_IPI_2420_SIZE SZ_4K 134#define DSP_MMU_2420_PHYS OMAP2420_DSP_MMU_BASE 135 /* 0x5a000000 --> 0xfc129000 */ 136#define DSP_MMU_2420_VIRT 0xfc129000 137#define DSP_MMU_2420_SIZE SZ_4K 138 139/* 2430 IVA2.1 - currently unmapped */ 140 141/* 142 * ---------------------------------------------------------------------------- 143 * Omap3 specific IO mapping 144 * ---------------------------------------------------------------------------- 145 */ 146 147/* We map both L3 and L4 on OMAP3 */ 148#define L3_34XX_PHYS L3_34XX_BASE /* 0x68000000 --> 0xf8000000 */ 149#define L3_34XX_VIRT (L3_34XX_PHYS + OMAP2_L3_IO_OFFSET) 150#define L3_34XX_SIZE SZ_1M /* 44kB of 128MB used, want 1MB sect */ 151 152#define L4_34XX_PHYS L4_34XX_BASE /* 0x48000000 --> 0xfa000000 */ 153#define L4_34XX_VIRT (L4_34XX_PHYS + OMAP2_L4_IO_OFFSET) 154#define L4_34XX_SIZE SZ_4M /* 1MB of 128MB used, want 1MB sect */ 155 156/* 157 * Need to look at the Size 4M for L4. 158 * VPOM3430 was not working for Int controller 159 */ 160 161#define L4_PER_34XX_PHYS L4_PER_34XX_BASE 162 /* 0x49000000 --> 0xfb000000 */ 163#define L4_PER_34XX_VIRT (L4_PER_34XX_PHYS + OMAP2_L4_IO_OFFSET) 164#define L4_PER_34XX_SIZE SZ_1M 165 166#define L4_EMU_34XX_PHYS L4_EMU_34XX_BASE 167 /* 0x54000000 --> 0xfe800000 */ 168#define L4_EMU_34XX_VIRT (L4_EMU_34XX_PHYS + OMAP2_EMU_IO_OFFSET) 169#define L4_EMU_34XX_SIZE SZ_8M 170 171#define OMAP34XX_GPMC_PHYS OMAP34XX_GPMC_BASE 172 /* 0x6e000000 --> 0xfe000000 */ 173#define OMAP34XX_GPMC_VIRT (OMAP34XX_GPMC_PHYS + OMAP2_L3_IO_OFFSET) 174#define OMAP34XX_GPMC_SIZE SZ_1M 175 176#define OMAP343X_SMS_PHYS OMAP343X_SMS_BASE 177 /* 0x6c000000 --> 0xfc000000 */ 178#define OMAP343X_SMS_VIRT (OMAP343X_SMS_PHYS + OMAP2_L3_IO_OFFSET) 179#define OMAP343X_SMS_SIZE SZ_1M 180 181#define OMAP343X_SDRC_PHYS OMAP343X_SDRC_BASE 182 /* 0x6D000000 --> 0xfd000000 */ 183#define OMAP343X_SDRC_VIRT (OMAP343X_SDRC_PHYS + OMAP2_L3_IO_OFFSET) 184#define OMAP343X_SDRC_SIZE SZ_1M 185 186/* 3430 IVA - currently unmapped */ 187 188/* 189 * ---------------------------------------------------------------------------- 190 * Omap4 specific IO mapping 191 * ---------------------------------------------------------------------------- 192 */ 193 194/* We map both L3 and L4 on OMAP4 */ 195#define L3_44XX_PHYS L3_44XX_BASE /* 0x44000000 --> 0xf8000000 */ 196#define L3_44XX_VIRT (L3_44XX_PHYS + OMAP4_L3_IO_OFFSET) 197#define L3_44XX_SIZE SZ_1M 198 199#define L4_44XX_PHYS L4_44XX_BASE /* 0x4a000000 --> 0xfc000000 */ 200#define L4_44XX_VIRT (L4_44XX_PHYS + OMAP2_L4_IO_OFFSET) 201#define L4_44XX_SIZE SZ_4M 202 203#define L4_PER_44XX_PHYS L4_PER_44XX_BASE 204 /* 0x48000000 --> 0xfa000000 */ 205#define L4_PER_44XX_VIRT (L4_PER_44XX_PHYS + OMAP2_L4_IO_OFFSET) 206#define L4_PER_44XX_SIZE SZ_4M 207 208#define L4_ABE_44XX_PHYS L4_ABE_44XX_BASE 209 /* 0x49000000 --> 0xfb000000 */ 210#define L4_ABE_44XX_VIRT (L4_ABE_44XX_PHYS + OMAP2_L4_IO_OFFSET) 211#define L4_ABE_44XX_SIZE SZ_1M 212 213#define L4_EMU_44XX_PHYS L4_EMU_44XX_BASE 214 /* 0x54000000 --> 0xfe800000 */ 215#define L4_EMU_44XX_VIRT (L4_EMU_44XX_PHYS + OMAP2_EMU_IO_OFFSET) 216#define L4_EMU_44XX_SIZE SZ_8M 217 218#define OMAP44XX_GPMC_PHYS OMAP44XX_GPMC_BASE 219 /* 0x50000000 --> 0xf9000000 */ 220#define OMAP44XX_GPMC_VIRT (OMAP44XX_GPMC_PHYS + OMAP4_GPMC_IO_OFFSET) 221#define OMAP44XX_GPMC_SIZE SZ_1M 222 223 224#define OMAP44XX_EMIF1_PHYS OMAP44XX_EMIF1_BASE 225 /* 0x4c000000 --> 0xfd100000 */ 226#define OMAP44XX_EMIF1_VIRT (OMAP44XX_EMIF1_PHYS + OMAP4_L3_PER_IO_OFFSET) 227#define OMAP44XX_EMIF1_SIZE SZ_1M 228 229#define OMAP44XX_EMIF2_PHYS OMAP44XX_EMIF2_BASE 230 /* 0x4d000000 --> 0xfd200000 */ 231#define OMAP44XX_EMIF2_VIRT (OMAP44XX_EMIF2_PHYS + OMAP4_L3_PER_IO_OFFSET) 232#define OMAP44XX_EMIF2_SIZE SZ_1M 233 234#define OMAP44XX_DMM_PHYS OMAP44XX_DMM_BASE 235 /* 0x4e000000 --> 0xfd300000 */ 236#define OMAP44XX_DMM_VIRT (OMAP44XX_DMM_PHYS + OMAP4_L3_PER_IO_OFFSET) 237#define OMAP44XX_DMM_SIZE SZ_1M 238/* 239 * ---------------------------------------------------------------------------- 240 * Omap specific register access 241 * ---------------------------------------------------------------------------- 242 */ 243 244#ifndef __ASSEMBLER__ 245 246/* 247 * NOTE: Please use ioremap + __raw_read/write where possible instead of these 248 */ 249 250extern u8 omap_readb(u32 pa); 251extern u16 omap_readw(u32 pa); 252extern u32 omap_readl(u32 pa); 253extern void omap_writeb(u8 v, u32 pa); 254extern void omap_writew(u16 v, u32 pa); 255extern void omap_writel(u32 v, u32 pa); 256 257struct omap_sdrc_params; 258 259extern void omap1_map_common_io(void); 260extern void omap1_init_common_hw(void); 261 262#ifdef CONFIG_ARCH_OMAP2420 263extern void omap242x_map_common_io(void); 264#else 265static inline void omap242x_map_common_io(void) 266{ 267} 268#endif 269 270#ifdef CONFIG_ARCH_OMAP2430 271extern void omap243x_map_common_io(void); 272#else 273static inline void omap243x_map_common_io(void) 274{ 275} 276#endif 277 278#ifdef CONFIG_ARCH_OMAP3 279extern void omap34xx_map_common_io(void); 280#else 281static inline void omap34xx_map_common_io(void) 282{ 283} 284#endif 285 286#ifdef CONFIG_ARCH_OMAP4 287extern void omap44xx_map_common_io(void); 288#else 289static inline void omap44xx_map_common_io(void) 290{ 291} 292#endif 293 294extern void omap2_init_common_hw(struct omap_sdrc_params *sdrc_cs0, 295 struct omap_sdrc_params *sdrc_cs1); 296 297#define __arch_ioremap(p,s,t) omap_ioremap(p,s,t) 298#define __arch_iounmap(v) omap_iounmap(v) 299 300void __iomem *omap_ioremap(unsigned long phys, size_t size, unsigned int type); 301void omap_iounmap(volatile void __iomem *addr); 302 303#endif 304 305#endif 306