1/* 2 * linux/arch/arm/plat-omap/gpio.c 3 * 4 * Support functions for OMAP GPIO 5 * 6 * Copyright (C) 2003-2005 Nokia Corporation 7 * Written by Juha Yrj��l�� <juha.yrjola@nokia.com> 8 * 9 * Copyright (C) 2009 Texas Instruments 10 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com> 11 * 12 * This program is free software; you can redistribute it and/or modify 13 * it under the terms of the GNU General Public License version 2 as 14 * published by the Free Software Foundation. 15 */ 16 17#include <linux/init.h> 18#include <linux/module.h> 19#include <linux/interrupt.h> 20#include <linux/sysdev.h> 21#include <linux/err.h> 22#include <linux/clk.h> 23#include <linux/io.h> 24 25#include <mach/hardware.h> 26#include <asm/irq.h> 27#include <mach/irqs.h> 28#include <mach/gpio.h> 29#include <asm/mach/irq.h> 30#include <plat/powerdomain.h> 31 32/* 33 * OMAP1510 GPIO registers 34 */ 35#define OMAP1510_GPIO_BASE 0xfffce000 36#define OMAP1510_GPIO_DATA_INPUT 0x00 37#define OMAP1510_GPIO_DATA_OUTPUT 0x04 38#define OMAP1510_GPIO_DIR_CONTROL 0x08 39#define OMAP1510_GPIO_INT_CONTROL 0x0c 40#define OMAP1510_GPIO_INT_MASK 0x10 41#define OMAP1510_GPIO_INT_STATUS 0x14 42#define OMAP1510_GPIO_PIN_CONTROL 0x18 43 44#define OMAP1510_IH_GPIO_BASE 64 45 46/* 47 * OMAP1610 specific GPIO registers 48 */ 49#define OMAP1610_GPIO1_BASE 0xfffbe400 50#define OMAP1610_GPIO2_BASE 0xfffbec00 51#define OMAP1610_GPIO3_BASE 0xfffbb400 52#define OMAP1610_GPIO4_BASE 0xfffbbc00 53#define OMAP1610_GPIO_REVISION 0x0000 54#define OMAP1610_GPIO_SYSCONFIG 0x0010 55#define OMAP1610_GPIO_SYSSTATUS 0x0014 56#define OMAP1610_GPIO_IRQSTATUS1 0x0018 57#define OMAP1610_GPIO_IRQENABLE1 0x001c 58#define OMAP1610_GPIO_WAKEUPENABLE 0x0028 59#define OMAP1610_GPIO_DATAIN 0x002c 60#define OMAP1610_GPIO_DATAOUT 0x0030 61#define OMAP1610_GPIO_DIRECTION 0x0034 62#define OMAP1610_GPIO_EDGE_CTRL1 0x0038 63#define OMAP1610_GPIO_EDGE_CTRL2 0x003c 64#define OMAP1610_GPIO_CLEAR_IRQENABLE1 0x009c 65#define OMAP1610_GPIO_CLEAR_WAKEUPENA 0x00a8 66#define OMAP1610_GPIO_CLEAR_DATAOUT 0x00b0 67#define OMAP1610_GPIO_SET_IRQENABLE1 0x00dc 68#define OMAP1610_GPIO_SET_WAKEUPENA 0x00e8 69#define OMAP1610_GPIO_SET_DATAOUT 0x00f0 70 71/* 72 * OMAP7XX specific GPIO registers 73 */ 74#define OMAP7XX_GPIO1_BASE 0xfffbc000 75#define OMAP7XX_GPIO2_BASE 0xfffbc800 76#define OMAP7XX_GPIO3_BASE 0xfffbd000 77#define OMAP7XX_GPIO4_BASE 0xfffbd800 78#define OMAP7XX_GPIO5_BASE 0xfffbe000 79#define OMAP7XX_GPIO6_BASE 0xfffbe800 80#define OMAP7XX_GPIO_DATA_INPUT 0x00 81#define OMAP7XX_GPIO_DATA_OUTPUT 0x04 82#define OMAP7XX_GPIO_DIR_CONTROL 0x08 83#define OMAP7XX_GPIO_INT_CONTROL 0x0c 84#define OMAP7XX_GPIO_INT_MASK 0x10 85#define OMAP7XX_GPIO_INT_STATUS 0x14 86 87#define OMAP1_MPUIO_VBASE OMAP1_MPUIO_BASE 88 89/* 90 * omap24xx specific GPIO registers 91 */ 92#define OMAP242X_GPIO1_BASE 0x48018000 93#define OMAP242X_GPIO2_BASE 0x4801a000 94#define OMAP242X_GPIO3_BASE 0x4801c000 95#define OMAP242X_GPIO4_BASE 0x4801e000 96 97#define OMAP243X_GPIO1_BASE 0x4900C000 98#define OMAP243X_GPIO2_BASE 0x4900E000 99#define OMAP243X_GPIO3_BASE 0x49010000 100#define OMAP243X_GPIO4_BASE 0x49012000 101#define OMAP243X_GPIO5_BASE 0x480B6000 102 103#define OMAP24XX_GPIO_REVISION 0x0000 104#define OMAP24XX_GPIO_SYSCONFIG 0x0010 105#define OMAP24XX_GPIO_SYSSTATUS 0x0014 106#define OMAP24XX_GPIO_IRQSTATUS1 0x0018 107#define OMAP24XX_GPIO_IRQSTATUS2 0x0028 108#define OMAP24XX_GPIO_IRQENABLE2 0x002c 109#define OMAP24XX_GPIO_IRQENABLE1 0x001c 110#define OMAP24XX_GPIO_WAKE_EN 0x0020 111#define OMAP24XX_GPIO_CTRL 0x0030 112#define OMAP24XX_GPIO_OE 0x0034 113#define OMAP24XX_GPIO_DATAIN 0x0038 114#define OMAP24XX_GPIO_DATAOUT 0x003c 115#define OMAP24XX_GPIO_LEVELDETECT0 0x0040 116#define OMAP24XX_GPIO_LEVELDETECT1 0x0044 117#define OMAP24XX_GPIO_RISINGDETECT 0x0048 118#define OMAP24XX_GPIO_FALLINGDETECT 0x004c 119#define OMAP24XX_GPIO_DEBOUNCE_EN 0x0050 120#define OMAP24XX_GPIO_DEBOUNCE_VAL 0x0054 121#define OMAP24XX_GPIO_CLEARIRQENABLE1 0x0060 122#define OMAP24XX_GPIO_SETIRQENABLE1 0x0064 123#define OMAP24XX_GPIO_CLEARWKUENA 0x0080 124#define OMAP24XX_GPIO_SETWKUENA 0x0084 125#define OMAP24XX_GPIO_CLEARDATAOUT 0x0090 126#define OMAP24XX_GPIO_SETDATAOUT 0x0094 127 128#define OMAP4_GPIO_REVISION 0x0000 129#define OMAP4_GPIO_SYSCONFIG 0x0010 130#define OMAP4_GPIO_EOI 0x0020 131#define OMAP4_GPIO_IRQSTATUSRAW0 0x0024 132#define OMAP4_GPIO_IRQSTATUSRAW1 0x0028 133#define OMAP4_GPIO_IRQSTATUS0 0x002c 134#define OMAP4_GPIO_IRQSTATUS1 0x0030 135#define OMAP4_GPIO_IRQSTATUSSET0 0x0034 136#define OMAP4_GPIO_IRQSTATUSSET1 0x0038 137#define OMAP4_GPIO_IRQSTATUSCLR0 0x003c 138#define OMAP4_GPIO_IRQSTATUSCLR1 0x0040 139#define OMAP4_GPIO_IRQWAKEN0 0x0044 140#define OMAP4_GPIO_IRQWAKEN1 0x0048 141#define OMAP4_GPIO_SYSSTATUS 0x0114 142#define OMAP4_GPIO_IRQENABLE1 0x011c 143#define OMAP4_GPIO_WAKE_EN 0x0120 144#define OMAP4_GPIO_IRQSTATUS2 0x0128 145#define OMAP4_GPIO_IRQENABLE2 0x012c 146#define OMAP4_GPIO_CTRL 0x0130 147#define OMAP4_GPIO_OE 0x0134 148#define OMAP4_GPIO_DATAIN 0x0138 149#define OMAP4_GPIO_DATAOUT 0x013c 150#define OMAP4_GPIO_LEVELDETECT0 0x0140 151#define OMAP4_GPIO_LEVELDETECT1 0x0144 152#define OMAP4_GPIO_RISINGDETECT 0x0148 153#define OMAP4_GPIO_FALLINGDETECT 0x014c 154#define OMAP4_GPIO_DEBOUNCENABLE 0x0150 155#define OMAP4_GPIO_DEBOUNCINGTIME 0x0154 156#define OMAP4_GPIO_CLEARIRQENABLE1 0x0160 157#define OMAP4_GPIO_SETIRQENABLE1 0x0164 158#define OMAP4_GPIO_CLEARWKUENA 0x0180 159#define OMAP4_GPIO_SETWKUENA 0x0184 160#define OMAP4_GPIO_CLEARDATAOUT 0x0190 161#define OMAP4_GPIO_SETDATAOUT 0x0194 162/* 163 * omap34xx specific GPIO registers 164 */ 165 166#define OMAP34XX_GPIO1_BASE 0x48310000 167#define OMAP34XX_GPIO2_BASE 0x49050000 168#define OMAP34XX_GPIO3_BASE 0x49052000 169#define OMAP34XX_GPIO4_BASE 0x49054000 170#define OMAP34XX_GPIO5_BASE 0x49056000 171#define OMAP34XX_GPIO6_BASE 0x49058000 172 173/* 174 * OMAP44XX specific GPIO registers 175 */ 176#define OMAP44XX_GPIO1_BASE 0x4a310000 177#define OMAP44XX_GPIO2_BASE 0x48055000 178#define OMAP44XX_GPIO3_BASE 0x48057000 179#define OMAP44XX_GPIO4_BASE 0x48059000 180#define OMAP44XX_GPIO5_BASE 0x4805B000 181#define OMAP44XX_GPIO6_BASE 0x4805D000 182 183struct gpio_bank { 184 unsigned long pbase; 185 void __iomem *base; 186 u16 irq; 187 u16 virtual_irq_start; 188 int method; 189#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS) 190 u32 suspend_wakeup; 191 u32 saved_wakeup; 192#endif 193#ifdef CONFIG_ARCH_OMAP2PLUS 194 u32 non_wakeup_gpios; 195 u32 enabled_non_wakeup_gpios; 196 197 u32 saved_datain; 198 u32 saved_fallingdetect; 199 u32 saved_risingdetect; 200#endif 201 u32 level_mask; 202 u32 toggle_mask; 203 spinlock_t lock; 204 struct gpio_chip chip; 205 struct clk *dbck; 206 u32 mod_usage; 207 u32 dbck_enable_mask; 208}; 209 210#define METHOD_MPUIO 0 211#define METHOD_GPIO_1510 1 212#define METHOD_GPIO_1610 2 213#define METHOD_GPIO_7XX 3 214#define METHOD_GPIO_24XX 5 215#define METHOD_GPIO_44XX 6 216 217#ifdef CONFIG_ARCH_OMAP16XX 218static struct gpio_bank gpio_bank_1610[5] = { 219 { OMAP1_MPUIO_VBASE, NULL, INT_MPUIO, IH_MPUIO_BASE, 220 METHOD_MPUIO }, 221 { OMAP1610_GPIO1_BASE, NULL, INT_GPIO_BANK1, IH_GPIO_BASE, 222 METHOD_GPIO_1610 }, 223 { OMAP1610_GPIO2_BASE, NULL, INT_1610_GPIO_BANK2, IH_GPIO_BASE + 16, 224 METHOD_GPIO_1610 }, 225 { OMAP1610_GPIO3_BASE, NULL, INT_1610_GPIO_BANK3, IH_GPIO_BASE + 32, 226 METHOD_GPIO_1610 }, 227 { OMAP1610_GPIO4_BASE, NULL, INT_1610_GPIO_BANK4, IH_GPIO_BASE + 48, 228 METHOD_GPIO_1610 }, 229}; 230#endif 231 232#ifdef CONFIG_ARCH_OMAP15XX 233static struct gpio_bank gpio_bank_1510[2] = { 234 { OMAP1_MPUIO_VBASE, NULL, INT_MPUIO, IH_MPUIO_BASE, 235 METHOD_MPUIO }, 236 { OMAP1510_GPIO_BASE, NULL, INT_GPIO_BANK1, IH_GPIO_BASE, 237 METHOD_GPIO_1510 } 238}; 239#endif 240 241#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850) 242static struct gpio_bank gpio_bank_7xx[7] = { 243 { OMAP1_MPUIO_VBASE, NULL, INT_7XX_MPUIO, IH_MPUIO_BASE, 244 METHOD_MPUIO }, 245 { OMAP7XX_GPIO1_BASE, NULL, INT_7XX_GPIO_BANK1, IH_GPIO_BASE, 246 METHOD_GPIO_7XX }, 247 { OMAP7XX_GPIO2_BASE, NULL, INT_7XX_GPIO_BANK2, IH_GPIO_BASE + 32, 248 METHOD_GPIO_7XX }, 249 { OMAP7XX_GPIO3_BASE, NULL, INT_7XX_GPIO_BANK3, IH_GPIO_BASE + 64, 250 METHOD_GPIO_7XX }, 251 { OMAP7XX_GPIO4_BASE, NULL, INT_7XX_GPIO_BANK4, IH_GPIO_BASE + 96, 252 METHOD_GPIO_7XX }, 253 { OMAP7XX_GPIO5_BASE, NULL, INT_7XX_GPIO_BANK5, IH_GPIO_BASE + 128, 254 METHOD_GPIO_7XX }, 255 { OMAP7XX_GPIO6_BASE, NULL, INT_7XX_GPIO_BANK6, IH_GPIO_BASE + 160, 256 METHOD_GPIO_7XX }, 257}; 258#endif 259 260#ifdef CONFIG_ARCH_OMAP2 261 262static struct gpio_bank gpio_bank_242x[4] = { 263 { OMAP242X_GPIO1_BASE, NULL, INT_24XX_GPIO_BANK1, IH_GPIO_BASE, 264 METHOD_GPIO_24XX }, 265 { OMAP242X_GPIO2_BASE, NULL, INT_24XX_GPIO_BANK2, IH_GPIO_BASE + 32, 266 METHOD_GPIO_24XX }, 267 { OMAP242X_GPIO3_BASE, NULL, INT_24XX_GPIO_BANK3, IH_GPIO_BASE + 64, 268 METHOD_GPIO_24XX }, 269 { OMAP242X_GPIO4_BASE, NULL, INT_24XX_GPIO_BANK4, IH_GPIO_BASE + 96, 270 METHOD_GPIO_24XX }, 271}; 272 273static struct gpio_bank gpio_bank_243x[5] = { 274 { OMAP243X_GPIO1_BASE, NULL, INT_24XX_GPIO_BANK1, IH_GPIO_BASE, 275 METHOD_GPIO_24XX }, 276 { OMAP243X_GPIO2_BASE, NULL, INT_24XX_GPIO_BANK2, IH_GPIO_BASE + 32, 277 METHOD_GPIO_24XX }, 278 { OMAP243X_GPIO3_BASE, NULL, INT_24XX_GPIO_BANK3, IH_GPIO_BASE + 64, 279 METHOD_GPIO_24XX }, 280 { OMAP243X_GPIO4_BASE, NULL, INT_24XX_GPIO_BANK4, IH_GPIO_BASE + 96, 281 METHOD_GPIO_24XX }, 282 { OMAP243X_GPIO5_BASE, NULL, INT_24XX_GPIO_BANK5, IH_GPIO_BASE + 128, 283 METHOD_GPIO_24XX }, 284}; 285 286#endif 287 288#ifdef CONFIG_ARCH_OMAP3 289static struct gpio_bank gpio_bank_34xx[6] = { 290 { OMAP34XX_GPIO1_BASE, NULL, INT_34XX_GPIO_BANK1, IH_GPIO_BASE, 291 METHOD_GPIO_24XX }, 292 { OMAP34XX_GPIO2_BASE, NULL, INT_34XX_GPIO_BANK2, IH_GPIO_BASE + 32, 293 METHOD_GPIO_24XX }, 294 { OMAP34XX_GPIO3_BASE, NULL, INT_34XX_GPIO_BANK3, IH_GPIO_BASE + 64, 295 METHOD_GPIO_24XX }, 296 { OMAP34XX_GPIO4_BASE, NULL, INT_34XX_GPIO_BANK4, IH_GPIO_BASE + 96, 297 METHOD_GPIO_24XX }, 298 { OMAP34XX_GPIO5_BASE, NULL, INT_34XX_GPIO_BANK5, IH_GPIO_BASE + 128, 299 METHOD_GPIO_24XX }, 300 { OMAP34XX_GPIO6_BASE, NULL, INT_34XX_GPIO_BANK6, IH_GPIO_BASE + 160, 301 METHOD_GPIO_24XX }, 302}; 303 304struct omap3_gpio_regs { 305 u32 sysconfig; 306 u32 irqenable1; 307 u32 irqenable2; 308 u32 wake_en; 309 u32 ctrl; 310 u32 oe; 311 u32 leveldetect0; 312 u32 leveldetect1; 313 u32 risingdetect; 314 u32 fallingdetect; 315 u32 dataout; 316}; 317 318static struct omap3_gpio_regs gpio_context[OMAP34XX_NR_GPIOS]; 319#endif 320 321#ifdef CONFIG_ARCH_OMAP4 322static struct gpio_bank gpio_bank_44xx[6] = { 323 { OMAP44XX_GPIO1_BASE, NULL, OMAP44XX_IRQ_GPIO1, IH_GPIO_BASE, 324 METHOD_GPIO_44XX }, 325 { OMAP44XX_GPIO2_BASE, NULL, OMAP44XX_IRQ_GPIO2, IH_GPIO_BASE + 32, 326 METHOD_GPIO_44XX }, 327 { OMAP44XX_GPIO3_BASE, NULL, OMAP44XX_IRQ_GPIO3, IH_GPIO_BASE + 64, 328 METHOD_GPIO_44XX }, 329 { OMAP44XX_GPIO4_BASE, NULL, OMAP44XX_IRQ_GPIO4, IH_GPIO_BASE + 96, 330 METHOD_GPIO_44XX }, 331 { OMAP44XX_GPIO5_BASE, NULL, OMAP44XX_IRQ_GPIO5, IH_GPIO_BASE + 128, 332 METHOD_GPIO_44XX }, 333 { OMAP44XX_GPIO6_BASE, NULL, OMAP44XX_IRQ_GPIO6, IH_GPIO_BASE + 160, 334 METHOD_GPIO_44XX }, 335}; 336 337#endif 338 339static struct gpio_bank *gpio_bank; 340static int gpio_bank_count; 341 342static inline struct gpio_bank *get_gpio_bank(int gpio) 343{ 344 if (cpu_is_omap15xx()) { 345 if (OMAP_GPIO_IS_MPUIO(gpio)) 346 return &gpio_bank[0]; 347 return &gpio_bank[1]; 348 } 349 if (cpu_is_omap16xx()) { 350 if (OMAP_GPIO_IS_MPUIO(gpio)) 351 return &gpio_bank[0]; 352 return &gpio_bank[1 + (gpio >> 4)]; 353 } 354 if (cpu_is_omap7xx()) { 355 if (OMAP_GPIO_IS_MPUIO(gpio)) 356 return &gpio_bank[0]; 357 return &gpio_bank[1 + (gpio >> 5)]; 358 } 359 if (cpu_is_omap24xx()) 360 return &gpio_bank[gpio >> 5]; 361 if (cpu_is_omap34xx() || cpu_is_omap44xx()) 362 return &gpio_bank[gpio >> 5]; 363 BUG(); 364 return NULL; 365} 366 367static inline int get_gpio_index(int gpio) 368{ 369 if (cpu_is_omap7xx()) 370 return gpio & 0x1f; 371 if (cpu_is_omap24xx()) 372 return gpio & 0x1f; 373 if (cpu_is_omap34xx() || cpu_is_omap44xx()) 374 return gpio & 0x1f; 375 return gpio & 0x0f; 376} 377 378static inline int gpio_valid(int gpio) 379{ 380 if (gpio < 0) 381 return -1; 382 if (cpu_class_is_omap1() && OMAP_GPIO_IS_MPUIO(gpio)) { 383 if (gpio >= OMAP_MAX_GPIO_LINES + 16) 384 return -1; 385 return 0; 386 } 387 if (cpu_is_omap15xx() && gpio < 16) 388 return 0; 389 if ((cpu_is_omap16xx()) && gpio < 64) 390 return 0; 391 if (cpu_is_omap7xx() && gpio < 192) 392 return 0; 393 if (cpu_is_omap2420() && gpio < 128) 394 return 0; 395 if (cpu_is_omap2430() && gpio < 160) 396 return 0; 397 if ((cpu_is_omap34xx() || cpu_is_omap44xx()) && gpio < 192) 398 return 0; 399 return -1; 400} 401 402static int check_gpio(int gpio) 403{ 404 if (unlikely(gpio_valid(gpio) < 0)) { 405 printk(KERN_ERR "omap-gpio: invalid GPIO %d\n", gpio); 406 dump_stack(); 407 return -1; 408 } 409 return 0; 410} 411 412static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input) 413{ 414 void __iomem *reg = bank->base; 415 u32 l; 416 417 switch (bank->method) { 418#ifdef CONFIG_ARCH_OMAP1 419 case METHOD_MPUIO: 420 reg += OMAP_MPUIO_IO_CNTL; 421 break; 422#endif 423#ifdef CONFIG_ARCH_OMAP15XX 424 case METHOD_GPIO_1510: 425 reg += OMAP1510_GPIO_DIR_CONTROL; 426 break; 427#endif 428#ifdef CONFIG_ARCH_OMAP16XX 429 case METHOD_GPIO_1610: 430 reg += OMAP1610_GPIO_DIRECTION; 431 break; 432#endif 433#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850) 434 case METHOD_GPIO_7XX: 435 reg += OMAP7XX_GPIO_DIR_CONTROL; 436 break; 437#endif 438#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) 439 case METHOD_GPIO_24XX: 440 reg += OMAP24XX_GPIO_OE; 441 break; 442#endif 443#if defined(CONFIG_ARCH_OMAP4) 444 case METHOD_GPIO_44XX: 445 reg += OMAP4_GPIO_OE; 446 break; 447#endif 448 default: 449 WARN_ON(1); 450 return; 451 } 452 l = __raw_readl(reg); 453 if (is_input) 454 l |= 1 << gpio; 455 else 456 l &= ~(1 << gpio); 457 __raw_writel(l, reg); 458} 459 460static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable) 461{ 462 void __iomem *reg = bank->base; 463 u32 l = 0; 464 465 switch (bank->method) { 466#ifdef CONFIG_ARCH_OMAP1 467 case METHOD_MPUIO: 468 reg += OMAP_MPUIO_OUTPUT; 469 l = __raw_readl(reg); 470 if (enable) 471 l |= 1 << gpio; 472 else 473 l &= ~(1 << gpio); 474 break; 475#endif 476#ifdef CONFIG_ARCH_OMAP15XX 477 case METHOD_GPIO_1510: 478 reg += OMAP1510_GPIO_DATA_OUTPUT; 479 l = __raw_readl(reg); 480 if (enable) 481 l |= 1 << gpio; 482 else 483 l &= ~(1 << gpio); 484 break; 485#endif 486#ifdef CONFIG_ARCH_OMAP16XX 487 case METHOD_GPIO_1610: 488 if (enable) 489 reg += OMAP1610_GPIO_SET_DATAOUT; 490 else 491 reg += OMAP1610_GPIO_CLEAR_DATAOUT; 492 l = 1 << gpio; 493 break; 494#endif 495#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850) 496 case METHOD_GPIO_7XX: 497 reg += OMAP7XX_GPIO_DATA_OUTPUT; 498 l = __raw_readl(reg); 499 if (enable) 500 l |= 1 << gpio; 501 else 502 l &= ~(1 << gpio); 503 break; 504#endif 505#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) 506 case METHOD_GPIO_24XX: 507 if (enable) 508 reg += OMAP24XX_GPIO_SETDATAOUT; 509 else 510 reg += OMAP24XX_GPIO_CLEARDATAOUT; 511 l = 1 << gpio; 512 break; 513#endif 514#ifdef CONFIG_ARCH_OMAP4 515 case METHOD_GPIO_44XX: 516 if (enable) 517 reg += OMAP4_GPIO_SETDATAOUT; 518 else 519 reg += OMAP4_GPIO_CLEARDATAOUT; 520 l = 1 << gpio; 521 break; 522#endif 523 default: 524 WARN_ON(1); 525 return; 526 } 527 __raw_writel(l, reg); 528} 529 530static int _get_gpio_datain(struct gpio_bank *bank, int gpio) 531{ 532 void __iomem *reg; 533 534 if (check_gpio(gpio) < 0) 535 return -EINVAL; 536 reg = bank->base; 537 switch (bank->method) { 538#ifdef CONFIG_ARCH_OMAP1 539 case METHOD_MPUIO: 540 reg += OMAP_MPUIO_INPUT_LATCH; 541 break; 542#endif 543#ifdef CONFIG_ARCH_OMAP15XX 544 case METHOD_GPIO_1510: 545 reg += OMAP1510_GPIO_DATA_INPUT; 546 break; 547#endif 548#ifdef CONFIG_ARCH_OMAP16XX 549 case METHOD_GPIO_1610: 550 reg += OMAP1610_GPIO_DATAIN; 551 break; 552#endif 553#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850) 554 case METHOD_GPIO_7XX: 555 reg += OMAP7XX_GPIO_DATA_INPUT; 556 break; 557#endif 558#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) 559 case METHOD_GPIO_24XX: 560 reg += OMAP24XX_GPIO_DATAIN; 561 break; 562#endif 563#ifdef CONFIG_ARCH_OMAP4 564 case METHOD_GPIO_44XX: 565 reg += OMAP4_GPIO_DATAIN; 566 break; 567#endif 568 default: 569 return -EINVAL; 570 } 571 return (__raw_readl(reg) 572 & (1 << get_gpio_index(gpio))) != 0; 573} 574 575static int _get_gpio_dataout(struct gpio_bank *bank, int gpio) 576{ 577 void __iomem *reg; 578 579 if (check_gpio(gpio) < 0) 580 return -EINVAL; 581 reg = bank->base; 582 583 switch (bank->method) { 584#ifdef CONFIG_ARCH_OMAP1 585 case METHOD_MPUIO: 586 reg += OMAP_MPUIO_OUTPUT; 587 break; 588#endif 589#ifdef CONFIG_ARCH_OMAP15XX 590 case METHOD_GPIO_1510: 591 reg += OMAP1510_GPIO_DATA_OUTPUT; 592 break; 593#endif 594#ifdef CONFIG_ARCH_OMAP16XX 595 case METHOD_GPIO_1610: 596 reg += OMAP1610_GPIO_DATAOUT; 597 break; 598#endif 599#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850) 600 case METHOD_GPIO_7XX: 601 reg += OMAP7XX_GPIO_DATA_OUTPUT; 602 break; 603#endif 604#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) 605 case METHOD_GPIO_24XX: 606 reg += OMAP24XX_GPIO_DATAOUT; 607 break; 608#endif 609#ifdef CONFIG_ARCH_OMAP4 610 case METHOD_GPIO_44XX: 611 reg += OMAP4_GPIO_DATAOUT; 612 break; 613#endif 614 default: 615 return -EINVAL; 616 } 617 618 return (__raw_readl(reg) & (1 << get_gpio_index(gpio))) != 0; 619} 620 621#define MOD_REG_BIT(reg, bit_mask, set) \ 622do { \ 623 int l = __raw_readl(base + reg); \ 624 if (set) l |= bit_mask; \ 625 else l &= ~bit_mask; \ 626 __raw_writel(l, base + reg); \ 627} while(0) 628 629/** 630 * _set_gpio_debounce - low level gpio debounce time 631 * @bank: the gpio bank we're acting upon 632 * @gpio: the gpio number on this @gpio 633 * @debounce: debounce time to use 634 * 635 * OMAP's debounce time is in 31us steps so we need 636 * to convert and round up to the closest unit. 637 */ 638static void _set_gpio_debounce(struct gpio_bank *bank, unsigned gpio, 639 unsigned debounce) 640{ 641 void __iomem *reg = bank->base; 642 u32 val; 643 u32 l; 644 645 if (debounce < 32) 646 debounce = 0x01; 647 else if (debounce > 7936) 648 debounce = 0xff; 649 else 650 debounce = (debounce / 0x1f) - 1; 651 652 l = 1 << get_gpio_index(gpio); 653 654 if (cpu_is_omap44xx()) 655 reg += OMAP4_GPIO_DEBOUNCINGTIME; 656 else 657 reg += OMAP24XX_GPIO_DEBOUNCE_VAL; 658 659 __raw_writel(debounce, reg); 660 661 reg = bank->base; 662 if (cpu_is_omap44xx()) 663 reg += OMAP4_GPIO_DEBOUNCENABLE; 664 else 665 reg += OMAP24XX_GPIO_DEBOUNCE_EN; 666 667 val = __raw_readl(reg); 668 669 if (debounce) { 670 val |= l; 671 if (cpu_is_omap34xx() || cpu_is_omap44xx()) 672 clk_enable(bank->dbck); 673 } else { 674 val &= ~l; 675 if (cpu_is_omap34xx() || cpu_is_omap44xx()) 676 clk_disable(bank->dbck); 677 } 678 bank->dbck_enable_mask = val; 679 680 __raw_writel(val, reg); 681} 682 683#ifdef CONFIG_ARCH_OMAP2PLUS 684static inline void set_24xx_gpio_triggering(struct gpio_bank *bank, int gpio, 685 int trigger) 686{ 687 void __iomem *base = bank->base; 688 u32 gpio_bit = 1 << gpio; 689 u32 val; 690 691 if (cpu_is_omap44xx()) { 692 MOD_REG_BIT(OMAP4_GPIO_LEVELDETECT0, gpio_bit, 693 trigger & IRQ_TYPE_LEVEL_LOW); 694 MOD_REG_BIT(OMAP4_GPIO_LEVELDETECT1, gpio_bit, 695 trigger & IRQ_TYPE_LEVEL_HIGH); 696 MOD_REG_BIT(OMAP4_GPIO_RISINGDETECT, gpio_bit, 697 trigger & IRQ_TYPE_EDGE_RISING); 698 MOD_REG_BIT(OMAP4_GPIO_FALLINGDETECT, gpio_bit, 699 trigger & IRQ_TYPE_EDGE_FALLING); 700 } else { 701 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT0, gpio_bit, 702 trigger & IRQ_TYPE_LEVEL_LOW); 703 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT1, gpio_bit, 704 trigger & IRQ_TYPE_LEVEL_HIGH); 705 MOD_REG_BIT(OMAP24XX_GPIO_RISINGDETECT, gpio_bit, 706 trigger & IRQ_TYPE_EDGE_RISING); 707 MOD_REG_BIT(OMAP24XX_GPIO_FALLINGDETECT, gpio_bit, 708 trigger & IRQ_TYPE_EDGE_FALLING); 709 } 710 if (likely(!(bank->non_wakeup_gpios & gpio_bit))) { 711 if (cpu_is_omap44xx()) { 712 if (trigger != 0) 713 __raw_writel(1 << gpio, bank->base+ 714 OMAP4_GPIO_IRQWAKEN0); 715 else { 716 val = __raw_readl(bank->base + 717 OMAP4_GPIO_IRQWAKEN0); 718 __raw_writel(val & (~(1 << gpio)), bank->base + 719 OMAP4_GPIO_IRQWAKEN0); 720 } 721 } else { 722 /* 723 * GPIO wakeup request can only be generated on edge 724 * transitions 725 */ 726 if (trigger & IRQ_TYPE_EDGE_BOTH) 727 __raw_writel(1 << gpio, bank->base 728 + OMAP24XX_GPIO_SETWKUENA); 729 else 730 __raw_writel(1 << gpio, bank->base 731 + OMAP24XX_GPIO_CLEARWKUENA); 732 } 733 } 734 /* This part needs to be executed always for OMAP34xx */ 735 if (cpu_is_omap34xx() || (bank->non_wakeup_gpios & gpio_bit)) { 736 /* 737 * Log the edge gpio and manually trigger the IRQ 738 * after resume if the input level changes 739 * to avoid irq lost during PER RET/OFF mode 740 * Applies for omap2 non-wakeup gpio and all omap3 gpios 741 */ 742 if (trigger & IRQ_TYPE_EDGE_BOTH) 743 bank->enabled_non_wakeup_gpios |= gpio_bit; 744 else 745 bank->enabled_non_wakeup_gpios &= ~gpio_bit; 746 } 747 748 if (cpu_is_omap44xx()) { 749 bank->level_mask = 750 __raw_readl(bank->base + OMAP4_GPIO_LEVELDETECT0) | 751 __raw_readl(bank->base + OMAP4_GPIO_LEVELDETECT1); 752 } else { 753 bank->level_mask = 754 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0) | 755 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1); 756 } 757} 758#endif 759 760#ifdef CONFIG_ARCH_OMAP1 761/* 762 * This only applies to chips that can't do both rising and falling edge 763 * detection at once. For all other chips, this function is a noop. 764 */ 765static void _toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio) 766{ 767 void __iomem *reg = bank->base; 768 u32 l = 0; 769 770 switch (bank->method) { 771 case METHOD_MPUIO: 772 reg += OMAP_MPUIO_GPIO_INT_EDGE; 773 break; 774#ifdef CONFIG_ARCH_OMAP15XX 775 case METHOD_GPIO_1510: 776 reg += OMAP1510_GPIO_INT_CONTROL; 777 break; 778#endif 779#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850) 780 case METHOD_GPIO_7XX: 781 reg += OMAP7XX_GPIO_INT_CONTROL; 782 break; 783#endif 784 default: 785 return; 786 } 787 788 l = __raw_readl(reg); 789 if ((l >> gpio) & 1) 790 l &= ~(1 << gpio); 791 else 792 l |= 1 << gpio; 793 794 __raw_writel(l, reg); 795} 796#endif 797 798static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger) 799{ 800 void __iomem *reg = bank->base; 801 u32 l = 0; 802 803 switch (bank->method) { 804#ifdef CONFIG_ARCH_OMAP1 805 case METHOD_MPUIO: 806 reg += OMAP_MPUIO_GPIO_INT_EDGE; 807 l = __raw_readl(reg); 808 if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) 809 bank->toggle_mask |= 1 << gpio; 810 if (trigger & IRQ_TYPE_EDGE_RISING) 811 l |= 1 << gpio; 812 else if (trigger & IRQ_TYPE_EDGE_FALLING) 813 l &= ~(1 << gpio); 814 else 815 goto bad; 816 break; 817#endif 818#ifdef CONFIG_ARCH_OMAP15XX 819 case METHOD_GPIO_1510: 820 reg += OMAP1510_GPIO_INT_CONTROL; 821 l = __raw_readl(reg); 822 if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) 823 bank->toggle_mask |= 1 << gpio; 824 if (trigger & IRQ_TYPE_EDGE_RISING) 825 l |= 1 << gpio; 826 else if (trigger & IRQ_TYPE_EDGE_FALLING) 827 l &= ~(1 << gpio); 828 else 829 goto bad; 830 break; 831#endif 832#ifdef CONFIG_ARCH_OMAP16XX 833 case METHOD_GPIO_1610: 834 if (gpio & 0x08) 835 reg += OMAP1610_GPIO_EDGE_CTRL2; 836 else 837 reg += OMAP1610_GPIO_EDGE_CTRL1; 838 gpio &= 0x07; 839 l = __raw_readl(reg); 840 l &= ~(3 << (gpio << 1)); 841 if (trigger & IRQ_TYPE_EDGE_RISING) 842 l |= 2 << (gpio << 1); 843 if (trigger & IRQ_TYPE_EDGE_FALLING) 844 l |= 1 << (gpio << 1); 845 if (trigger) 846 /* Enable wake-up during idle for dynamic tick */ 847 __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_SET_WAKEUPENA); 848 else 849 __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA); 850 break; 851#endif 852#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850) 853 case METHOD_GPIO_7XX: 854 reg += OMAP7XX_GPIO_INT_CONTROL; 855 l = __raw_readl(reg); 856 if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) 857 bank->toggle_mask |= 1 << gpio; 858 if (trigger & IRQ_TYPE_EDGE_RISING) 859 l |= 1 << gpio; 860 else if (trigger & IRQ_TYPE_EDGE_FALLING) 861 l &= ~(1 << gpio); 862 else 863 goto bad; 864 break; 865#endif 866#ifdef CONFIG_ARCH_OMAP2PLUS 867 case METHOD_GPIO_24XX: 868 case METHOD_GPIO_44XX: 869 set_24xx_gpio_triggering(bank, gpio, trigger); 870 break; 871#endif 872 default: 873 goto bad; 874 } 875 __raw_writel(l, reg); 876 return 0; 877bad: 878 return -EINVAL; 879} 880 881static int gpio_irq_type(unsigned irq, unsigned type) 882{ 883 struct gpio_bank *bank; 884 unsigned gpio; 885 int retval; 886 unsigned long flags; 887 888 if (!cpu_class_is_omap2() && irq > IH_MPUIO_BASE) 889 gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE); 890 else 891 gpio = irq - IH_GPIO_BASE; 892 893 if (check_gpio(gpio) < 0) 894 return -EINVAL; 895 896 if (type & ~IRQ_TYPE_SENSE_MASK) 897 return -EINVAL; 898 899 /* OMAP1 allows only only edge triggering */ 900 if (!cpu_class_is_omap2() 901 && (type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH))) 902 return -EINVAL; 903 904 bank = get_irq_chip_data(irq); 905 spin_lock_irqsave(&bank->lock, flags); 906 retval = _set_gpio_triggering(bank, get_gpio_index(gpio), type); 907 if (retval == 0) { 908 irq_desc[irq].status &= ~IRQ_TYPE_SENSE_MASK; 909 irq_desc[irq].status |= type; 910 } 911 spin_unlock_irqrestore(&bank->lock, flags); 912 913 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH)) 914 __set_irq_handler_unlocked(irq, handle_level_irq); 915 else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) 916 __set_irq_handler_unlocked(irq, handle_edge_irq); 917 918 return retval; 919} 920 921static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask) 922{ 923 void __iomem *reg = bank->base; 924 925 switch (bank->method) { 926#ifdef CONFIG_ARCH_OMAP1 927 case METHOD_MPUIO: 928 /* MPUIO irqstatus is reset by reading the status register, 929 * so do nothing here */ 930 return; 931#endif 932#ifdef CONFIG_ARCH_OMAP15XX 933 case METHOD_GPIO_1510: 934 reg += OMAP1510_GPIO_INT_STATUS; 935 break; 936#endif 937#ifdef CONFIG_ARCH_OMAP16XX 938 case METHOD_GPIO_1610: 939 reg += OMAP1610_GPIO_IRQSTATUS1; 940 break; 941#endif 942#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850) 943 case METHOD_GPIO_7XX: 944 reg += OMAP7XX_GPIO_INT_STATUS; 945 break; 946#endif 947#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) 948 case METHOD_GPIO_24XX: 949 reg += OMAP24XX_GPIO_IRQSTATUS1; 950 break; 951#endif 952#if defined(CONFIG_ARCH_OMAP4) 953 case METHOD_GPIO_44XX: 954 reg += OMAP4_GPIO_IRQSTATUS0; 955 break; 956#endif 957 default: 958 WARN_ON(1); 959 return; 960 } 961 __raw_writel(gpio_mask, reg); 962 963 if (cpu_is_omap24xx() || cpu_is_omap34xx()) 964 reg = bank->base + OMAP24XX_GPIO_IRQSTATUS2; 965 else if (cpu_is_omap44xx()) 966 reg = bank->base + OMAP4_GPIO_IRQSTATUS1; 967 968 if (cpu_is_omap24xx() || cpu_is_omap34xx() || cpu_is_omap44xx()) { 969 __raw_writel(gpio_mask, reg); 970 971 /* Flush posted write for the irq status to avoid spurious interrupts */ 972 __raw_readl(reg); 973 } 974} 975 976static inline void _clear_gpio_irqstatus(struct gpio_bank *bank, int gpio) 977{ 978 _clear_gpio_irqbank(bank, 1 << get_gpio_index(gpio)); 979} 980 981static u32 _get_gpio_irqbank_mask(struct gpio_bank *bank) 982{ 983 void __iomem *reg = bank->base; 984 int inv = 0; 985 u32 l; 986 u32 mask; 987 988 switch (bank->method) { 989#ifdef CONFIG_ARCH_OMAP1 990 case METHOD_MPUIO: 991 reg += OMAP_MPUIO_GPIO_MASKIT; 992 mask = 0xffff; 993 inv = 1; 994 break; 995#endif 996#ifdef CONFIG_ARCH_OMAP15XX 997 case METHOD_GPIO_1510: 998 reg += OMAP1510_GPIO_INT_MASK; 999 mask = 0xffff; 1000 inv = 1; 1001 break; 1002#endif 1003#ifdef CONFIG_ARCH_OMAP16XX 1004 case METHOD_GPIO_1610: 1005 reg += OMAP1610_GPIO_IRQENABLE1; 1006 mask = 0xffff; 1007 break; 1008#endif 1009#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850) 1010 case METHOD_GPIO_7XX: 1011 reg += OMAP7XX_GPIO_INT_MASK; 1012 mask = 0xffffffff; 1013 inv = 1; 1014 break; 1015#endif 1016#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) 1017 case METHOD_GPIO_24XX: 1018 reg += OMAP24XX_GPIO_IRQENABLE1; 1019 mask = 0xffffffff; 1020 break; 1021#endif 1022#if defined(CONFIG_ARCH_OMAP4) 1023 case METHOD_GPIO_44XX: 1024 reg += OMAP4_GPIO_IRQSTATUSSET0; 1025 mask = 0xffffffff; 1026 break; 1027#endif 1028 default: 1029 WARN_ON(1); 1030 return 0; 1031 } 1032 1033 l = __raw_readl(reg); 1034 if (inv) 1035 l = ~l; 1036 l &= mask; 1037 return l; 1038} 1039 1040static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask, int enable) 1041{ 1042 void __iomem *reg = bank->base; 1043 u32 l; 1044 1045 switch (bank->method) { 1046#ifdef CONFIG_ARCH_OMAP1 1047 case METHOD_MPUIO: 1048 reg += OMAP_MPUIO_GPIO_MASKIT; 1049 l = __raw_readl(reg); 1050 if (enable) 1051 l &= ~(gpio_mask); 1052 else 1053 l |= gpio_mask; 1054 break; 1055#endif 1056#ifdef CONFIG_ARCH_OMAP15XX 1057 case METHOD_GPIO_1510: 1058 reg += OMAP1510_GPIO_INT_MASK; 1059 l = __raw_readl(reg); 1060 if (enable) 1061 l &= ~(gpio_mask); 1062 else 1063 l |= gpio_mask; 1064 break; 1065#endif 1066#ifdef CONFIG_ARCH_OMAP16XX 1067 case METHOD_GPIO_1610: 1068 if (enable) 1069 reg += OMAP1610_GPIO_SET_IRQENABLE1; 1070 else 1071 reg += OMAP1610_GPIO_CLEAR_IRQENABLE1; 1072 l = gpio_mask; 1073 break; 1074#endif 1075#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850) 1076 case METHOD_GPIO_7XX: 1077 reg += OMAP7XX_GPIO_INT_MASK; 1078 l = __raw_readl(reg); 1079 if (enable) 1080 l &= ~(gpio_mask); 1081 else 1082 l |= gpio_mask; 1083 break; 1084#endif 1085#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) 1086 case METHOD_GPIO_24XX: 1087 if (enable) 1088 reg += OMAP24XX_GPIO_SETIRQENABLE1; 1089 else 1090 reg += OMAP24XX_GPIO_CLEARIRQENABLE1; 1091 l = gpio_mask; 1092 break; 1093#endif 1094#ifdef CONFIG_ARCH_OMAP4 1095 case METHOD_GPIO_44XX: 1096 if (enable) 1097 reg += OMAP4_GPIO_IRQSTATUSSET0; 1098 else 1099 reg += OMAP4_GPIO_IRQSTATUSCLR0; 1100 l = gpio_mask; 1101 break; 1102#endif 1103 default: 1104 WARN_ON(1); 1105 return; 1106 } 1107 __raw_writel(l, reg); 1108} 1109 1110static inline void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int enable) 1111{ 1112 _enable_gpio_irqbank(bank, 1 << get_gpio_index(gpio), enable); 1113} 1114 1115/* 1116 * Note that ENAWAKEUP needs to be enabled in GPIO_SYSCONFIG register. 1117 * 1510 does not seem to have a wake-up register. If JTAG is connected 1118 * to the target, system will wake up always on GPIO events. While 1119 * system is running all registered GPIO interrupts need to have wake-up 1120 * enabled. When system is suspended, only selected GPIO interrupts need 1121 * to have wake-up enabled. 1122 */ 1123static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable) 1124{ 1125 unsigned long uninitialized_var(flags); 1126 1127 switch (bank->method) { 1128#ifdef CONFIG_ARCH_OMAP16XX 1129 case METHOD_MPUIO: 1130 case METHOD_GPIO_1610: 1131 spin_lock_irqsave(&bank->lock, flags); 1132 if (enable) 1133 bank->suspend_wakeup |= (1 << gpio); 1134 else 1135 bank->suspend_wakeup &= ~(1 << gpio); 1136 spin_unlock_irqrestore(&bank->lock, flags); 1137 return 0; 1138#endif 1139#ifdef CONFIG_ARCH_OMAP2PLUS 1140 case METHOD_GPIO_24XX: 1141 case METHOD_GPIO_44XX: 1142 if (bank->non_wakeup_gpios & (1 << gpio)) { 1143 printk(KERN_ERR "Unable to modify wakeup on " 1144 "non-wakeup GPIO%d\n", 1145 (bank - gpio_bank) * 32 + gpio); 1146 return -EINVAL; 1147 } 1148 spin_lock_irqsave(&bank->lock, flags); 1149 if (enable) 1150 bank->suspend_wakeup |= (1 << gpio); 1151 else 1152 bank->suspend_wakeup &= ~(1 << gpio); 1153 spin_unlock_irqrestore(&bank->lock, flags); 1154 return 0; 1155#endif 1156 default: 1157 printk(KERN_ERR "Can't enable GPIO wakeup for method %i\n", 1158 bank->method); 1159 return -EINVAL; 1160 } 1161} 1162 1163static void _reset_gpio(struct gpio_bank *bank, int gpio) 1164{ 1165 _set_gpio_direction(bank, get_gpio_index(gpio), 1); 1166 _set_gpio_irqenable(bank, gpio, 0); 1167 _clear_gpio_irqstatus(bank, gpio); 1168 _set_gpio_triggering(bank, get_gpio_index(gpio), IRQ_TYPE_NONE); 1169} 1170 1171/* Use disable_irq_wake() and enable_irq_wake() functions from drivers */ 1172static int gpio_wake_enable(unsigned int irq, unsigned int enable) 1173{ 1174 unsigned int gpio = irq - IH_GPIO_BASE; 1175 struct gpio_bank *bank; 1176 int retval; 1177 1178 if (check_gpio(gpio) < 0) 1179 return -ENODEV; 1180 bank = get_irq_chip_data(irq); 1181 retval = _set_gpio_wakeup(bank, get_gpio_index(gpio), enable); 1182 1183 return retval; 1184} 1185 1186static int omap_gpio_request(struct gpio_chip *chip, unsigned offset) 1187{ 1188 struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip); 1189 unsigned long flags; 1190 1191 spin_lock_irqsave(&bank->lock, flags); 1192 1193 /* Set trigger to none. You need to enable the desired trigger with 1194 * request_irq() or set_irq_type(). 1195 */ 1196 _set_gpio_triggering(bank, offset, IRQ_TYPE_NONE); 1197 1198#ifdef CONFIG_ARCH_OMAP15XX 1199 if (bank->method == METHOD_GPIO_1510) { 1200 void __iomem *reg; 1201 1202 /* Claim the pin for MPU */ 1203 reg = bank->base + OMAP1510_GPIO_PIN_CONTROL; 1204 __raw_writel(__raw_readl(reg) | (1 << offset), reg); 1205 } 1206#endif 1207 if (!cpu_class_is_omap1()) { 1208 if (!bank->mod_usage) { 1209 void __iomem *reg = bank->base; 1210 u32 ctrl; 1211 1212 if (cpu_is_omap24xx() || cpu_is_omap34xx()) 1213 reg += OMAP24XX_GPIO_CTRL; 1214 else if (cpu_is_omap44xx()) 1215 reg += OMAP4_GPIO_CTRL; 1216 ctrl = __raw_readl(reg); 1217 /* Module is enabled, clocks are not gated */ 1218 ctrl &= 0xFFFFFFFE; 1219 __raw_writel(ctrl, reg); 1220 } 1221 bank->mod_usage |= 1 << offset; 1222 } 1223 spin_unlock_irqrestore(&bank->lock, flags); 1224 1225 return 0; 1226} 1227 1228static void omap_gpio_free(struct gpio_chip *chip, unsigned offset) 1229{ 1230 struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip); 1231 unsigned long flags; 1232 1233 spin_lock_irqsave(&bank->lock, flags); 1234#ifdef CONFIG_ARCH_OMAP16XX 1235 if (bank->method == METHOD_GPIO_1610) { 1236 /* Disable wake-up during idle for dynamic tick */ 1237 void __iomem *reg = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA; 1238 __raw_writel(1 << offset, reg); 1239 } 1240#endif 1241#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) 1242 if (bank->method == METHOD_GPIO_24XX) { 1243 /* Disable wake-up during idle for dynamic tick */ 1244 void __iomem *reg = bank->base + OMAP24XX_GPIO_CLEARWKUENA; 1245 __raw_writel(1 << offset, reg); 1246 } 1247#endif 1248#ifdef CONFIG_ARCH_OMAP4 1249 if (bank->method == METHOD_GPIO_44XX) { 1250 /* Disable wake-up during idle for dynamic tick */ 1251 void __iomem *reg = bank->base + OMAP4_GPIO_IRQWAKEN0; 1252 __raw_writel(1 << offset, reg); 1253 } 1254#endif 1255 if (!cpu_class_is_omap1()) { 1256 bank->mod_usage &= ~(1 << offset); 1257 if (!bank->mod_usage) { 1258 void __iomem *reg = bank->base; 1259 u32 ctrl; 1260 1261 if (cpu_is_omap24xx() || cpu_is_omap34xx()) 1262 reg += OMAP24XX_GPIO_CTRL; 1263 else if (cpu_is_omap44xx()) 1264 reg += OMAP4_GPIO_CTRL; 1265 ctrl = __raw_readl(reg); 1266 /* Module is disabled, clocks are gated */ 1267 ctrl |= 1; 1268 __raw_writel(ctrl, reg); 1269 } 1270 } 1271 _reset_gpio(bank, bank->chip.base + offset); 1272 spin_unlock_irqrestore(&bank->lock, flags); 1273} 1274 1275/* 1276 * We need to unmask the GPIO bank interrupt as soon as possible to 1277 * avoid missing GPIO interrupts for other lines in the bank. 1278 * Then we need to mask-read-clear-unmask the triggered GPIO lines 1279 * in the bank to avoid missing nested interrupts for a GPIO line. 1280 * If we wait to unmask individual GPIO lines in the bank after the 1281 * line's interrupt handler has been run, we may miss some nested 1282 * interrupts. 1283 */ 1284static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc) 1285{ 1286 void __iomem *isr_reg = NULL; 1287 u32 isr; 1288 unsigned int gpio_irq, gpio_index; 1289 struct gpio_bank *bank; 1290 u32 retrigger = 0; 1291 int unmasked = 0; 1292 1293 desc->chip->ack(irq); 1294 1295 bank = get_irq_data(irq); 1296#ifdef CONFIG_ARCH_OMAP1 1297 if (bank->method == METHOD_MPUIO) 1298 isr_reg = bank->base + OMAP_MPUIO_GPIO_INT; 1299#endif 1300#ifdef CONFIG_ARCH_OMAP15XX 1301 if (bank->method == METHOD_GPIO_1510) 1302 isr_reg = bank->base + OMAP1510_GPIO_INT_STATUS; 1303#endif 1304#if defined(CONFIG_ARCH_OMAP16XX) 1305 if (bank->method == METHOD_GPIO_1610) 1306 isr_reg = bank->base + OMAP1610_GPIO_IRQSTATUS1; 1307#endif 1308#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850) 1309 if (bank->method == METHOD_GPIO_7XX) 1310 isr_reg = bank->base + OMAP7XX_GPIO_INT_STATUS; 1311#endif 1312#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) 1313 if (bank->method == METHOD_GPIO_24XX) 1314 isr_reg = bank->base + OMAP24XX_GPIO_IRQSTATUS1; 1315#endif 1316#if defined(CONFIG_ARCH_OMAP4) 1317 if (bank->method == METHOD_GPIO_44XX) 1318 isr_reg = bank->base + OMAP4_GPIO_IRQSTATUS0; 1319#endif 1320 while(1) { 1321 u32 isr_saved, level_mask = 0; 1322 u32 enabled; 1323 1324 enabled = _get_gpio_irqbank_mask(bank); 1325 isr_saved = isr = __raw_readl(isr_reg) & enabled; 1326 1327 if (cpu_is_omap15xx() && (bank->method == METHOD_MPUIO)) 1328 isr &= 0x0000ffff; 1329 1330 if (cpu_class_is_omap2()) { 1331 level_mask = bank->level_mask & enabled; 1332 } 1333 1334 /* clear edge sensitive interrupts before handler(s) are 1335 called so that we don't miss any interrupt occurred while 1336 executing them */ 1337 _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 0); 1338 _clear_gpio_irqbank(bank, isr_saved & ~level_mask); 1339 _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 1); 1340 1341 /* if there is only edge sensitive GPIO pin interrupts 1342 configured, we could unmask GPIO bank interrupt immediately */ 1343 if (!level_mask && !unmasked) { 1344 unmasked = 1; 1345 desc->chip->unmask(irq); 1346 } 1347 1348 isr |= retrigger; 1349 retrigger = 0; 1350 if (!isr) 1351 break; 1352 1353 gpio_irq = bank->virtual_irq_start; 1354 for (; isr != 0; isr >>= 1, gpio_irq++) { 1355 gpio_index = get_gpio_index(irq_to_gpio(gpio_irq)); 1356 1357 if (!(isr & 1)) 1358 continue; 1359 1360#ifdef CONFIG_ARCH_OMAP1 1361 /* 1362 * Some chips can't respond to both rising and falling 1363 * at the same time. If this irq was requested with 1364 * both flags, we need to flip the ICR data for the IRQ 1365 * to respond to the IRQ for the opposite direction. 1366 * This will be indicated in the bank toggle_mask. 1367 */ 1368 if (bank->toggle_mask & (1 << gpio_index)) 1369 _toggle_gpio_edge_triggering(bank, gpio_index); 1370#endif 1371 1372 generic_handle_irq(gpio_irq); 1373 } 1374 } 1375 /* if bank has any level sensitive GPIO pin interrupt 1376 configured, we must unmask the bank interrupt only after 1377 handler(s) are executed in order to avoid spurious bank 1378 interrupt */ 1379 if (!unmasked) 1380 desc->chip->unmask(irq); 1381 1382} 1383 1384static void gpio_irq_shutdown(unsigned int irq) 1385{ 1386 unsigned int gpio = irq - IH_GPIO_BASE; 1387 struct gpio_bank *bank = get_irq_chip_data(irq); 1388 1389 _reset_gpio(bank, gpio); 1390} 1391 1392static void gpio_ack_irq(unsigned int irq) 1393{ 1394 unsigned int gpio = irq - IH_GPIO_BASE; 1395 struct gpio_bank *bank = get_irq_chip_data(irq); 1396 1397 _clear_gpio_irqstatus(bank, gpio); 1398} 1399 1400static void gpio_mask_irq(unsigned int irq) 1401{ 1402 unsigned int gpio = irq - IH_GPIO_BASE; 1403 struct gpio_bank *bank = get_irq_chip_data(irq); 1404 1405 _set_gpio_irqenable(bank, gpio, 0); 1406 _set_gpio_triggering(bank, get_gpio_index(gpio), IRQ_TYPE_NONE); 1407} 1408 1409static void gpio_unmask_irq(unsigned int irq) 1410{ 1411 unsigned int gpio = irq - IH_GPIO_BASE; 1412 struct gpio_bank *bank = get_irq_chip_data(irq); 1413 unsigned int irq_mask = 1 << get_gpio_index(gpio); 1414 struct irq_desc *desc = irq_to_desc(irq); 1415 u32 trigger = desc->status & IRQ_TYPE_SENSE_MASK; 1416 1417 if (trigger) 1418 _set_gpio_triggering(bank, get_gpio_index(gpio), trigger); 1419 1420 /* For level-triggered GPIOs, the clearing must be done after 1421 * the HW source is cleared, thus after the handler has run */ 1422 if (bank->level_mask & irq_mask) { 1423 _set_gpio_irqenable(bank, gpio, 0); 1424 _clear_gpio_irqstatus(bank, gpio); 1425 } 1426 1427 _set_gpio_irqenable(bank, gpio, 1); 1428} 1429 1430static struct irq_chip gpio_irq_chip = { 1431 .name = "GPIO", 1432 .shutdown = gpio_irq_shutdown, 1433 .ack = gpio_ack_irq, 1434 .mask = gpio_mask_irq, 1435 .unmask = gpio_unmask_irq, 1436 .set_type = gpio_irq_type, 1437 .set_wake = gpio_wake_enable, 1438}; 1439 1440/*---------------------------------------------------------------------*/ 1441 1442#ifdef CONFIG_ARCH_OMAP1 1443 1444/* MPUIO uses the always-on 32k clock */ 1445 1446static void mpuio_ack_irq(unsigned int irq) 1447{ 1448 /* The ISR is reset automatically, so do nothing here. */ 1449} 1450 1451static void mpuio_mask_irq(unsigned int irq) 1452{ 1453 unsigned int gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE); 1454 struct gpio_bank *bank = get_irq_chip_data(irq); 1455 1456 _set_gpio_irqenable(bank, gpio, 0); 1457} 1458 1459static void mpuio_unmask_irq(unsigned int irq) 1460{ 1461 unsigned int gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE); 1462 struct gpio_bank *bank = get_irq_chip_data(irq); 1463 1464 _set_gpio_irqenable(bank, gpio, 1); 1465} 1466 1467static struct irq_chip mpuio_irq_chip = { 1468 .name = "MPUIO", 1469 .ack = mpuio_ack_irq, 1470 .mask = mpuio_mask_irq, 1471 .unmask = mpuio_unmask_irq, 1472 .set_type = gpio_irq_type, 1473#ifdef CONFIG_ARCH_OMAP16XX 1474 /* REVISIT: assuming only 16xx supports MPUIO wake events */ 1475 .set_wake = gpio_wake_enable, 1476#endif 1477}; 1478 1479 1480#define bank_is_mpuio(bank) ((bank)->method == METHOD_MPUIO) 1481 1482 1483#ifdef CONFIG_ARCH_OMAP16XX 1484 1485#include <linux/platform_device.h> 1486 1487static int omap_mpuio_suspend_noirq(struct device *dev) 1488{ 1489 struct platform_device *pdev = to_platform_device(dev); 1490 struct gpio_bank *bank = platform_get_drvdata(pdev); 1491 void __iomem *mask_reg = bank->base + OMAP_MPUIO_GPIO_MASKIT; 1492 unsigned long flags; 1493 1494 spin_lock_irqsave(&bank->lock, flags); 1495 bank->saved_wakeup = __raw_readl(mask_reg); 1496 __raw_writel(0xffff & ~bank->suspend_wakeup, mask_reg); 1497 spin_unlock_irqrestore(&bank->lock, flags); 1498 1499 return 0; 1500} 1501 1502static int omap_mpuio_resume_noirq(struct device *dev) 1503{ 1504 struct platform_device *pdev = to_platform_device(dev); 1505 struct gpio_bank *bank = platform_get_drvdata(pdev); 1506 void __iomem *mask_reg = bank->base + OMAP_MPUIO_GPIO_MASKIT; 1507 unsigned long flags; 1508 1509 spin_lock_irqsave(&bank->lock, flags); 1510 __raw_writel(bank->saved_wakeup, mask_reg); 1511 spin_unlock_irqrestore(&bank->lock, flags); 1512 1513 return 0; 1514} 1515 1516static const struct dev_pm_ops omap_mpuio_dev_pm_ops = { 1517 .suspend_noirq = omap_mpuio_suspend_noirq, 1518 .resume_noirq = omap_mpuio_resume_noirq, 1519}; 1520 1521/* use platform_driver for this, now that there's no longer any 1522 * point to sys_device (other than not disturbing old code). 1523 */ 1524static struct platform_driver omap_mpuio_driver = { 1525 .driver = { 1526 .name = "mpuio", 1527 .pm = &omap_mpuio_dev_pm_ops, 1528 }, 1529}; 1530 1531static struct platform_device omap_mpuio_device = { 1532 .name = "mpuio", 1533 .id = -1, 1534 .dev = { 1535 .driver = &omap_mpuio_driver.driver, 1536 } 1537 /* could list the /proc/iomem resources */ 1538}; 1539 1540static inline void mpuio_init(void) 1541{ 1542 platform_set_drvdata(&omap_mpuio_device, &gpio_bank_1610[0]); 1543 1544 if (platform_driver_register(&omap_mpuio_driver) == 0) 1545 (void) platform_device_register(&omap_mpuio_device); 1546} 1547 1548#else 1549static inline void mpuio_init(void) {} 1550#endif /* 16xx */ 1551 1552#else 1553 1554extern struct irq_chip mpuio_irq_chip; 1555 1556#define bank_is_mpuio(bank) 0 1557static inline void mpuio_init(void) {} 1558 1559#endif 1560 1561/*---------------------------------------------------------------------*/ 1562 1563/* REVISIT these are stupid implementations! replace by ones that 1564 * don't switch on METHOD_* and which mostly avoid spinlocks 1565 */ 1566 1567static int gpio_input(struct gpio_chip *chip, unsigned offset) 1568{ 1569 struct gpio_bank *bank; 1570 unsigned long flags; 1571 1572 bank = container_of(chip, struct gpio_bank, chip); 1573 spin_lock_irqsave(&bank->lock, flags); 1574 _set_gpio_direction(bank, offset, 1); 1575 spin_unlock_irqrestore(&bank->lock, flags); 1576 return 0; 1577} 1578 1579static int gpio_is_input(struct gpio_bank *bank, int mask) 1580{ 1581 void __iomem *reg = bank->base; 1582 1583 switch (bank->method) { 1584 case METHOD_MPUIO: 1585 reg += OMAP_MPUIO_IO_CNTL; 1586 break; 1587 case METHOD_GPIO_1510: 1588 reg += OMAP1510_GPIO_DIR_CONTROL; 1589 break; 1590 case METHOD_GPIO_1610: 1591 reg += OMAP1610_GPIO_DIRECTION; 1592 break; 1593 case METHOD_GPIO_7XX: 1594 reg += OMAP7XX_GPIO_DIR_CONTROL; 1595 break; 1596 case METHOD_GPIO_24XX: 1597 reg += OMAP24XX_GPIO_OE; 1598 break; 1599 case METHOD_GPIO_44XX: 1600 reg += OMAP4_GPIO_OE; 1601 break; 1602 default: 1603 WARN_ONCE(1, "gpio_is_input: incorrect OMAP GPIO method"); 1604 return -EINVAL; 1605 } 1606 return __raw_readl(reg) & mask; 1607} 1608 1609static int gpio_get(struct gpio_chip *chip, unsigned offset) 1610{ 1611 struct gpio_bank *bank; 1612 void __iomem *reg; 1613 int gpio; 1614 u32 mask; 1615 1616 gpio = chip->base + offset; 1617 bank = get_gpio_bank(gpio); 1618 reg = bank->base; 1619 mask = 1 << get_gpio_index(gpio); 1620 1621 if (gpio_is_input(bank, mask)) 1622 return _get_gpio_datain(bank, gpio); 1623 else 1624 return _get_gpio_dataout(bank, gpio); 1625} 1626 1627static int gpio_output(struct gpio_chip *chip, unsigned offset, int value) 1628{ 1629 struct gpio_bank *bank; 1630 unsigned long flags; 1631 1632 bank = container_of(chip, struct gpio_bank, chip); 1633 spin_lock_irqsave(&bank->lock, flags); 1634 _set_gpio_dataout(bank, offset, value); 1635 _set_gpio_direction(bank, offset, 0); 1636 spin_unlock_irqrestore(&bank->lock, flags); 1637 return 0; 1638} 1639 1640static int gpio_debounce(struct gpio_chip *chip, unsigned offset, 1641 unsigned debounce) 1642{ 1643 struct gpio_bank *bank; 1644 unsigned long flags; 1645 1646 bank = container_of(chip, struct gpio_bank, chip); 1647 spin_lock_irqsave(&bank->lock, flags); 1648 _set_gpio_debounce(bank, offset, debounce); 1649 spin_unlock_irqrestore(&bank->lock, flags); 1650 1651 return 0; 1652} 1653 1654static void gpio_set(struct gpio_chip *chip, unsigned offset, int value) 1655{ 1656 struct gpio_bank *bank; 1657 unsigned long flags; 1658 1659 bank = container_of(chip, struct gpio_bank, chip); 1660 spin_lock_irqsave(&bank->lock, flags); 1661 _set_gpio_dataout(bank, offset, value); 1662 spin_unlock_irqrestore(&bank->lock, flags); 1663} 1664 1665static int gpio_2irq(struct gpio_chip *chip, unsigned offset) 1666{ 1667 struct gpio_bank *bank; 1668 1669 bank = container_of(chip, struct gpio_bank, chip); 1670 return bank->virtual_irq_start + offset; 1671} 1672 1673/*---------------------------------------------------------------------*/ 1674 1675static int initialized; 1676#if defined(CONFIG_ARCH_OMAP1) || defined(CONFIG_ARCH_OMAP2) 1677static struct clk * gpio_ick; 1678#endif 1679 1680#if defined(CONFIG_ARCH_OMAP2) 1681static struct clk * gpio_fck; 1682#endif 1683 1684#if defined(CONFIG_ARCH_OMAP2430) 1685static struct clk * gpio5_ick; 1686static struct clk * gpio5_fck; 1687#endif 1688 1689#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4) 1690static struct clk *gpio_iclks[OMAP34XX_NR_GPIOS]; 1691#endif 1692 1693static void __init omap_gpio_show_rev(void) 1694{ 1695 u32 rev; 1696 1697 if (cpu_is_omap16xx()) 1698 rev = __raw_readw(gpio_bank[1].base + OMAP1610_GPIO_REVISION); 1699 else if (cpu_is_omap24xx() || cpu_is_omap34xx()) 1700 rev = __raw_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION); 1701 else if (cpu_is_omap44xx()) 1702 rev = __raw_readl(gpio_bank[0].base + OMAP4_GPIO_REVISION); 1703 else 1704 return; 1705 1706 printk(KERN_INFO "OMAP GPIO hardware version %d.%d\n", 1707 (rev >> 4) & 0x0f, rev & 0x0f); 1708} 1709 1710/* This lock class tells lockdep that GPIO irqs are in a different 1711 * category than their parents, so it won't report false recursion. 1712 */ 1713static struct lock_class_key gpio_lock_class; 1714 1715static int __init _omap_gpio_init(void) 1716{ 1717 int i; 1718 int gpio = 0; 1719 struct gpio_bank *bank; 1720 int bank_size = SZ_8K; /* Module 4KB + L4 4KB except on omap1 */ 1721 char clk_name[11]; 1722 1723 initialized = 1; 1724 1725#if defined(CONFIG_ARCH_OMAP1) 1726 if (cpu_is_omap15xx()) { 1727 gpio_ick = clk_get(NULL, "arm_gpio_ck"); 1728 if (IS_ERR(gpio_ick)) 1729 printk("Could not get arm_gpio_ck\n"); 1730 else 1731 clk_enable(gpio_ick); 1732 } 1733#endif 1734#if defined(CONFIG_ARCH_OMAP2) 1735 if (cpu_class_is_omap2()) { 1736 gpio_ick = clk_get(NULL, "gpios_ick"); 1737 if (IS_ERR(gpio_ick)) 1738 printk("Could not get gpios_ick\n"); 1739 else 1740 clk_enable(gpio_ick); 1741 gpio_fck = clk_get(NULL, "gpios_fck"); 1742 if (IS_ERR(gpio_fck)) 1743 printk("Could not get gpios_fck\n"); 1744 else 1745 clk_enable(gpio_fck); 1746 1747 /* 1748 * On 2430 & 3430 GPIO 5 uses CORE L4 ICLK 1749 */ 1750#if defined(CONFIG_ARCH_OMAP2430) 1751 if (cpu_is_omap2430()) { 1752 gpio5_ick = clk_get(NULL, "gpio5_ick"); 1753 if (IS_ERR(gpio5_ick)) 1754 printk("Could not get gpio5_ick\n"); 1755 else 1756 clk_enable(gpio5_ick); 1757 gpio5_fck = clk_get(NULL, "gpio5_fck"); 1758 if (IS_ERR(gpio5_fck)) 1759 printk("Could not get gpio5_fck\n"); 1760 else 1761 clk_enable(gpio5_fck); 1762 } 1763#endif 1764 } 1765#endif 1766 1767#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4) 1768 if (cpu_is_omap34xx() || cpu_is_omap44xx()) { 1769 for (i = 0; i < OMAP34XX_NR_GPIOS; i++) { 1770 sprintf(clk_name, "gpio%d_ick", i + 1); 1771 gpio_iclks[i] = clk_get(NULL, clk_name); 1772 if (IS_ERR(gpio_iclks[i])) 1773 printk(KERN_ERR "Could not get %s\n", clk_name); 1774 else 1775 clk_enable(gpio_iclks[i]); 1776 } 1777 } 1778#endif 1779 1780 1781#ifdef CONFIG_ARCH_OMAP15XX 1782 if (cpu_is_omap15xx()) { 1783 gpio_bank_count = 2; 1784 gpio_bank = gpio_bank_1510; 1785 bank_size = SZ_2K; 1786 } 1787#endif 1788#if defined(CONFIG_ARCH_OMAP16XX) 1789 if (cpu_is_omap16xx()) { 1790 gpio_bank_count = 5; 1791 gpio_bank = gpio_bank_1610; 1792 bank_size = SZ_2K; 1793 } 1794#endif 1795#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850) 1796 if (cpu_is_omap7xx()) { 1797 gpio_bank_count = 7; 1798 gpio_bank = gpio_bank_7xx; 1799 bank_size = SZ_2K; 1800 } 1801#endif 1802#ifdef CONFIG_ARCH_OMAP2 1803 if (cpu_is_omap242x()) { 1804 gpio_bank_count = 4; 1805 gpio_bank = gpio_bank_242x; 1806 } 1807 if (cpu_is_omap243x()) { 1808 gpio_bank_count = 5; 1809 gpio_bank = gpio_bank_243x; 1810 } 1811#endif 1812#ifdef CONFIG_ARCH_OMAP3 1813 if (cpu_is_omap34xx()) { 1814 gpio_bank_count = OMAP34XX_NR_GPIOS; 1815 gpio_bank = gpio_bank_34xx; 1816 } 1817#endif 1818#ifdef CONFIG_ARCH_OMAP4 1819 if (cpu_is_omap44xx()) { 1820 gpio_bank_count = OMAP34XX_NR_GPIOS; 1821 gpio_bank = gpio_bank_44xx; 1822 } 1823#endif 1824 for (i = 0; i < gpio_bank_count; i++) { 1825 int j, gpio_count = 16; 1826 1827 bank = &gpio_bank[i]; 1828 spin_lock_init(&bank->lock); 1829 1830 /* Static mapping, never released */ 1831 bank->base = ioremap(bank->pbase, bank_size); 1832 if (!bank->base) { 1833 printk(KERN_ERR "Could not ioremap gpio bank%i\n", i); 1834 continue; 1835 } 1836 1837 if (bank_is_mpuio(bank)) 1838 __raw_writew(0xffff, bank->base + OMAP_MPUIO_GPIO_MASKIT); 1839 if (cpu_is_omap15xx() && bank->method == METHOD_GPIO_1510) { 1840 __raw_writew(0xffff, bank->base + OMAP1510_GPIO_INT_MASK); 1841 __raw_writew(0x0000, bank->base + OMAP1510_GPIO_INT_STATUS); 1842 } 1843 if (cpu_is_omap16xx() && bank->method == METHOD_GPIO_1610) { 1844 __raw_writew(0x0000, bank->base + OMAP1610_GPIO_IRQENABLE1); 1845 __raw_writew(0xffff, bank->base + OMAP1610_GPIO_IRQSTATUS1); 1846 __raw_writew(0x0014, bank->base + OMAP1610_GPIO_SYSCONFIG); 1847 } 1848 if (cpu_is_omap7xx() && bank->method == METHOD_GPIO_7XX) { 1849 __raw_writel(0xffffffff, bank->base + OMAP7XX_GPIO_INT_MASK); 1850 __raw_writel(0x00000000, bank->base + OMAP7XX_GPIO_INT_STATUS); 1851 1852 gpio_count = 32; /* 7xx has 32-bit GPIOs */ 1853 } 1854 1855#ifdef CONFIG_ARCH_OMAP2PLUS 1856 if ((bank->method == METHOD_GPIO_24XX) || 1857 (bank->method == METHOD_GPIO_44XX)) { 1858 static const u32 non_wakeup_gpios[] = { 1859 0xe203ffc0, 0x08700040 1860 }; 1861 1862 if (cpu_is_omap44xx()) { 1863 __raw_writel(0xffffffff, bank->base + 1864 OMAP4_GPIO_IRQSTATUSCLR0); 1865 __raw_writew(0x0015, bank->base + 1866 OMAP4_GPIO_SYSCONFIG); 1867 __raw_writel(0x00000000, bank->base + 1868 OMAP4_GPIO_DEBOUNCENABLE); 1869 /* 1870 * Initialize interface clock ungated, 1871 * module enabled 1872 */ 1873 __raw_writel(0, bank->base + OMAP4_GPIO_CTRL); 1874 } else { 1875 __raw_writel(0x00000000, bank->base + 1876 OMAP24XX_GPIO_IRQENABLE1); 1877 __raw_writel(0xffffffff, bank->base + 1878 OMAP24XX_GPIO_IRQSTATUS1); 1879 __raw_writew(0x0015, bank->base + 1880 OMAP24XX_GPIO_SYSCONFIG); 1881 __raw_writel(0x00000000, bank->base + 1882 OMAP24XX_GPIO_DEBOUNCE_EN); 1883 1884 /* 1885 * Initialize interface clock ungated, 1886 * module enabled 1887 */ 1888 __raw_writel(0, bank->base + 1889 OMAP24XX_GPIO_CTRL); 1890 } 1891 if (cpu_is_omap24xx() && 1892 i < ARRAY_SIZE(non_wakeup_gpios)) 1893 bank->non_wakeup_gpios = non_wakeup_gpios[i]; 1894 gpio_count = 32; 1895 } 1896#endif 1897 1898 bank->mod_usage = 0; 1899 /* REVISIT eventually switch from OMAP-specific gpio structs 1900 * over to the generic ones 1901 */ 1902 bank->chip.request = omap_gpio_request; 1903 bank->chip.free = omap_gpio_free; 1904 bank->chip.direction_input = gpio_input; 1905 bank->chip.get = gpio_get; 1906 bank->chip.direction_output = gpio_output; 1907 bank->chip.set_debounce = gpio_debounce; 1908 bank->chip.set = gpio_set; 1909 bank->chip.to_irq = gpio_2irq; 1910 if (bank_is_mpuio(bank)) { 1911 bank->chip.label = "mpuio"; 1912#ifdef CONFIG_ARCH_OMAP16XX 1913 bank->chip.dev = &omap_mpuio_device.dev; 1914#endif 1915 bank->chip.base = OMAP_MPUIO(0); 1916 } else { 1917 bank->chip.label = "gpio"; 1918 bank->chip.base = gpio; 1919 gpio += gpio_count; 1920 } 1921 bank->chip.ngpio = gpio_count; 1922 1923 gpiochip_add(&bank->chip); 1924 1925 for (j = bank->virtual_irq_start; 1926 j < bank->virtual_irq_start + gpio_count; j++) { 1927 lockdep_set_class(&irq_desc[j].lock, &gpio_lock_class); 1928 set_irq_chip_data(j, bank); 1929 if (bank_is_mpuio(bank)) 1930 set_irq_chip(j, &mpuio_irq_chip); 1931 else 1932 set_irq_chip(j, &gpio_irq_chip); 1933 set_irq_handler(j, handle_simple_irq); 1934 set_irq_flags(j, IRQF_VALID); 1935 } 1936 set_irq_chained_handler(bank->irq, gpio_irq_handler); 1937 set_irq_data(bank->irq, bank); 1938 1939 if (cpu_is_omap34xx() || cpu_is_omap44xx()) { 1940 sprintf(clk_name, "gpio%d_dbck", i + 1); 1941 bank->dbck = clk_get(NULL, clk_name); 1942 if (IS_ERR(bank->dbck)) 1943 printk(KERN_ERR "Could not get %s\n", clk_name); 1944 } 1945 } 1946 1947 /* Enable system clock for GPIO module. 1948 * The CAM_CLK_CTRL *is* really the right place. */ 1949 if (cpu_is_omap16xx()) 1950 omap_writel(omap_readl(ULPD_CAM_CLK_CTRL) | 0x04, ULPD_CAM_CLK_CTRL); 1951 1952 /* Enable autoidle for the OCP interface */ 1953 if (cpu_is_omap24xx()) 1954 omap_writel(1 << 0, 0x48019010); 1955 if (cpu_is_omap34xx()) 1956 omap_writel(1 << 0, 0x48306814); 1957 1958 omap_gpio_show_rev(); 1959 1960 return 0; 1961} 1962 1963#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS) 1964static int omap_gpio_suspend(struct sys_device *dev, pm_message_t mesg) 1965{ 1966 int i; 1967 1968 if (!cpu_class_is_omap2() && !cpu_is_omap16xx()) 1969 return 0; 1970 1971 for (i = 0; i < gpio_bank_count; i++) { 1972 struct gpio_bank *bank = &gpio_bank[i]; 1973 void __iomem *wake_status; 1974 void __iomem *wake_clear; 1975 void __iomem *wake_set; 1976 unsigned long flags; 1977 1978 switch (bank->method) { 1979#ifdef CONFIG_ARCH_OMAP16XX 1980 case METHOD_GPIO_1610: 1981 wake_status = bank->base + OMAP1610_GPIO_WAKEUPENABLE; 1982 wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA; 1983 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA; 1984 break; 1985#endif 1986#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) 1987 case METHOD_GPIO_24XX: 1988 wake_status = bank->base + OMAP24XX_GPIO_WAKE_EN; 1989 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA; 1990 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA; 1991 break; 1992#endif 1993#ifdef CONFIG_ARCH_OMAP4 1994 case METHOD_GPIO_44XX: 1995 wake_status = bank->base + OMAP4_GPIO_IRQWAKEN0; 1996 wake_clear = bank->base + OMAP4_GPIO_IRQWAKEN0; 1997 wake_set = bank->base + OMAP4_GPIO_IRQWAKEN0; 1998 break; 1999#endif 2000 default: 2001 continue; 2002 } 2003 2004 spin_lock_irqsave(&bank->lock, flags); 2005 bank->saved_wakeup = __raw_readl(wake_status); 2006 __raw_writel(0xffffffff, wake_clear); 2007 __raw_writel(bank->suspend_wakeup, wake_set); 2008 spin_unlock_irqrestore(&bank->lock, flags); 2009 } 2010 2011 return 0; 2012} 2013 2014static int omap_gpio_resume(struct sys_device *dev) 2015{ 2016 int i; 2017 2018 if (!cpu_class_is_omap2() && !cpu_is_omap16xx()) 2019 return 0; 2020 2021 for (i = 0; i < gpio_bank_count; i++) { 2022 struct gpio_bank *bank = &gpio_bank[i]; 2023 void __iomem *wake_clear; 2024 void __iomem *wake_set; 2025 unsigned long flags; 2026 2027 switch (bank->method) { 2028#ifdef CONFIG_ARCH_OMAP16XX 2029 case METHOD_GPIO_1610: 2030 wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA; 2031 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA; 2032 break; 2033#endif 2034#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) 2035 case METHOD_GPIO_24XX: 2036 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA; 2037 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA; 2038 break; 2039#endif 2040#ifdef CONFIG_ARCH_OMAP4 2041 case METHOD_GPIO_44XX: 2042 wake_clear = bank->base + OMAP4_GPIO_IRQWAKEN0; 2043 wake_set = bank->base + OMAP4_GPIO_IRQWAKEN0; 2044 break; 2045#endif 2046 default: 2047 continue; 2048 } 2049 2050 spin_lock_irqsave(&bank->lock, flags); 2051 __raw_writel(0xffffffff, wake_clear); 2052 __raw_writel(bank->saved_wakeup, wake_set); 2053 spin_unlock_irqrestore(&bank->lock, flags); 2054 } 2055 2056 return 0; 2057} 2058 2059static struct sysdev_class omap_gpio_sysclass = { 2060 .name = "gpio", 2061 .suspend = omap_gpio_suspend, 2062 .resume = omap_gpio_resume, 2063}; 2064 2065static struct sys_device omap_gpio_device = { 2066 .id = 0, 2067 .cls = &omap_gpio_sysclass, 2068}; 2069 2070#endif 2071 2072#ifdef CONFIG_ARCH_OMAP2PLUS 2073 2074static int workaround_enabled; 2075 2076void omap2_gpio_prepare_for_idle(int power_state) 2077{ 2078 int i, c = 0; 2079 int min = 0; 2080 2081 if (cpu_is_omap34xx()) 2082 min = 1; 2083 2084 for (i = min; i < gpio_bank_count; i++) { 2085 struct gpio_bank *bank = &gpio_bank[i]; 2086 u32 l1, l2; 2087 2088 if (bank->dbck_enable_mask) 2089 clk_disable(bank->dbck); 2090 2091 if (power_state > PWRDM_POWER_OFF) 2092 continue; 2093 2094 /* If going to OFF, remove triggering for all 2095 * non-wakeup GPIOs. Otherwise spurious IRQs will be 2096 * generated. See OMAP2420 Errata item 1.101. */ 2097 if (!(bank->enabled_non_wakeup_gpios)) 2098 continue; 2099 2100 if (cpu_is_omap24xx() || cpu_is_omap34xx()) { 2101 bank->saved_datain = __raw_readl(bank->base + 2102 OMAP24XX_GPIO_DATAIN); 2103 l1 = __raw_readl(bank->base + 2104 OMAP24XX_GPIO_FALLINGDETECT); 2105 l2 = __raw_readl(bank->base + 2106 OMAP24XX_GPIO_RISINGDETECT); 2107 } 2108 2109 if (cpu_is_omap44xx()) { 2110 bank->saved_datain = __raw_readl(bank->base + 2111 OMAP4_GPIO_DATAIN); 2112 l1 = __raw_readl(bank->base + 2113 OMAP4_GPIO_FALLINGDETECT); 2114 l2 = __raw_readl(bank->base + 2115 OMAP4_GPIO_RISINGDETECT); 2116 } 2117 2118 bank->saved_fallingdetect = l1; 2119 bank->saved_risingdetect = l2; 2120 l1 &= ~bank->enabled_non_wakeup_gpios; 2121 l2 &= ~bank->enabled_non_wakeup_gpios; 2122 2123 if (cpu_is_omap24xx() || cpu_is_omap34xx()) { 2124 __raw_writel(l1, bank->base + 2125 OMAP24XX_GPIO_FALLINGDETECT); 2126 __raw_writel(l2, bank->base + 2127 OMAP24XX_GPIO_RISINGDETECT); 2128 } 2129 2130 if (cpu_is_omap44xx()) { 2131 __raw_writel(l1, bank->base + OMAP4_GPIO_FALLINGDETECT); 2132 __raw_writel(l2, bank->base + OMAP4_GPIO_RISINGDETECT); 2133 } 2134 2135 c++; 2136 } 2137 if (!c) { 2138 workaround_enabled = 0; 2139 return; 2140 } 2141 workaround_enabled = 1; 2142} 2143 2144void omap2_gpio_resume_after_idle(void) 2145{ 2146 int i; 2147 int min = 0; 2148 2149 if (cpu_is_omap34xx()) 2150 min = 1; 2151 for (i = min; i < gpio_bank_count; i++) { 2152 struct gpio_bank *bank = &gpio_bank[i]; 2153 u32 l, gen, gen0, gen1; 2154 2155 if (bank->dbck_enable_mask) 2156 clk_enable(bank->dbck); 2157 2158 if (!workaround_enabled) 2159 continue; 2160 2161 if (!(bank->enabled_non_wakeup_gpios)) 2162 continue; 2163 2164 if (cpu_is_omap24xx() || cpu_is_omap34xx()) { 2165 __raw_writel(bank->saved_fallingdetect, 2166 bank->base + OMAP24XX_GPIO_FALLINGDETECT); 2167 __raw_writel(bank->saved_risingdetect, 2168 bank->base + OMAP24XX_GPIO_RISINGDETECT); 2169 l = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN); 2170 } 2171 2172 if (cpu_is_omap44xx()) { 2173 __raw_writel(bank->saved_fallingdetect, 2174 bank->base + OMAP4_GPIO_FALLINGDETECT); 2175 __raw_writel(bank->saved_risingdetect, 2176 bank->base + OMAP4_GPIO_RISINGDETECT); 2177 l = __raw_readl(bank->base + OMAP4_GPIO_DATAIN); 2178 } 2179 2180 l ^= bank->saved_datain; 2181 l &= bank->enabled_non_wakeup_gpios; 2182 2183 /* 2184 * No need to generate IRQs for the rising edge for gpio IRQs 2185 * configured with falling edge only; and vice versa. 2186 */ 2187 gen0 = l & bank->saved_fallingdetect; 2188 gen0 &= bank->saved_datain; 2189 2190 gen1 = l & bank->saved_risingdetect; 2191 gen1 &= ~(bank->saved_datain); 2192 2193 gen = l & (~(bank->saved_fallingdetect) & 2194 ~(bank->saved_risingdetect)); 2195 /* Consider all GPIO IRQs needed to be updated */ 2196 gen |= gen0 | gen1; 2197 2198 if (gen) { 2199 u32 old0, old1; 2200 2201 if (cpu_is_omap24xx() || cpu_is_omap34xx()) { 2202 old0 = __raw_readl(bank->base + 2203 OMAP24XX_GPIO_LEVELDETECT0); 2204 old1 = __raw_readl(bank->base + 2205 OMAP24XX_GPIO_LEVELDETECT1); 2206 __raw_writel(old0 | gen, bank->base + 2207 OMAP24XX_GPIO_LEVELDETECT0); 2208 __raw_writel(old1 | gen, bank->base + 2209 OMAP24XX_GPIO_LEVELDETECT1); 2210 __raw_writel(old0, bank->base + 2211 OMAP24XX_GPIO_LEVELDETECT0); 2212 __raw_writel(old1, bank->base + 2213 OMAP24XX_GPIO_LEVELDETECT1); 2214 } 2215 2216 if (cpu_is_omap44xx()) { 2217 old0 = __raw_readl(bank->base + 2218 OMAP4_GPIO_LEVELDETECT0); 2219 old1 = __raw_readl(bank->base + 2220 OMAP4_GPIO_LEVELDETECT1); 2221 __raw_writel(old0 | l, bank->base + 2222 OMAP4_GPIO_LEVELDETECT0); 2223 __raw_writel(old1 | l, bank->base + 2224 OMAP4_GPIO_LEVELDETECT1); 2225 __raw_writel(old0, bank->base + 2226 OMAP4_GPIO_LEVELDETECT0); 2227 __raw_writel(old1, bank->base + 2228 OMAP4_GPIO_LEVELDETECT1); 2229 } 2230 } 2231 } 2232 2233} 2234 2235#endif 2236 2237#ifdef CONFIG_ARCH_OMAP3 2238/* save the registers of bank 2-6 */ 2239void omap_gpio_save_context(void) 2240{ 2241 int i; 2242 2243 /* saving banks from 2-6 only since GPIO1 is in WKUP */ 2244 for (i = 1; i < gpio_bank_count; i++) { 2245 struct gpio_bank *bank = &gpio_bank[i]; 2246 gpio_context[i].sysconfig = 2247 __raw_readl(bank->base + OMAP24XX_GPIO_SYSCONFIG); 2248 gpio_context[i].irqenable1 = 2249 __raw_readl(bank->base + OMAP24XX_GPIO_IRQENABLE1); 2250 gpio_context[i].irqenable2 = 2251 __raw_readl(bank->base + OMAP24XX_GPIO_IRQENABLE2); 2252 gpio_context[i].wake_en = 2253 __raw_readl(bank->base + OMAP24XX_GPIO_WAKE_EN); 2254 gpio_context[i].ctrl = 2255 __raw_readl(bank->base + OMAP24XX_GPIO_CTRL); 2256 gpio_context[i].oe = 2257 __raw_readl(bank->base + OMAP24XX_GPIO_OE); 2258 gpio_context[i].leveldetect0 = 2259 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0); 2260 gpio_context[i].leveldetect1 = 2261 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1); 2262 gpio_context[i].risingdetect = 2263 __raw_readl(bank->base + OMAP24XX_GPIO_RISINGDETECT); 2264 gpio_context[i].fallingdetect = 2265 __raw_readl(bank->base + OMAP24XX_GPIO_FALLINGDETECT); 2266 gpio_context[i].dataout = 2267 __raw_readl(bank->base + OMAP24XX_GPIO_DATAOUT); 2268 } 2269} 2270 2271/* restore the required registers of bank 2-6 */ 2272void omap_gpio_restore_context(void) 2273{ 2274 int i; 2275 2276 for (i = 1; i < gpio_bank_count; i++) { 2277 struct gpio_bank *bank = &gpio_bank[i]; 2278 __raw_writel(gpio_context[i].sysconfig, 2279 bank->base + OMAP24XX_GPIO_SYSCONFIG); 2280 __raw_writel(gpio_context[i].irqenable1, 2281 bank->base + OMAP24XX_GPIO_IRQENABLE1); 2282 __raw_writel(gpio_context[i].irqenable2, 2283 bank->base + OMAP24XX_GPIO_IRQENABLE2); 2284 __raw_writel(gpio_context[i].wake_en, 2285 bank->base + OMAP24XX_GPIO_WAKE_EN); 2286 __raw_writel(gpio_context[i].ctrl, 2287 bank->base + OMAP24XX_GPIO_CTRL); 2288 __raw_writel(gpio_context[i].oe, 2289 bank->base + OMAP24XX_GPIO_OE); 2290 __raw_writel(gpio_context[i].leveldetect0, 2291 bank->base + OMAP24XX_GPIO_LEVELDETECT0); 2292 __raw_writel(gpio_context[i].leveldetect1, 2293 bank->base + OMAP24XX_GPIO_LEVELDETECT1); 2294 __raw_writel(gpio_context[i].risingdetect, 2295 bank->base + OMAP24XX_GPIO_RISINGDETECT); 2296 __raw_writel(gpio_context[i].fallingdetect, 2297 bank->base + OMAP24XX_GPIO_FALLINGDETECT); 2298 __raw_writel(gpio_context[i].dataout, 2299 bank->base + OMAP24XX_GPIO_DATAOUT); 2300 } 2301} 2302#endif 2303 2304/* 2305 * This may get called early from board specific init 2306 * for boards that have interrupts routed via FPGA. 2307 */ 2308int __init omap_gpio_init(void) 2309{ 2310 if (!initialized) 2311 return _omap_gpio_init(); 2312 else 2313 return 0; 2314} 2315 2316static int __init omap_gpio_sysinit(void) 2317{ 2318 int ret = 0; 2319 2320 if (!initialized) 2321 ret = _omap_gpio_init(); 2322 2323 mpuio_init(); 2324 2325#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS) 2326 if (cpu_is_omap16xx() || cpu_class_is_omap2()) { 2327 if (ret == 0) { 2328 ret = sysdev_class_register(&omap_gpio_sysclass); 2329 if (ret == 0) 2330 ret = sysdev_register(&omap_gpio_device); 2331 } 2332 } 2333#endif 2334 2335 return ret; 2336} 2337 2338arch_initcall(omap_gpio_sysinit); 2339