1/* 2 * arch/arm/plat-iop/time.c 3 * 4 * Timer code for IOP32x and IOP33x based systems 5 * 6 * Author: Deepak Saxena <dsaxena@mvista.com> 7 * 8 * Copyright 2002-2003 MontaVista Software Inc. 9 * 10 * This program is free software; you can redistribute it and/or modify it 11 * under the terms of the GNU General Public License as published by the 12 * Free Software Foundation; either version 2 of the License, or (at your 13 * option) any later version. 14 */ 15 16#include <linux/kernel.h> 17#include <linux/interrupt.h> 18#include <linux/time.h> 19#include <linux/init.h> 20#include <linux/timex.h> 21#include <linux/io.h> 22#include <linux/clocksource.h> 23#include <linux/clockchips.h> 24#include <mach/hardware.h> 25#include <asm/irq.h> 26#include <asm/uaccess.h> 27#include <asm/mach/irq.h> 28#include <asm/mach/time.h> 29#include <mach/time.h> 30 31/* 32 * Minimum clocksource/clockevent timer range in seconds 33 */ 34#define IOP_MIN_RANGE 4 35 36/* 37 * IOP clocksource (free-running timer 1). 38 */ 39static cycle_t iop_clocksource_read(struct clocksource *unused) 40{ 41 return 0xffffffffu - read_tcr1(); 42} 43 44static struct clocksource iop_clocksource = { 45 .name = "iop_timer1", 46 .rating = 300, 47 .read = iop_clocksource_read, 48 .mask = CLOCKSOURCE_MASK(32), 49 .flags = CLOCK_SOURCE_IS_CONTINUOUS, 50}; 51 52/* 53 * IOP sched_clock() implementation via its clocksource. 54 */ 55unsigned long long sched_clock(void) 56{ 57 cycle_t cyc = iop_clocksource_read(NULL); 58 struct clocksource *cs = &iop_clocksource; 59 60 return clocksource_cyc2ns(cyc, cs->mult, cs->shift); 61} 62 63/* 64 * IOP clockevents (interrupting timer 0). 65 */ 66static int iop_set_next_event(unsigned long delta, 67 struct clock_event_device *unused) 68{ 69 u32 tmr = IOP_TMR_PRIVILEGED | IOP_TMR_RATIO_1_1; 70 71 BUG_ON(delta == 0); 72 write_tmr0(tmr & ~(IOP_TMR_EN | IOP_TMR_RELOAD)); 73 write_tcr0(delta); 74 write_tmr0((tmr & ~IOP_TMR_RELOAD) | IOP_TMR_EN); 75 76 return 0; 77} 78 79static unsigned long ticks_per_jiffy; 80 81static void iop_set_mode(enum clock_event_mode mode, 82 struct clock_event_device *unused) 83{ 84 u32 tmr = read_tmr0(); 85 86 switch (mode) { 87 case CLOCK_EVT_MODE_PERIODIC: 88 write_tmr0(tmr & ~IOP_TMR_EN); 89 write_tcr0(ticks_per_jiffy - 1); 90 tmr |= (IOP_TMR_RELOAD | IOP_TMR_EN); 91 break; 92 case CLOCK_EVT_MODE_ONESHOT: 93 /* ->set_next_event sets period and enables timer */ 94 tmr &= ~(IOP_TMR_RELOAD | IOP_TMR_EN); 95 break; 96 case CLOCK_EVT_MODE_RESUME: 97 tmr |= IOP_TMR_EN; 98 break; 99 case CLOCK_EVT_MODE_SHUTDOWN: 100 case CLOCK_EVT_MODE_UNUSED: 101 default: 102 tmr &= ~IOP_TMR_EN; 103 break; 104 } 105 106 write_tmr0(tmr); 107} 108 109static struct clock_event_device iop_clockevent = { 110 .name = "iop_timer0", 111 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, 112 .rating = 300, 113 .set_next_event = iop_set_next_event, 114 .set_mode = iop_set_mode, 115}; 116 117static irqreturn_t 118iop_timer_interrupt(int irq, void *dev_id) 119{ 120 struct clock_event_device *evt = dev_id; 121 122 write_tisr(1); 123 evt->event_handler(evt); 124 return IRQ_HANDLED; 125} 126 127static struct irqaction iop_timer_irq = { 128 .name = "IOP Timer Tick", 129 .handler = iop_timer_interrupt, 130 .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, 131 .dev_id = &iop_clockevent, 132}; 133 134static unsigned long iop_tick_rate; 135unsigned long get_iop_tick_rate(void) 136{ 137 return iop_tick_rate; 138} 139EXPORT_SYMBOL(get_iop_tick_rate); 140 141void __init iop_init_time(unsigned long tick_rate) 142{ 143 u32 timer_ctl; 144 145 ticks_per_jiffy = DIV_ROUND_CLOSEST(tick_rate, HZ); 146 iop_tick_rate = tick_rate; 147 148 timer_ctl = IOP_TMR_EN | IOP_TMR_PRIVILEGED | 149 IOP_TMR_RELOAD | IOP_TMR_RATIO_1_1; 150 151 /* 152 * Set up interrupting clockevent timer 0. 153 */ 154 write_tmr0(timer_ctl & ~IOP_TMR_EN); 155 setup_irq(IRQ_IOP_TIMER0, &iop_timer_irq); 156 clockevents_calc_mult_shift(&iop_clockevent, 157 tick_rate, IOP_MIN_RANGE); 158 iop_clockevent.max_delta_ns = 159 clockevent_delta2ns(0xfffffffe, &iop_clockevent); 160 iop_clockevent.min_delta_ns = 161 clockevent_delta2ns(0xf, &iop_clockevent); 162 iop_clockevent.cpumask = cpumask_of(0); 163 clockevents_register_device(&iop_clockevent); 164 write_trr0(ticks_per_jiffy - 1); 165 write_tcr0(ticks_per_jiffy - 1); 166 write_tmr0(timer_ctl); 167 168 /* 169 * Set up free-running clocksource timer 1. 170 */ 171 write_trr1(0xffffffff); 172 write_tcr1(0xffffffff); 173 write_tmr1(timer_ctl); 174 clocksource_calc_mult_shift(&iop_clocksource, tick_rate, 175 IOP_MIN_RANGE); 176 clocksource_register(&iop_clocksource); 177} 178