1/* 2 * ARM A9 MPCORE 3 * 4 * Platform hardware information and internal API 5 */ 6 7#ifndef PLAT_MPCORE_H 8#define PLAT_MPCORE_H 9 10/* MPCORE internally-connected IRQs */ 11#define MPCORE_IRQ_GLOBALTIMER 27 12#define MPCORE_IRQ_LOCALTIMER 29 13 14/* 15 NOTE: MPCORE physical based ontained at run-time, 16 while its virtual base address is set at compile-time in memory.h 17*/ 18 19/* MPCORE register offsets */ 20#define MPCORE_SCU_OFF 0x0000 /* Coherency controller */ 21#define MPCORE_GIC_CPUIF_OFF 0x0100 /* Interrupt controller CPU interface */ 22#define MPCORE_GTIMER_OFF 0x0200 /* Global timer */ 23#define MPCORE_LTIMER_OFF 0x0600 /* Local (private) timers */ 24#define MPCORE_GIC_DIST_OFF 0x1000 /* Interrupt distributor registers */ 25 26#ifndef __ASSEMBLY__ 27 28extern void __init mpcore_map_io( void ); 29extern void __init mpcore_init_gic( void ); 30extern void __init mpcore_init_timer( unsigned long periphclk_freq ); 31 32extern void __init 33 mpcore_gtimer_init( 34 void __iomem *base, 35 unsigned long freq, 36 unsigned int timer_irq); 37 38extern void __iomem * scu_base_addr(void); 39extern void __cpuinit mpcore_cpu_init(void); 40extern void plat_wake_secondary_cpu( 41 unsigned cpus, void (* _sec_entry_va)(void) ); 42 43#endif 44 45#endif /* PLAT_MPCORE_H */ 46