1/* Modified by Broadcom Corp. Portions Copyright (c) Broadcom Corp, 2012. */ 2/* 3 * Northstar PCI-Express driver 4 * Only supports Root-Complex (RC) mode 5 * 6 * Notes: 7 * PCI Domains are being used to identify the PCIe port 1:1. 8 * 9 * Only MEM access is supported, PAX does not support IO. 10 * 11 * TODO: 12 * MSI interrupts, 13 * DRAM > 128 MBytes (e.g. DMA zones) 14 */ 15 16#include <linux/init.h> 17#include <linux/kernel.h> 18#include <linux/bug.h> 19#include <linux/delay.h> 20#include <linux/pci.h> 21#include <linux/io.h> 22#include <linux/ioport.h> 23#include <linux/interrupt.h> 24 25#include <mach/memory.h> 26#include <mach/io_map.h> 27 28#include <typedefs.h> 29#include <bcmutils.h> 30#include <hndsoc.h> 31#include <siutils.h> 32#include <hndcpu.h> 33#include <hndpci.h> 34#include <pcicfg.h> 35#include <bcmdevs.h> 36#include <bcmnvram.h> 37 38/* Global SB handle */ 39extern si_t *bcm947xx_sih; 40extern spinlock_t bcm947xx_sih_lock; 41 42/* Convenience */ 43#define sih bcm947xx_sih 44#define sih_lock bcm947xx_sih_lock 45 46/* 47 * Register offset definitions 48 */ 49#define SOC_PCIE_CONTROL 0x000 /* a.k.a. CLK_CONTROL reg */ 50#define SOC_PCIE_PM_STATUS 0x008 51#define SOC_PCIE_PM_CONTROL 0x00c /* in EP mode only ! */ 52#define SOC_PCIE_RC_AXI_CONFIG 0x100 53#define SOC_PCIE_EXT_CFG_ADDR 0x120 54#define SOC_PCIE_EXT_CFG_DATA 0x124 55#define SOC_PCIE_CFG_ADDR 0x1f8 56#define SOC_PCIE_CFG_DATA 0x1fc 57 58#define SOC_PCIE_SYS_RC_INTX_EN 0x330 59#define SOC_PCIE_SYS_RC_INTX_CSR 0x334 60#define SOC_PCIE_SYS_HOST_INTR_EN 0x344 61#define SOC_PCIE_SYS_HOST_INTR_CSR 0x348 62 63#define SOC_PCIE_HDR_OFF 0x400 /* 256 bytes per function */ 64 65#define SOC_PCIE_IMAP0_0123_REGS_TYPE 0xcd0 66 67/* 32-bit 4KB in-bound mapping windows for Function 0..3, n=0..7 */ 68#define SOC_PCIE_SYS_IMAP0(f, n) (0xc00+((f)<<5)+((n)<<2)) 69/* 64-bit in-bound mapping windows for func 0..3 */ 70#define SOC_PCIE_SYS_IMAP1(f) (0xc80+((f)<<3)) 71#define SOC_PCIE_SYS_IMAP2(f) (0xcc0+((f)<<3)) 72/* 64-bit in-bound address range n=0..2 */ 73#define SOC_PCIE_SYS_IARR(n) (0xd00+((n)<<3)) 74/* 64-bit out-bound address filter n=0..2 */ 75#define SOC_PCIE_SYS_OARR(n) (0xd20+((n)<<3)) 76/* 64-bit out-bound mapping windows n=0..2 */ 77#define SOC_PCIE_SYS_OMAP(n) (0xd40+((n)<<3)) 78 79#ifdef __nonexistent_regs_ 80#define SOC_PCIE_MDIO_CONTROL 0x128 81#define SOC_PCIE_MDIO_RD_DATA 0x12c 82#define SOC_PCIE_MDIO_WR_DATA 0x130 83#define SOC_PCIE_CLK_STAT 0x1e0 84#endif 85 86extern int _memsize; 87 88#define PCI_MAX_BUS 4 89#define PLX_PRIM_SEC_BUS_NUM (0x00000201 | (PCI_MAX_BUS << 16)) 90 91#define PLX_SWITCH_ID 0x8603 92#define ASMEDIA_SWITCH_ID 0x1182 93 94static uint pcie_coreid, pcie_corerev; 95 96#ifdef CONFIG_PCI 97 98/* 99 * Forward declarations 100 */ 101static int soc_pci_setup(int nr, struct pci_sys_data *sys); 102static struct pci_bus *soc_pci_scan_bus(int nr, struct pci_sys_data *sys); 103static int soc_pcie_map_irq(struct pci_dev *dev, u8 slot, u8 pin); 104static int soc_pci_read_config(struct pci_bus *bus, unsigned int devfn, 105 int where, int size, u32 *val); 106static int soc_pci_write_config(struct pci_bus *bus, unsigned int devfn, 107 int where, int size, u32 val); 108 109#ifndef CONFIG_PCI_DOMAINS 110#error CONFIG_PCI_DOMAINS is required 111#endif 112 113static int 114sbpci_read_config_reg(struct pci_bus *bus, unsigned int devfn, int where, 115 int size, u32 *value) 116{ 117 unsigned long flags; 118 int ret; 119 120 spin_lock_irqsave(&sih_lock, flags); 121 ret = hndpci_read_config(sih, bus->number, PCI_SLOT(devfn), 122 PCI_FUNC(devfn), where, value, size); 123 spin_unlock_irqrestore(&sih_lock, flags); 124 return ret ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL; 125} 126 127static int 128sbpci_write_config_reg(struct pci_bus *bus, unsigned int devfn, int where, 129 int size, u32 value) 130{ 131 unsigned long flags; 132 int ret; 133 134 spin_lock_irqsave(&sih_lock, flags); 135 ret = hndpci_write_config(sih, bus->number, PCI_SLOT(devfn), 136 PCI_FUNC(devfn), where, &value, size); 137 spin_unlock_irqrestore(&sih_lock, flags); 138 return ret ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL; 139} 140 141static struct pci_ops pcibios_ops = { 142 sbpci_read_config_reg, 143 sbpci_write_config_reg 144}; 145 146/* 147 * PCIe host controller registers 148 * one entry per port 149 */ 150static struct resource soc_pcie_regs[3] = { 151 { 152 .name = "pcie0", 153 .start = 0x18012000, 154 .end = 0x18012fff, 155 .flags = IORESOURCE_MEM, 156 }, 157 { 158 .name = "pcie1", 159 .start = 0x18013000, 160 .end = 0x18013fff, 161 .flags = IORESOURCE_MEM, 162 }, 163 { 164 .name = "pcie2", 165 .start = 0x18014000, 166 .end = 0x18014fff, 167 .flags = IORESOURCE_MEM, 168 }, 169}; 170 171static struct resource soc_pcie_owin[3] = { 172 { 173 .name = "PCIe Outbound Window, Port 0", 174 .start = 0x08000000, 175 .end = 0x08000000 + SZ_128M - 1, 176 .flags = IORESOURCE_MEM, 177 }, 178 { 179 .name = "PCIe Outbound Window, Port 1", 180 .start = 0x40000000, 181 .end = 0x40000000 + SZ_128M - 1, 182 .flags = IORESOURCE_MEM, 183 }, 184 { 185 .name = "PCIe Outbound Window, Port 2", 186 .start = 0x48000000, 187 .end = 0x48000000 + SZ_128M - 1, 188 .flags = IORESOURCE_MEM, 189 }, 190}; 191 192/* 193 * Per port control structure 194 */ 195static struct soc_pcie_port { 196 struct resource *regs_res; 197 struct resource *owin_res; 198 void * __iomem reg_base; 199 unsigned short irqs[6]; 200 struct hw_pci hw_pci; 201 202 bool enable; 203 bool link; 204 bool isswitch; 205 bool port1active; 206 bool port2active; 207 uint16 switch_id; 208} soc_pcie_ports[4] = { 209 { 210 .irqs = {0, 0, 0, 0, 0, 0}, 211 .hw_pci = { 212 .domain = 0, 213 .swizzle = NULL, 214 .nr_controllers = 1, 215 .map_irq = NULL, 216 }, 217 .enable = 1, 218 .isswitch = 0, 219 .port1active = 0, 220 .port2active = 0, 221 }, 222 { 223 .regs_res = & soc_pcie_regs[0], 224 .owin_res = & soc_pcie_owin[0], 225 .irqs = {158, 159, 160, 161, 162, 163}, 226 .hw_pci = { 227 .domain = 1, 228 .swizzle = pci_std_swizzle, 229 .nr_controllers = 1, 230 .setup = soc_pci_setup, 231 .scan = soc_pci_scan_bus, 232 .map_irq = soc_pcie_map_irq, 233 }, 234 .enable = 1, 235 .isswitch = 0, 236 .port1active = 0, 237 .port2active = 0, 238 }, 239 { 240 .regs_res = & soc_pcie_regs[1], 241 .owin_res = & soc_pcie_owin[1], 242 .irqs = {164, 165, 166, 167, 168, 169}, 243 .hw_pci = { 244 .domain = 2, 245 .swizzle = pci_std_swizzle, 246 .nr_controllers = 1, 247 .setup = soc_pci_setup, 248 .scan = soc_pci_scan_bus, 249 .map_irq = soc_pcie_map_irq, 250 }, 251 .enable = 1, 252 .isswitch = 0, 253 .port1active = 0, 254 .port2active = 0, 255 }, 256 { 257 .regs_res = & soc_pcie_regs[2], 258 .owin_res = & soc_pcie_owin[2], 259 .irqs = {170, 171, 172, 173, 174, 175}, 260 .hw_pci = { 261 .domain = 3, 262 .swizzle = pci_std_swizzle, 263 .nr_controllers = 1, 264 .setup = soc_pci_setup, 265 .scan = soc_pci_scan_bus, 266 .map_irq = soc_pcie_map_irq, 267 }, 268 .enable = 1, 269 .isswitch = 0, 270 .port1active = 0, 271 .port2active = 0, 272 } 273 }; 274 275/* 276 * Methods for accessing configuration registers 277 */ 278static struct pci_ops soc_pcie_ops = { 279 .read = soc_pci_read_config, 280 .write = soc_pci_write_config, 281}; 282 283/* 284 * Per hnd si bus devices irq map 285 */ 286typedef struct si_bus_irq_map { 287 unsigned short device; 288 unsigned short unit; 289 unsigned short max_unit; 290 unsigned short irq; 291} si_bus_irq_map_t; 292 293si_bus_irq_map_t si_bus_irq_map[] = { 294 {BCM47XX_GMAC_ID, 0, 4, 179} /* 179, 180, 181, 182 */, 295 {BCM47XX_USB20H_ID, 0, 1, 111} /* 111 EHCI. */, 296 {BCM47XX_USB20H_ID, 0, 1, 111} /* 111 OHCI. */, 297 {BCM47XX_USB30H_ID, 0, 5, 112} /* 112, 113, 114, 115, 116. XHCI */ 298}; 299#define SI_BUS_IRQ_MAP_SIZE (sizeof(si_bus_irq_map) / sizeof(si_bus_irq_map_t)) 300 301static int si_bus_map_irq(struct pci_dev *pdev) 302{ 303 int i, irq = 0; 304 305 for (i = 0; i < SI_BUS_IRQ_MAP_SIZE; i++) { 306 if (pdev->device == si_bus_irq_map[i].device && 307 si_bus_irq_map[i].unit < si_bus_irq_map[i].max_unit) { 308 irq = si_bus_irq_map[i].irq + si_bus_irq_map[i].unit; 309 si_bus_irq_map[i].unit++; 310 break; 311 } 312 } 313 314 return irq; 315} 316 317static struct soc_pcie_port *soc_pcie_sysdata2port(struct pci_sys_data *sysdata) 318{ 319 unsigned port; 320 321 port = sysdata->domain; 322 BUG_ON(port >= ARRAY_SIZE(soc_pcie_ports)); 323 return & soc_pcie_ports[port]; 324} 325 326static struct soc_pcie_port *soc_pcie_pdev2port(struct pci_dev *pdev) 327{ 328 return soc_pcie_sysdata2port(pdev->sysdata); 329} 330 331static struct soc_pcie_port *soc_pcie_bus2port(struct pci_bus *bus) 332{ 333 return soc_pcie_sysdata2port(bus->sysdata); 334} 335 336static struct pci_bus *soc_pci_scan_bus(int nr, struct pci_sys_data *sys) 337{ 338 return pci_scan_bus(sys->busnr, &soc_pcie_ops, sys); 339} 340 341static int soc_pcie_map_irq(struct pci_dev *pdev, u8 slot, u8 pin) 342{ 343 struct soc_pcie_port *port = soc_pcie_pdev2port(pdev); 344 int irq; 345 346 irq = port->irqs[5]; /* All INTx share int src 5, last per port */ 347 348 pr_debug("PCIe map irq: %04d:%02x:%02x.%02x slot %d, pin %d, irq: %d\n", 349 pci_domain_nr(pdev->bus), 350 pdev->bus->number, 351 PCI_SLOT(pdev->devfn), 352 PCI_FUNC(pdev->devfn), 353 slot, pin, irq); 354 355 return irq; 356} 357 358static void __iomem *soc_pci_cfg_base(struct pci_bus *bus, unsigned int devfn, int where) 359{ 360 struct soc_pcie_port *port = soc_pcie_bus2port(bus); 361 int busno = bus->number; 362 int slot = PCI_SLOT(devfn); 363 int fn = PCI_FUNC(devfn); 364 void __iomem *base; 365 int offset; 366 int type; 367 u32 addr_reg; 368 369 base = port->reg_base; 370 371 /* If there is no link, just show the PCI bridge. */ 372 if (!port->link && (busno > 0 || slot > 0)) 373 return NULL; 374 375 if (busno == 0) { 376 if (slot >= 1) 377 return NULL; 378 type = slot; 379 __raw_writel(where & 0x1ffc, base + SOC_PCIE_EXT_CFG_ADDR); 380 offset = SOC_PCIE_EXT_CFG_DATA; 381 } else { 382 /* WAR for function num > 1 */ 383 if (fn > 1) 384 return NULL; 385 type = 1; 386 addr_reg = (busno & 0xff) << 20 | 387 (slot << 15) | 388 (fn << 12) | 389 (where & 0xffc) | 390 (type & 0x3); 391 392 __raw_writel(addr_reg, base + SOC_PCIE_CFG_ADDR); 393 offset = SOC_PCIE_CFG_DATA; 394 } 395 396 return base + offset; 397} 398 399static void plx_pcie_switch_init(struct pci_bus *bus, unsigned int devfn) 400{ 401 struct soc_pcie_port *port = soc_pcie_bus2port(bus); 402 u32 dRead = 0; 403 u16 bm = 0; 404 int bus_inc = 0; 405 406 soc_pci_read_config(bus, devfn, 0x100, 4, &dRead); 407 printk("PCIE: Doing PLX switch Init...Test Read = %08x\n", (unsigned int)dRead); 408 409 /* Debug control register. */ 410 soc_pci_read_config(bus, devfn, 0x1dc, 4, &dRead); 411 dRead &= ~(1<<22); 412 413 soc_pci_write_config(bus, devfn, 0x1dc, 4, dRead); 414 415 /* Set GPIO enables. */ 416 soc_pci_read_config(bus, devfn, 0x62c, 4, &dRead); 417 418 printk("PCIE: Doing PLX switch Init...GPIO Read = %08x\n", (unsigned int)dRead); 419 420 dRead &= ~((1 << 0) | (1 << 1) | (1 << 3)); 421 dRead |= ((1 << 4) | (1 << 5) | (1 << 7)); 422 423 soc_pci_write_config(bus, devfn, 0x62c, 4, dRead); 424 425 mdelay(50); 426 dRead |= ((1<<0)|(1<<1)); 427 soc_pci_write_config(bus, devfn, 0x62c, 4, dRead); 428 429 soc_pci_read_config(bus, devfn, 0x4, 2, &bm); 430#if NS_PCI_DEBUG 431 printk("bus master: %08x\n", bm); 432#endif 433 bm |= 0x06; 434 soc_pci_write_config(bus, devfn, 0x4, 2, bm); 435 bm = 0; 436#if NS_PCI_DEBUG 437 soc_pci_read_config(bus, devfn, 0x4, 2, &bm); 438 printk("bus master after: %08x\n", bm); 439 bm = 0; 440#endif 441 /* Bus 1 if the upstream port of the switch. 442 * Bus 2 has the two downstream ports, one on each device number. 443 */ 444 if (bus->number == (bus_inc + 1)) { 445 soc_pci_write_config(bus, devfn, 0x18, 4, PLX_PRIM_SEC_BUS_NUM); 446 447 /* TODO: We need to scan all outgoing windows, 448 * to look for a base limit pair for this register. 449 */ 450 /* MEM_BASE, MEM_LIM require 1MB alignment */ 451 BUG_ON((port->owin_res->start >> 16) & 0xf); 452 soc_pci_write_config(bus, devfn, PCI_MEMORY_BASE, 2, 453 port->owin_res->start >> 16); 454 BUG_ON(((port->owin_res->start + SZ_32M) >> 16) & 0xf); 455 soc_pci_write_config(bus, devfn, PCI_MEMORY_LIMIT, 2, 456 (port->owin_res->start + SZ_32M) >> 16); 457 } else if (bus->number == (bus_inc + 2)) { 458 /* TODO: I need to fix these hard coded addresses. */ 459 if (devfn == 0x8) { 460 soc_pci_write_config(bus, devfn, 0x18, 4, 461 (0x00000000 | ((bus->number + 1) << 16) | 462 ((bus->number + 1) << 8) | bus->number)); 463 BUG_ON((port->owin_res->start + SZ_48M >> 16) & 0xf); 464 soc_pci_write_config(bus, devfn, PCI_MEMORY_BASE, 2, 465 port->owin_res->start + SZ_48M >> 16); 466 BUG_ON(((port->owin_res->start + SZ_48M + SZ_32M) >> 16) & 0xf); 467 soc_pci_write_config(bus, devfn, PCI_MEMORY_LIMIT, 2, 468 (port->owin_res->start + SZ_48M + SZ_32M) >> 16); 469 soc_pci_read_config(bus, devfn, 0x7A, 2, &bm); 470 if (bm & PCI_EXP_LNKSTA_DLLLA) 471 port->port1active = 1; 472 printk("bm = %04x\n devfn = = %08x, bus = %08x\n", bm, devfn, bus->number); 473 } else if (devfn == 0x10) { 474 soc_pci_write_config(bus, devfn, 0x18, 4, 475 (0x00000000 | ((bus->number + 2) << 16) | 476 ((bus->number + 2) << 8) | bus->number)); 477 BUG_ON((port->owin_res->start + (SZ_48M * 2) >> 16) & 0xf); 478 soc_pci_write_config(bus, devfn, PCI_MEMORY_BASE, 2, 479 port->owin_res->start + (SZ_48M * 2) >> 16); 480 BUG_ON(((port->owin_res->start + (SZ_48M * 2) + SZ_32M) >> 16) & 0xf); 481 soc_pci_write_config(bus, devfn, PCI_MEMORY_LIMIT, 2, 482 (port->owin_res->start + (SZ_48M * 2) + SZ_32M) >> 16); 483 soc_pci_read_config(bus, devfn, 0x7A, 2, &bm); 484 if (bm & PCI_EXP_LNKSTA_DLLLA) 485 port->port2active = 1; 486 printk("bm = %04x\n devfn = = %08x, bus = %08x\n", bm, devfn, bus->number); 487 } 488 } 489} 490 491static void 492asmedia_pcie_switch_init(struct pci_bus *bus, unsigned int devfn) 493{ 494 struct soc_pcie_port *port = soc_pcie_bus2port(bus); 495 u32 dRead = 0; 496 u16 bm = 0; 497 int bus_inc = 0; 498 499 soc_pci_read_config(bus, devfn, 0x100, 4, &dRead); 500 printk("PCIE: Doing ASMedia switch Init...Test Read = %08x\n", (unsigned int)dRead); 501 502 soc_pci_read_config(bus, devfn, 0x4, 2, &bm); 503#if NS_PCI_DEBUG 504 printk("bus master: %08x\n", bm); 505#endif 506 bm |= 0x06; 507 soc_pci_write_config(bus, devfn, 0x4, 2, bm); 508 bm = 0; 509#if NS_PCI_DEBUG 510 soc_pci_read_config(bus, devfn, 0x4, 2, &bm); 511 printk("bus master after: %08x\n", bm); 512 bm = 0; 513#endif 514 515 /* Bus 1 is the upstream port of the switch. 516 * Bus 2 has the two downstream ports, one on each device number. 517 */ 518 if (bus->number == (bus_inc + 1)) { 519 /* Upstream port */ 520 soc_pci_write_config(bus, devfn, 0x18, 4, (0x00000201 | (PCI_MAX_BUS << 16))); 521 522 /* MEM_BASE, MEM_LIM require 1MB alignment */ 523 BUG_ON((port->owin_res->start >> 16) & 0xf); 524 soc_pci_write_config(bus, devfn, PCI_MEMORY_BASE, 2, 525 port->owin_res->start >> 16); 526 BUG_ON(((port->owin_res->start + SZ_32M) >> 16) & 0xf); 527 soc_pci_write_config(bus, devfn, PCI_MEMORY_LIMIT, 2, 528 (port->owin_res->start + SZ_32M) >> 16); 529 530 printk("bm = %04x\n devfn = = %08x, bus = %08x\n", bm, devfn, bus->number); 531 } else if (bus->number == (bus_inc + 2)) { 532 /* Downstream ports */ 533 if (devfn == 0x18) { 534 soc_pci_write_config(bus, devfn, 0x18, 4, 535 (0x00000000 | ((bus->number + 1) << 16) | 536 ((bus->number + 1) << 8) | bus->number)); 537 BUG_ON((port->owin_res->start + SZ_48M >> 16) & 0xf); 538 soc_pci_write_config(bus, devfn, PCI_MEMORY_BASE, 2, 539 port->owin_res->start + SZ_48M >> 16); 540 BUG_ON(((port->owin_res->start + SZ_48M + SZ_32M) >> 16) & 0xf); 541 soc_pci_write_config(bus, devfn, PCI_MEMORY_LIMIT, 2, 542 (port->owin_res->start + SZ_48M + SZ_32M) >> 16); 543 544 soc_pci_read_config(bus, devfn, 0x92, 2, &bm); 545 if (bm & PCI_EXP_LNKSTA_DLLLA) 546 port->port1active = 1; 547 548 printk("bm = %04x\n devfn = = %08x, bus = %08x\n", bm, devfn, bus->number); 549 } else if (devfn == 0x38) { 550 soc_pci_write_config(bus, devfn, 0x18, 4, 551 (0x00000000 | ((bus->number + 2) << 16) | 552 ((bus->number + 2) << 8) | bus->number)); 553 BUG_ON((port->owin_res->start + (SZ_48M * 2) >> 16) & 0xf); 554 soc_pci_write_config(bus, devfn, PCI_MEMORY_BASE, 2, 555 port->owin_res->start + (SZ_48M * 2) >> 16); 556 BUG_ON(((port->owin_res->start + (SZ_48M * 2) + SZ_32M) >> 16) & 0xf); 557 soc_pci_write_config(bus, devfn, PCI_MEMORY_LIMIT, 2, 558 (port->owin_res->start + (SZ_48M * 2) + SZ_32M) >> 16); 559 560 soc_pci_read_config(bus, devfn, 0x92, 2, &bm); 561 if (bm & PCI_EXP_LNKSTA_DLLLA) 562 port->port2active = 1; 563 564 printk("bm = %04x\n devfn = = %08x, bus = %08x\n", bm, devfn, bus->number); 565 } 566 } 567} 568 569static int soc_pci_read_config(struct pci_bus *bus, unsigned int devfn, 570 int where, int size, u32 *val) 571{ 572 void __iomem *base; 573 u32 data_reg; 574 struct soc_pcie_port *port = soc_pcie_bus2port(bus); 575 int bus_inc = 0; 576 577 if ((bus->number > (bus_inc + 4))) { 578 *val = ~0UL; 579 return PCIBIOS_SUCCESSFUL; 580 } 581 582 if (port->isswitch == 1) { 583 if (bus->number == (bus_inc + 2)) { 584 if (port->switch_id == PLX_SWITCH_ID && 585 !((devfn == 0x8) || (devfn == 0x10))) { 586 *val = ~0UL; 587 return PCIBIOS_SUCCESSFUL; 588 } else if (port->switch_id == ASMEDIA_SWITCH_ID && 589 !((devfn == 0x18) || (devfn == 0x38))) { 590 *val = ~0UL; 591 return PCIBIOS_SUCCESSFUL; 592 } 593 } else if ((bus->number == (bus_inc + 3)) || (bus->number == (bus_inc + 4))) { 594 if (devfn != 0) { 595 *val = ~0UL; 596 return PCIBIOS_SUCCESSFUL; 597 } else if ((bus->number == (bus_inc + 3)) && (port->port1active == 0)) { 598 *val = ~0UL; 599 return PCIBIOS_SUCCESSFUL; 600 } else if ((bus->number == (bus_inc + 4)) && (port->port2active == 0)) { 601 *val = ~0UL; 602 return PCIBIOS_SUCCESSFUL; 603 } 604 } 605 } 606 607 base = soc_pci_cfg_base(bus, devfn, where); 608 if (base == NULL) { 609 *val = ~0UL; 610 return PCIBIOS_SUCCESSFUL; 611 } 612 613 data_reg = __raw_readl(base); 614 615 /* NS: CLASS field is R/O, and set to wrong 0x200 value */ 616 if (bus->number == 0 && devfn == 0) { 617 if ((where & 0xffc) == PCI_CLASS_REVISION) { 618 /* 619 * RC's class is 0x0280, but Linux PCI driver needs 0x604 620 * for a PCIe bridge. So we must fixup the class code 621 * to 0x604 here. 622 */ 623 data_reg &= 0xff; 624 data_reg |= 0x604 << 16; 625 } 626 } 627 628 if ((bus->number == (bus_inc + 1)) && (port->isswitch == 0) && 629 (where == 0) && (((data_reg >> 16) & 0xFFFF) == PLX_SWITCH_ID)) { 630 plx_pcie_switch_init(bus, devfn); 631 port->switch_id = PLX_SWITCH_ID; 632 port->isswitch = 1; 633 } else if ((bus->number == (bus_inc + 1)) && (port->isswitch == 0) && 634 (where == 0) && (((data_reg >> 16) & 0xFFFF) == ASMEDIA_SWITCH_ID)) { 635 asmedia_pcie_switch_init(bus, devfn); 636 port->switch_id = ASMEDIA_SWITCH_ID; 637 port->isswitch = 1; 638 } 639 if ((bus->number == (bus_inc + 2)) && (port->isswitch == 1) && 640 (where == 0) && (((data_reg >> 16) & 0xFFFF) == PLX_SWITCH_ID)) { 641 plx_pcie_switch_init(bus, devfn); 642 } else if ((bus->number == (bus_inc + 2)) && (port->isswitch == 1) && 643 (where == 0) && (((data_reg >> 16) & 0xFFFF) == ASMEDIA_SWITCH_ID)) { 644 asmedia_pcie_switch_init(bus, devfn); 645 } 646 647 /* HEADER_TYPE=00 indicates the port in EP mode */ 648 649 if (size == 4) { 650 *val = data_reg; 651 } else if (size < 4) { 652 u32 mask = (1 << (size * 8)) - 1; 653 int shift = (where % 4) * 8; 654 *val = (data_reg >> shift) & mask; 655 } 656 657 return PCIBIOS_SUCCESSFUL; 658} 659 660static int soc_pci_write_config(struct pci_bus *bus, unsigned int devfn, 661 int where, int size, u32 val) 662{ 663 void __iomem *base; 664 u32 data_reg; 665 struct soc_pcie_port *port = soc_pcie_bus2port(bus); 666 int bus_inc = 0; 667 668 if (bus->number > (bus_inc + 4)) 669 return PCIBIOS_SUCCESSFUL; 670 671 if ((bus->number == (bus_inc + 2)) && (port->isswitch == 1)) { 672 if (port->switch_id == PLX_SWITCH_ID && !((devfn == 0x8) || (devfn == 0x10))) { 673 return PCIBIOS_SUCCESSFUL; 674 } else if (port->switch_id == ASMEDIA_SWITCH_ID && 675 !((devfn == 0x18) || (devfn == 0x38))) { 676 return PCIBIOS_SUCCESSFUL; 677 } 678 } 679 else if ((bus->number == (bus_inc + 3)) && (port->isswitch == 1)) { 680 if (devfn != 0) 681 return PCIBIOS_SUCCESSFUL; 682 } 683 else if ((bus->number == (bus_inc + 4)) && (port->isswitch == 1)) { 684 if (devfn != 0) 685 return PCIBIOS_SUCCESSFUL; 686 } 687 688 base = soc_pci_cfg_base(bus, devfn, where); 689 if (base == NULL) { 690 return PCIBIOS_SUCCESSFUL; 691 } 692 693 if (size < 4) { 694 u32 mask = (1 << (size * 8)) - 1; 695 int shift = (where % 4) * 8; 696 data_reg = __raw_readl(base); 697 data_reg &= ~(mask << shift); 698 data_reg |= (val & mask) << shift; 699 } else { 700 data_reg = val; 701 } 702 703 __raw_writel(data_reg, base); 704 705 return PCIBIOS_SUCCESSFUL; 706} 707 708static int soc_pci_setup(int nr, struct pci_sys_data *sys) 709{ 710 struct soc_pcie_port *port = soc_pcie_sysdata2port(sys); 711 712 BUG_ON(request_resource(&iomem_resource, port->owin_res)); 713 714 sys->resource[0] = port->owin_res; 715 sys->private_data = port; 716 return 1; 717} 718 719/* 720 * Check link status, return 0 if link is up in RC mode, 721 * otherwise return non-zero 722 */ 723static int __init noinline soc_pcie_check_link(struct soc_pcie_port *port, uint32 allow_gen2) 724{ 725 u32 devfn = 0; 726 u16 pos, tmp16; 727 u8 nlw, tmp8; 728 u32 tmp32; 729 730 struct pci_sys_data sd = { 731 .domain = port->hw_pci.domain, 732 }; 733 struct pci_bus bus = { 734 .number = 0, 735 .ops = &soc_pcie_ops, 736 .sysdata = &sd, 737 }; 738 739 if (!port->enable) 740 return -EINVAL; 741 742 743 pci_bus_read_config_dword(&bus, devfn, 0xdc, &tmp32); 744 tmp32 &= ~0xf; 745 if (allow_gen2) 746 tmp32 |= 2; 747 else { 748 /* force PCIE GEN1 */ 749 tmp32 |= 1; 750 } 751 pci_bus_write_config_dword(&bus, devfn, 0xdc, tmp32); 752 753 /* See if the port is in EP mode, indicated by header type 00 */ 754 pci_bus_read_config_byte(&bus, devfn, PCI_HEADER_TYPE, &tmp8); 755 if (tmp8 != PCI_HEADER_TYPE_BRIDGE) { 756 pr_info("PCIe port %d in End-Point mode - ignored\n", 757 port->hw_pci.domain); 758 return -ENODEV; 759 } 760 761 /* NS PAX only changes NLW field when card is present */ 762 pos = pci_bus_find_capability(&bus, devfn, PCI_CAP_ID_EXP); 763 pci_bus_read_config_word(&bus, devfn, pos + PCI_EXP_LNKSTA, &tmp16); 764 765#ifdef DEBUG 766 pr_debug("PCIE%d: LINKSTA reg %#x val %#x\n", port->hw_pci.domain, 767 pos+PCI_EXP_LNKSTA, tmp16); 768#endif 769 770 nlw = (tmp16 & PCI_EXP_LNKSTA_NLW) >> PCI_EXP_LNKSTA_NLW_SHIFT; 771 port->link = tmp16 & PCI_EXP_LNKSTA_DLLLA; 772 773 if (nlw != 0) 774 port->link = 1; 775 776#ifdef DEBUG 777 for (; pos < 0x100; pos += 2) { 778 pci_bus_read_config_word(&bus, devfn, pos, &tmp16); 779 if (tmp16) 780 pr_debug("reg[%#x]=%#x, ", pos, tmp16); 781 } 782#endif 783 pr_info("PCIE%d link=%d\n", port->hw_pci.domain, port->link); 784 785 return ((port->link)? 0: -ENOSYS); 786} 787 788/* 789 * Initializte the PCIe controller 790 */ 791static void __init soc_pcie_hw_init(struct soc_pcie_port *port) 792{ 793 u32 devfn = 0; 794 u32 tmp32; 795 struct pci_sys_data sd = { 796 .domain = port->hw_pci.domain, 797 }; 798 struct pci_bus bus = { 799 .number = 0, 800 .ops = &soc_pcie_ops, 801 .sysdata = &sd, 802 }; 803 804 /* Change MPS and MRRS to 512 */ 805 pci_bus_read_config_word(&bus, devfn, 0x4d4, &tmp32); 806 tmp32 &= ~7; 807 tmp32 |= 2; 808 pci_bus_write_config_word(&bus, devfn, 0x4d4, tmp32); 809 810 pci_bus_read_config_dword(&bus, devfn, 0xb4, &tmp32); 811 tmp32 &= ~((7 << 12) | (7 << 5)); 812 tmp32 |= (2 << 12) | (2 << 5); 813 pci_bus_write_config_dword(&bus, devfn, 0xb4, tmp32); 814 815 /* Turn-on Root-Complex (RC) mode, from reset defailt of EP */ 816 817 /* The mode is set by straps, can be overwritten via DMU 818 register <cru_straps_control> bit 5, "1" means RC 819 */ 820 821 /* Send a downstream reset */ 822 __raw_writel(0x3, port->reg_base + SOC_PCIE_CONTROL); 823 udelay(250); 824 __raw_writel(0x1, port->reg_base + SOC_PCIE_CONTROL); 825 mdelay(250); 826 827 if (ACP_WAR_ENAB() || arch_is_coherent()) { 828 /* Set ARCACHE to 0xb, and AWCACHE to 0x7, ARUSER to 0x1, and AWUSER to 0x1 829 * ARCACHE=0xb - Cacheable write-back, allocate on write 830 * AWCACHE=0x7 - Cacheable write-back, allocate on read 831 */ 832 tmp32 = ((0x7 << 14) | (0x1 << 9) | (0xb << 5) | (0x1 << 0)); 833 __raw_writel(tmp32, port->reg_base + SOC_PCIE_RC_AXI_CONFIG); 834 udelay(250); 835 } 836 837 /* TBD: take care of PM, check we're on */ 838} 839 840/* 841 * Setup the address translation 842 */ 843static void __init soc_pcie_map_init(struct soc_pcie_port *port) 844{ 845 unsigned size, i; 846 u32 addr; 847 848 /* 849 * NOTE: 850 * All PCI-to-CPU address mapping are 1:1 for simplicity 851 */ 852 853 /* Outbound address translation setup */ 854 size = resource_size(port->owin_res); 855 addr = port->owin_res->start; 856 BUG_ON(!addr); 857 BUG_ON(addr & ((1 << 25) - 1)); /* 64MB alignment */ 858 859 for (i = 0; i < 3; i++) { 860 const unsigned win_size = SZ_64M; 861 /* 64-bit LE regs, write low word, high is 0 at reset */ 862 __raw_writel(addr, port->reg_base + SOC_PCIE_SYS_OMAP(i)); 863 __raw_writel(addr|0x1, port->reg_base + SOC_PCIE_SYS_OARR(i)); 864 addr += win_size; 865 if (size >= win_size) 866 size -= win_size; 867 if (size == 0) 868 break; 869 } 870 WARN_ON(size > 0); 871 872 if (pcie_coreid == NS_PCIEG2_CORE_ID && pcie_corerev == 0x7) { 873 /* Enable FUNC0_IMAP0_0/1/2/3 from RO to RW for NS-B0 */ 874 __raw_writel(0x1, port->reg_base + SOC_PCIE_IMAP0_0123_REGS_TYPE); 875 /* 4KB memory page pointing to CCB for NS-B0 */ 876 addr = (0x18001 << 12) | 0x1; 877 __raw_writel(addr, port->reg_base + SOC_PCIE_SYS_IMAP0(0, 1)); 878 } 879 880 /* 881 * Inbound address translation setup 882 * Northstar only maps up to 128 MiB inbound, DRAM could be up to 1 GiB. 883 * 884 * For now allow access to entire DRAM, assuming it is less than 128MiB, 885 * otherwise DMA bouncing mechanism may be required. 886 * Also consider DMA mask to limit DMA physical address 887 */ 888 if (arch_is_coherent()) { 889 /* Using IARR_2/IMAP_2 is enough since it supports up to 2GB for NS-B0 */ 890 addr = DDR_PADDR_ACP; 891 __raw_writel(addr | 0x1, 892 port->reg_base + SOC_PCIE_SYS_IMAP2(0)); 893 __raw_writel(addr | 0x1, /* 1GB size */ 894 port->reg_base + SOC_PCIE_SYS_IARR(2)); 895 return; 896 } 897 898 size = min(_memsize, SZ_128M); 899 addr = PHYS_OFFSET; 900 901 size >>= 20; /* In MB */ 902 size &= 0xff; /* Size is an 8-bit field */ 903 904 WARN_ON(size == 0); 905 /* 64-bit LE regs, write low word, high is 0 at reset */ 906 __raw_writel(addr | 0x1, 907 port->reg_base + SOC_PCIE_SYS_IMAP1(0)); 908 __raw_writel(addr | size, 909 port->reg_base + SOC_PCIE_SYS_IARR(1)); 910 911 if (_memsize <= SZ_128M) 912 return; 913 914#ifdef CONFIG_SPARSEMEM 915 /* DDR memory size > 128MB */ 916 addr = PHYS_OFFSET2; 917 918 if (pcie_coreid == NS_PCIEG2_CORE_ID && pcie_corerev == 0x7) { 919 /* Means 1GB for NS-B0 IARR_2 */ 920 size = 1; 921 } else { 922 size = min(_memsize - SZ_128M, SZ_128M); 923 size >>= 20; /* In MB */ 924 size &= 0xff; /* Size is an 8-bit field */ 925 } 926 __raw_writel(addr | 0x1, 927 port->reg_base + SOC_PCIE_SYS_IMAP2(0)); 928 __raw_writel(addr | size, 929 port->reg_base + SOC_PCIE_SYS_IARR(2)); 930#endif 931} 932 933/* 934 * Setup PCIE Host bridge 935 */ 936static void __init noinline soc_pcie_bridge_init(struct soc_pcie_port *port) 937{ 938 u32 devfn = 0; 939 u8 tmp8; 940 u16 tmp16; 941 942 /* Fake <bus> object */ 943 struct pci_sys_data sd = { 944 .domain = port->hw_pci.domain, 945 }; 946 struct pci_bus bus = { 947 .number = 0, 948 .ops = &soc_pcie_ops, 949 .sysdata = &sd, 950 }; 951 952 953 pci_bus_write_config_byte(&bus, devfn, PCI_PRIMARY_BUS, 0); 954 pci_bus_write_config_byte(&bus, devfn, PCI_SECONDARY_BUS, 1); 955 pci_bus_write_config_byte(&bus, devfn, PCI_SUBORDINATE_BUS, 4); 956 957 pci_bus_read_config_byte(&bus, devfn, PCI_PRIMARY_BUS, &tmp8); 958 pci_bus_read_config_byte(&bus, devfn, PCI_SECONDARY_BUS, &tmp8); 959 pci_bus_read_config_byte(&bus, devfn, PCI_SUBORDINATE_BUS, &tmp8); 960 961 /* MEM_BASE, MEM_LIM require 1MB alignment */ 962 BUG_ON((port->owin_res->start >> 16) & 0xf); 963#ifdef DEBUG 964 pr_debug("%s: membase %#x memlimit %#x\n", __FUNCTION__, 965 port->owin_res->start, port->owin_res->end+1); 966#endif 967 pci_bus_write_config_word(&bus, devfn, PCI_MEMORY_BASE, 968 port->owin_res->start >> 16); 969 BUG_ON(((port->owin_res->end+1) >> 16) & 0xf); 970 pci_bus_write_config_word(&bus, devfn, PCI_MEMORY_LIMIT, 971 (port->owin_res->end+1) >> 16); 972 973 /* These registers are not supported on the NS */ 974 pci_bus_write_config_word(&bus, devfn, PCI_IO_BASE_UPPER16, 0); 975 pci_bus_write_config_word(&bus, devfn, PCI_IO_LIMIT_UPPER16, 0); 976 977 /* Force class to that of a Bridge */ 978 pci_bus_write_config_word(&bus, devfn, PCI_CLASS_DEVICE, PCI_CLASS_BRIDGE_PCI); 979 980 pci_bus_read_config_word(&bus, devfn, PCI_CLASS_DEVICE, &tmp16); 981 pci_bus_read_config_word(&bus, devfn, PCI_MEMORY_BASE, &tmp16); 982 pci_bus_read_config_word(&bus, devfn, PCI_MEMORY_LIMIT, &tmp16); 983} 984 985 986int 987pcibios_enable_resources(struct pci_dev *dev) 988{ 989 u16 cmd, old_cmd; 990 int idx; 991 struct resource *r; 992 993 /* External PCI only */ 994 if (dev->bus->number == 0) 995 return 0; 996 997 pci_read_config_word(dev, PCI_COMMAND, &cmd); 998 old_cmd = cmd; 999 for (idx = 0; idx < 6; idx++) { 1000 r = &dev->resource[idx]; 1001 if (r->flags & IORESOURCE_IO) 1002 cmd |= PCI_COMMAND_IO; 1003 if (r->flags & IORESOURCE_MEM) 1004 cmd |= PCI_COMMAND_MEMORY; 1005 } 1006 if (dev->resource[PCI_ROM_RESOURCE].start) 1007 cmd |= PCI_COMMAND_MEMORY; 1008 if (cmd != old_cmd) { 1009 printk("PCI: Enabling device %s (%04x -> %04x)\n", pci_name(dev), old_cmd, cmd); 1010 pci_write_config_word(dev, PCI_COMMAND, cmd); 1011 } 1012 return 0; 1013} 1014 1015static void 1016bcm5301x_usb_power_on(int coreid) 1017{ 1018 int enable_usb; 1019 1020 /* foxconn modified start, 09/10/2013, enable usb later to avoid boot up failed if USB 3.0 storage is connected to USB 3.0 port */ 1021 if (coreid == NS_USB20_CORE_ID) { 1022 enable_usb = getgpiopin(NULL, "usbport1", GPIO_PIN_NOTDEFINED); 1023 if (enable_usb != GPIO_PIN_NOTDEFINED) { 1024 int enable_usb_mask = 1 << enable_usb; 1025 1026 si_gpioout(sih, enable_usb_mask, enable_usb_mask, GPIO_DRV_PRIORITY); 1027 si_gpioouten(sih, enable_usb_mask, enable_usb_mask, GPIO_DRV_PRIORITY); 1028 } 1029 1030 enable_usb = getgpiopin(NULL, "usbport2", GPIO_PIN_NOTDEFINED); 1031 if (enable_usb != GPIO_PIN_NOTDEFINED) { 1032 int enable_usb_mask = 1 << enable_usb; 1033 1034 si_gpioout(sih, enable_usb_mask, enable_usb_mask, GPIO_DRV_PRIORITY); 1035 si_gpioouten(sih, enable_usb_mask, enable_usb_mask, GPIO_DRV_PRIORITY); 1036 } 1037 } 1038 else if (coreid == NS_USB30_CORE_ID) { 1039 1040 enable_usb = getgpiopin(NULL, "usbport1", GPIO_PIN_NOTDEFINED); 1041 if (enable_usb != GPIO_PIN_NOTDEFINED) { 1042 int enable_usb_mask = 1 << enable_usb; 1043 1044 si_gpioout(sih, enable_usb_mask, enable_usb_mask, GPIO_DRV_PRIORITY); 1045 si_gpioouten(sih, enable_usb_mask, enable_usb_mask, GPIO_DRV_PRIORITY); 1046 } 1047 enable_usb = getgpiopin(NULL, "usbport2", GPIO_PIN_NOTDEFINED); 1048 if (enable_usb != GPIO_PIN_NOTDEFINED) { 1049 int enable_usb_mask = 1 << enable_usb; 1050 1051 si_gpioout(sih, enable_usb_mask, enable_usb_mask, GPIO_DRV_PRIORITY); 1052 si_gpioouten(sih, enable_usb_mask, enable_usb_mask, GPIO_DRV_PRIORITY); 1053 } 1054 } 1055 /* foxconn modified end, 09/10/2013, enable usb later to avoid boot up failed if USB 3.0 storage is connected to USB 3.0 port*/ 1056} 1057 1058static void 1059bcm5301x_usb20_phy_init(void) 1060{ 1061 uint32 dmu_base; 1062 uint32 *cru_clkset_key; 1063 uint32 *cru_usb2_control; 1064 1065 /* Check Chip ID */ 1066 if (!BCM4707_CHIP(CHIPID(sih->chip))) 1067 return; 1068 1069 /* Check Package ID */ 1070 if (sih->chippkg == BCM4709_PKG_ID) { 1071 return; 1072 } 1073 else if (sih->chippkg == BCM4707_PKG_ID || sih->chippkg == BCM4708_PKG_ID) { 1074 dmu_base = (uint32)REG_MAP(0x1800c000, 4096); 1075 cru_clkset_key = (uint32 *)(dmu_base + 0x180); 1076 cru_usb2_control = (uint32 *)(dmu_base + 0x164); 1077 1078 /* unlock */ 1079 writel(0x0000ea68, cru_clkset_key); 1080 1081 /* fill value */ 1082 writel(0x00dd10c3, cru_usb2_control); 1083 1084 /* lock */ 1085 writel(0x00000000, cru_clkset_key); 1086 1087 REG_UNMAP((void *)dmu_base); 1088 } 1089} 1090 1091static void 1092bcm5301x_usb30_phy_init(void) 1093{ 1094 uint32 ccb_mii_base; 1095 uint32 dmu_base; 1096 uint32 *ccb_mii_mng_ctrl_addr; 1097 uint32 *ccb_mii_mng_cmd_data_addr; 1098 uint32 *cru_rst_addr; 1099 uint32 cru_straps_ctrl; 1100 uint32 usb3_idm_idm_base; 1101 uint32 *usb3_idm_idm_reset_ctrl_addr; 1102 1103 /* Check Chip ID */ 1104 if (!BCM4707_CHIP(CHIPID(sih->chip))) 1105 return; 1106 1107 dmu_base = (uint32)REG_MAP(0x1800c000, 4096); 1108 /* Check strapping of PCIE/USB3 SEL */ 1109 cru_straps_ctrl = readl((uint32 *)(dmu_base + 0x2a0)); 1110 if ((cru_straps_ctrl & 0x10) == 0) 1111 goto out; 1112 cru_rst_addr = (uint32 *)(dmu_base + 0x184); 1113 1114 /* Reg map */ 1115 ccb_mii_base = (uint32)REG_MAP(0x18003000, 4096); 1116 ccb_mii_mng_ctrl_addr = (uint32 *)(ccb_mii_base + 0x0); 1117 ccb_mii_mng_cmd_data_addr = (uint32 *)(ccb_mii_base + 0x4); 1118 usb3_idm_idm_base = (uint32)REG_MAP(0x18105000, 4096); 1119 usb3_idm_idm_reset_ctrl_addr = (uint32 *)(usb3_idm_idm_base + 0x800); 1120 1121 /* Perform USB3 system soft reset */ 1122 writel(0x00000001, usb3_idm_idm_reset_ctrl_addr); 1123 1124 /* Enable MDIO. Setting MDCDIV as 26 */ 1125 writel(0x0000009a, ccb_mii_mng_ctrl_addr); 1126 OSL_DELAY(2); 1127 1128 if (CHIPID(sih->chip) == BCM4707_CHIP_ID) { 1129 /* Chiprev 4 for NS-B0 and chiprev 6 for NS-B1 */ 1130 if (CHIPREV(sih->chiprev) == 4 || CHIPREV(sih->chiprev) == 6) { 1131 /* USB3 PLL Block */ 1132 SPINWAIT((((readl(ccb_mii_mng_ctrl_addr) >> 8) & 1) == 1), 1000); 1133 writel(0x587e8000, ccb_mii_mng_cmd_data_addr); 1134 1135 /* Clear ana_pllSeqStart */ 1136 SPINWAIT((((readl(ccb_mii_mng_ctrl_addr) >> 8) & 1) == 1), 1000); 1137 writel(0x58061000, ccb_mii_mng_cmd_data_addr); 1138 1139 /* CMOS Divider ratio to 25 */ 1140 SPINWAIT((((readl(ccb_mii_mng_ctrl_addr) >> 8) & 1) == 1), 1000); 1141 writel(0x582a6400, ccb_mii_mng_cmd_data_addr); 1142 1143 /* Asserting PLL Reset */ 1144 SPINWAIT((((readl(ccb_mii_mng_ctrl_addr) >> 8) & 1) == 1), 1000); 1145 writel(0x582ec000, ccb_mii_mng_cmd_data_addr); 1146 1147 /* Deaaserting PLL Reset */ 1148 SPINWAIT((((readl(ccb_mii_mng_ctrl_addr) >> 8) & 1) == 1), 1000); 1149 writel(0x582e8000, ccb_mii_mng_cmd_data_addr); 1150 1151 /* Deasserting USB3 system reset */ 1152 writel(0x00000000, usb3_idm_idm_reset_ctrl_addr); 1153 1154 /* Set ana_pllSeqStart */ 1155 SPINWAIT((((readl(ccb_mii_mng_ctrl_addr) >> 8) & 1) == 1), 1000); 1156 writel(0x58069000, ccb_mii_mng_cmd_data_addr); 1157 1158 /* RXPMD block */ 1159 SPINWAIT((((readl(ccb_mii_mng_ctrl_addr) >> 8) & 1) == 1), 1000); 1160 writel(0x587e8020, ccb_mii_mng_cmd_data_addr); 1161 1162 /* CDR int loop locking BW to 1 */ 1163 SPINWAIT((((readl(ccb_mii_mng_ctrl_addr) >> 8) & 1) == 1), 1000); 1164 writel(0x58120049, ccb_mii_mng_cmd_data_addr); 1165 1166 /* CDR int loop acquisition BW to 1 */ 1167 SPINWAIT((((readl(ccb_mii_mng_ctrl_addr) >> 8) & 1) == 1), 1000); 1168 writel(0x580e0049, ccb_mii_mng_cmd_data_addr); 1169 1170 /* CDR prop loop BW to 1 */ 1171 SPINWAIT((((readl(ccb_mii_mng_ctrl_addr) >> 8) & 1) == 1), 1000); 1172 writel(0x580a005c, ccb_mii_mng_cmd_data_addr); 1173 1174 /* Waiting MII Mgt interface idle */ 1175 SPINWAIT((((readl(ccb_mii_mng_ctrl_addr) >> 8) & 1) == 1), 1000); 1176 } else { 1177 /* PLL30 block */ 1178 SPINWAIT((((readl(ccb_mii_mng_ctrl_addr) >> 8) & 1) == 1), 1000); 1179 writel(0x587e8000, ccb_mii_mng_cmd_data_addr); 1180 1181 SPINWAIT((((readl(ccb_mii_mng_ctrl_addr) >> 8) & 1) == 1), 1000); 1182 writel(0x582a6400, ccb_mii_mng_cmd_data_addr); 1183 1184 SPINWAIT((((readl(ccb_mii_mng_ctrl_addr) >> 8) & 1) == 1), 1000); 1185 writel(0x587e80e0, ccb_mii_mng_cmd_data_addr); 1186 1187 SPINWAIT((((readl(ccb_mii_mng_ctrl_addr) >> 8) & 1) == 1), 1000); 1188 writel(0x580a009c, ccb_mii_mng_cmd_data_addr); 1189 1190 /* Enable SSC */ 1191 SPINWAIT((((readl(ccb_mii_mng_ctrl_addr) >> 8) & 1) == 1), 1000); 1192 writel(0x587e8040, ccb_mii_mng_cmd_data_addr); 1193 1194 SPINWAIT((((readl(ccb_mii_mng_ctrl_addr) >> 8) & 1) == 1), 1000); 1195 writel(0x580a21d3, ccb_mii_mng_cmd_data_addr); 1196 1197 SPINWAIT((((readl(ccb_mii_mng_ctrl_addr) >> 8) & 1) == 1), 1000); 1198 writel(0x58061003, ccb_mii_mng_cmd_data_addr); 1199 1200 /* Waiting MII Mgt interface idle */ 1201 SPINWAIT((((readl(ccb_mii_mng_ctrl_addr) >> 8) & 1) == 1), 1000); 1202 1203 /* Deasserting USB3 system reset */ 1204 writel(0x00000000, usb3_idm_idm_reset_ctrl_addr); 1205 } 1206 } 1207 else if (CHIPID(sih->chip) == BCM53018_CHIP_ID) { 1208 /* USB3 PLL Block */ 1209 SPINWAIT((((readl(ccb_mii_mng_ctrl_addr) >> 8) & 1) == 1), 1000); 1210 writel(0x587e8000, ccb_mii_mng_cmd_data_addr); 1211 1212 /* Assert Ana_Pllseq start */ 1213 SPINWAIT((((readl(ccb_mii_mng_ctrl_addr) >> 8) & 1) == 1), 1000); 1214 writel(0x58061000, ccb_mii_mng_cmd_data_addr); 1215 1216 /* Assert CML Divider ratio to 26 */ 1217 SPINWAIT((((readl(ccb_mii_mng_ctrl_addr) >> 8) & 1) == 1), 1000); 1218 writel(0x582a6400, ccb_mii_mng_cmd_data_addr); 1219 1220 /* Asserting PLL Reset */ 1221 SPINWAIT((((readl(ccb_mii_mng_ctrl_addr) >> 8) & 1) == 1), 1000); 1222 writel(0x582ec000, ccb_mii_mng_cmd_data_addr); 1223 1224 /* Deaaserting PLL Reset */ 1225 SPINWAIT((((readl(ccb_mii_mng_ctrl_addr) >> 8) & 1) == 1), 1000); 1226 writel(0x582e8000, ccb_mii_mng_cmd_data_addr); 1227 1228 /* Waiting MII Mgt interface idle */ 1229 SPINWAIT((((readl(ccb_mii_mng_ctrl_addr) >> 8) & 1) == 1), 1000); 1230 1231 /* Deasserting USB3 system reset */ 1232 writel(0x00000000, usb3_idm_idm_reset_ctrl_addr); 1233 1234 /* PLL frequency monitor enable */ 1235 SPINWAIT((((readl(ccb_mii_mng_ctrl_addr) >> 8) & 1) == 1), 1000); 1236 writel(0x58069000, ccb_mii_mng_cmd_data_addr); 1237 1238 /* PIPE Block */ 1239 SPINWAIT((((readl(ccb_mii_mng_ctrl_addr) >> 8) & 1) == 1), 1000); 1240 writel(0x587e8060, ccb_mii_mng_cmd_data_addr); 1241 1242 /* CMPMAX & CMPMINTH setting */ 1243 SPINWAIT((((readl(ccb_mii_mng_ctrl_addr) >> 8) & 1) == 1), 1000); 1244 writel(0x580af30d, ccb_mii_mng_cmd_data_addr); 1245 1246 /* DEGLITCH MIN & MAX setting */ 1247 SPINWAIT((((readl(ccb_mii_mng_ctrl_addr) >> 8) & 1) == 1), 1000); 1248 writel(0x580e6302, ccb_mii_mng_cmd_data_addr); 1249 1250 /* TXPMD block */ 1251 SPINWAIT((((readl(ccb_mii_mng_ctrl_addr) >> 8) & 1) == 1), 1000); 1252 writel(0x587e8040, ccb_mii_mng_cmd_data_addr); 1253 1254 /* Enabling SSC */ 1255 SPINWAIT((((readl(ccb_mii_mng_ctrl_addr) >> 8) & 1) == 1), 1000); 1256 writel(0x58061003, ccb_mii_mng_cmd_data_addr); 1257 1258 /* Waiting MII Mgt interface idle */ 1259 SPINWAIT((((readl(ccb_mii_mng_ctrl_addr) >> 8) & 1) == 1), 1000); 1260 } 1261 1262 /* Reg unmap */ 1263 REG_UNMAP((void *)ccb_mii_base); 1264 REG_UNMAP((void *)usb3_idm_idm_base); 1265 1266out: 1267 REG_UNMAP((void *)dmu_base); 1268 1269} 1270 1271static void 1272bcm5301x_usb_phy_init(int coreid) 1273{ 1274 if (coreid == NS_USB20_CORE_ID) { 1275 bcm5301x_usb20_phy_init(); 1276 } 1277 else if (coreid == NS_USB30_CORE_ID) { 1278 bcm5301x_usb30_phy_init(); 1279 } 1280} 1281 1282static void 1283bcm5301x_usb_idm_ioctrl(int coreid) 1284{ 1285 uint32 usb3_idm_idm_base; 1286 uint32 *usb3_idm_idm_ioctrl_addr; 1287 uint32 ioctrl_val; 1288 uint32 arcache = 0xb, awcache = 0x7, aruser = 0x1, awuser = 0x1; 1289 1290 if (!arch_is_coherent()) 1291 return; 1292 1293 usb3_idm_idm_base = (uint32)REG_MAP(0x18105000, 4096); 1294 usb3_idm_idm_ioctrl_addr = (uint32 *)(usb3_idm_idm_base + 0x408); 1295 1296 if (coreid == NS_USB20_CORE_ID) { 1297 uint32 usb2_idm_idm_base; 1298 uint32 *usb2_idm_idm_ioctrl_addr; 1299 1300 usb2_idm_idm_base = (uint32)REG_MAP(0x18115000, 4096); 1301 usb2_idm_idm_ioctrl_addr = (uint32 *)(usb2_idm_idm_base + 0x408); 1302 1303 ioctrl_val = readl(usb2_idm_idm_ioctrl_addr); 1304 ioctrl_val &= ~((0xf << 2) | (0xf << 6)); 1305 ioctrl_val |= (arcache << 6) | (awcache << 2); 1306 writel(ioctrl_val, usb2_idm_idm_ioctrl_addr); 1307 1308 REG_UNMAP((void *)usb2_idm_idm_base); 1309 1310 ioctrl_val = readl(usb3_idm_idm_ioctrl_addr); 1311 ioctrl_val &= ~((0x1f << 12) | (0x1f << 17)); 1312 ioctrl_val |= (aruser << 17) | (awuser << 12); 1313 writel(ioctrl_val, usb3_idm_idm_ioctrl_addr); 1314 } 1315 else if (coreid == NS_USB30_CORE_ID) { 1316 ioctrl_val = readl(usb3_idm_idm_ioctrl_addr); 1317 ioctrl_val &= ~((0xf << 2) | (0xf << 6) | (0x1f << 22) | (0x1f << 27)); 1318 ioctrl_val |= (aruser << 27) | (awuser << 22) | (arcache << 6) | (awcache << 2); 1319 writel(ioctrl_val, usb3_idm_idm_ioctrl_addr); 1320 } 1321 1322 REG_UNMAP((void *)usb3_idm_idm_base); 1323} 1324 1325static void 1326bcm5301x_usb_hc_init(struct pci_dev *dev, int coreid) 1327{ 1328 uint32 start, len; 1329 1330 if (!BCM4707_CHIP(CHIPID(sih->chip))) 1331 return; 1332 1333 if (coreid == NS_USB20_CORE_ID) { 1334 uint32 ehci_base; 1335 uint32 *insnreg01, *insnreg03; 1336 1337 start = pci_resource_start(dev, 0); 1338 len = pci_resource_len(dev, 0); 1339 if (!len) 1340 return; 1341 1342 /* Delay after PHY initialized to ensure HC is ready to be configured */ 1343 mdelay(1); 1344 1345 ehci_base = (uint32)REG_MAP(start, len); 1346 insnreg01 = (uint32 *)(ehci_base + 0x94); 1347 insnreg03 = (uint32 *)(ehci_base + 0x9C); 1348 /* Set packet buffer OUT threshold */ 1349 writel(((readl(insnreg01) & 0xFFFF) | (0x80 << 16)), insnreg01); 1350 /* Enabling break memory transfer */ 1351 writel((readl(insnreg03) | 0x1), insnreg03); 1352 REG_UNMAP((void *)ehci_base); 1353 } 1354} 1355 1356int 1357pcibios_enable_device(struct pci_dev *dev, int mask) 1358{ 1359 ulong flags; 1360 uint coreidx, coreid; 1361 void *regs; 1362 int rc = -1; 1363 1364 /* External PCI device enable */ 1365 if (dev->bus->number != 0) 1366 return pcibios_enable_resources(dev); 1367 1368 /* These cores come out of reset enabled */ 1369 if (dev->device == NS_IHOST_CORE_ID || 1370 dev->device == CC_CORE_ID) 1371 return 0; 1372 1373 spin_lock_irqsave(&sih_lock, flags); 1374 1375 regs = si_setcoreidx(sih, PCI_SLOT(dev->devfn)); 1376 coreidx = si_coreidx(sih); 1377 coreid = si_coreid(sih); 1378 1379 if (!regs) { 1380 printk(KERN_ERR "WARNING! PCIBIOS_DEVICE_NOT_FOUND\n"); 1381 goto out; 1382 } 1383 1384 /* OHCI/EHCI only initialize one time */ 1385 if (coreid == NS_USB20_CORE_ID && si_iscoreup(sih)) { 1386 rc = 0; 1387 goto out; 1388 } 1389 1390 if (coreid != GMAC_CORE_ID) 1391 si_core_reset(sih, 0, 0); 1392 1393 if (coreid == NS_USB20_CORE_ID || coreid == NS_USB30_CORE_ID) { 1394 /* Set gpio HIGH to turn on USB VBUS power */ 1395 bcm5301x_usb_power_on(coreid); 1396 1397 /* USB PHY init */ 1398 bcm5301x_usb_phy_init(coreid); 1399 1400 /* USB HC init */ 1401 bcm5301x_usb_hc_init(dev, coreid); 1402 1403 bcm5301x_usb_idm_ioctrl(coreid); 1404 1405 } 1406 1407 rc = 0; 1408out: 1409 si_setcoreidx(sih, coreidx); 1410 spin_unlock_irqrestore(&sih_lock, flags); 1411 1412 return rc; 1413} 1414 1415bool __devinit 1416plat_fixup_bus(struct pci_bus *b) 1417{ 1418 struct list_head *ln; 1419 struct pci_dev *d; 1420 u8 irq; 1421 1422 printk("PCI: Fixing up bus %d\n", b->number); 1423 1424 /* Fix up SB */ 1425 if (((struct pci_sys_data *)b->sysdata)->domain == 0) { 1426 for (ln = b->devices.next; ln != &b->devices; ln = ln->next) { 1427 d = pci_dev_b(ln); 1428 /* Fix up interrupt lines */ 1429 pci_read_config_byte(d, PCI_INTERRUPT_LINE, &irq); 1430 d->irq = si_bus_map_irq(d); 1431 pci_write_config_byte(d, PCI_INTERRUPT_LINE, d->irq); 1432 } 1433 return TRUE; 1434 } 1435 1436 return FALSE; 1437} 1438 1439static int __init allow_gen2_rc(struct soc_pcie_port *port) 1440{ 1441 uint32 vendorid, devid, chipid, chiprev; 1442 uint32 val, bar, base; 1443 int allow = 1; 1444 char *p; 1445 1446 /* Force GEN1 if specified in NVRAM */ 1447 if ((p = nvram_get("forcegen1rc")) != NULL && simple_strtoul(p, NULL, 0) == 1) { 1448 printk(KERN_NOTICE "Force PCIE RC to GEN1 only\n"); 1449 return 0; 1450 } 1451 1452 /* Read PCI vendor/device ID's */ 1453 __raw_writel(0x0, port->reg_base + SOC_PCIE_CFG_ADDR); 1454 val = __raw_readl(port->reg_base + SOC_PCIE_CFG_DATA); 1455 vendorid = val & 0xffff; 1456 devid = val >> 16; 1457 if (vendorid == VENDOR_BROADCOM && 1458 (devid == BCM4360_CHIP_ID || devid == BCM4360_D11AC_ID || 1459 devid == BCM4360_D11AC2G_ID || devid == BCM4360_D11AC5G_ID || 1460 devid == BCM4352_D11AC_ID || devid == BCM4352_D11AC2G_ID || 1461 devid == BCM4352_D11AC5G_ID)) { 1462 /* Config BAR0 */ 1463 bar = port->owin_res->start; 1464 __raw_writel(0x10, port->reg_base + SOC_PCIE_CFG_ADDR); 1465 __raw_writel(bar, port->reg_base + SOC_PCIE_CFG_DATA); 1466 /* Config BAR0 window to access chipc */ 1467 __raw_writel(0x80, port->reg_base + SOC_PCIE_CFG_ADDR); 1468 __raw_writel(SI_ENUM_BASE, port->reg_base + SOC_PCIE_CFG_DATA); 1469 1470 /* Enable memory resource */ 1471 __raw_writel(0x4, port->reg_base + SOC_PCIE_CFG_ADDR); 1472 val = __raw_readl(port->reg_base + SOC_PCIE_CFG_DATA); 1473 val |= PCI_COMMAND_MEMORY; 1474 __raw_writel(val, port->reg_base + SOC_PCIE_CFG_DATA); 1475 /* Enable memory and bus master */ 1476 __raw_writel(0x6, port->reg_base + SOC_PCIE_HDR_OFF + 4); 1477 1478 /* Read CHIP ID */ 1479 base = (uint32)ioremap(bar, 0x1000); 1480 val = __raw_readl(base); 1481 iounmap((void *)base); 1482 chipid = val & 0xffff; 1483 chiprev = (val >> 16) & 0xf; 1484 if ((chipid == BCM4360_CHIP_ID || 1485 chipid == BCM43460_CHIP_ID || 1486 chipid == BCM4352_CHIP_ID) && (chiprev < 3)) 1487 allow = 0; 1488 } 1489 return (allow); 1490} 1491 1492static void __init 1493bcm5301x_3rd_pcie_init(void) 1494{ 1495 uint32 cru_straps_ctrl; 1496 uint32 ccb_mii_base; 1497 uint32 dmu_base; 1498 uint32 *ccb_mii_mng_ctrl_addr; 1499 uint32 *ccb_mii_mng_cmd_data_addr; 1500 1501 /* Check Chip ID */ 1502 if (!BCM4707_CHIP(CHIPID(sih->chip)) || 1503 (sih->chippkg != BCM4708_PKG_ID && sih->chippkg != BCM4709_PKG_ID)) 1504 return; 1505 1506 /* Reg map */ 1507 dmu_base = (uint32)REG_MAP(0x1800c000, 4096); 1508 1509 /* Check strapping of PCIE/USB3 SEL */ 1510 cru_straps_ctrl = readl((uint32 *)(dmu_base + 0x2a0)); 1511 /* PCIE mode is not selected */ 1512 if (cru_straps_ctrl & 0x10) 1513 goto out; 1514 1515 /* Reg map */ 1516 ccb_mii_base = (uint32)REG_MAP(0x18003000, 4096); 1517 ccb_mii_mng_ctrl_addr = (uint32 *)(ccb_mii_base + 0x0); 1518 ccb_mii_mng_cmd_data_addr = (uint32 *)(ccb_mii_base + 0x4); 1519 1520 /* MDIO setting. set MDC-> MDCDIV is 7'd8 */ 1521 writel(0x00000088, ccb_mii_mng_ctrl_addr); 1522 SPINWAIT(((readl(ccb_mii_mng_ctrl_addr) >> 8 & 1) == 1), 1000); 1523 /* PCIE PLL block register (base 0x8000) */ 1524 writel(0x57fe8000, ccb_mii_mng_cmd_data_addr); 1525 SPINWAIT(((readl(ccb_mii_mng_ctrl_addr) >> 8 & 1) == 1), 1000); 1526 /* Check PCIE PLL lock status */ 1527 writel(0x67c60000, ccb_mii_mng_cmd_data_addr); 1528 SPINWAIT(((readl(ccb_mii_mng_ctrl_addr) >> 8 & 1) == 1), 1000); 1529 1530 /* Reg unmap */ 1531 REG_UNMAP((void *)ccb_mii_base); 1532out: 1533 REG_UNMAP((void *)dmu_base); 1534} 1535 1536static void __init 1537bcm5301x_pcie_phy_init(void) 1538{ 1539 uint32 ccb_mii_base; 1540 uint32 *ccb_mii_mng_ctrl_addr; 1541 uint32 *ccb_mii_mng_cmd_data_addr; 1542 uint32 dmu_base, cru_straps_ctrl; 1543 uint32 blkaddr = 0x863, regaddr; 1544 uint32 sb = 1, op_w = 1, pa[3] = {0x0, 0x1, 0xf}, blkra = 0x1f, ta = 2; 1545 uint32 i, val; 1546 1547 /* Check Chip ID */ 1548 if (!BCM4707_CHIP(CHIPID(sih->chip))) 1549 return; 1550 1551 /* Reg map */ 1552 dmu_base = (uint32)REG_MAP(0x1800c000, 4096); 1553 ccb_mii_base = (uint32)REG_MAP(0x18003000, 4096); 1554 ccb_mii_mng_ctrl_addr = (uint32 *)ccb_mii_base; 1555 ccb_mii_mng_cmd_data_addr = (uint32 *)(ccb_mii_base + 0x4); 1556 1557 /* Set MDC/MDIO for Internal phy */ 1558 SPINWAIT(((readl(ccb_mii_mng_ctrl_addr) >> 8 & 1) == 1), 1000); 1559 writel(0x0000009a, ccb_mii_mng_ctrl_addr); 1560 1561 /* To improve PCIE phy jitter */ 1562 for (i = 0; i < (ARRAY_SIZE(soc_pcie_ports) - 1); i++) { 1563 if (i == 2) { 1564 cru_straps_ctrl = readl((uint32 *)(dmu_base + 0x2a0)); 1565 1566 /* 3rd PCIE is not selected */ 1567 if (cru_straps_ctrl & 0x10) 1568 break; 1569 } 1570 1571 /* Change blkaddr */ 1572 SPINWAIT(((readl(ccb_mii_mng_ctrl_addr) >> 8 & 1) == 1), 1000); 1573 val = (sb << 30) | (op_w << 28) | (pa[i] << 23) | (blkra << 18) | 1574 (ta << 16) | (blkaddr << 4); 1575 writel(val, ccb_mii_mng_cmd_data_addr); 1576 1577 /* Write 0x0190 to 0x13 regaddr */ 1578 SPINWAIT(((readl(ccb_mii_mng_ctrl_addr) >> 8 & 1) == 1), 1000); 1579 regaddr = 0x13; 1580 val = (sb << 30) | (op_w << 28) | (pa[i] << 23) | (regaddr << 18) | 1581 (ta << 16) | 0x0190; 1582 writel(val, ccb_mii_mng_cmd_data_addr); 1583 1584 /* Write 0x0191 to 0x19 regaddr */ 1585 SPINWAIT(((readl(ccb_mii_mng_ctrl_addr) >> 8 & 1) == 1), 1000); 1586 regaddr = 0x19; 1587 val = (sb << 30) | (op_w << 28) | (pa[i] << 23) | (regaddr << 18) | 1588 (ta << 16) | 0x0191; 1589 writel(val, ccb_mii_mng_cmd_data_addr); 1590 } 1591 1592 /* Waiting MII Mgt interface idle */ 1593 SPINWAIT((((readl(ccb_mii_mng_ctrl_addr) >> 8) & 1) == 1), 1000); 1594 1595 /* Reg unmap */ 1596 REG_UNMAP((void *)dmu_base); 1597 REG_UNMAP((void *)ccb_mii_base); 1598} 1599 1600static int __init soc_pcie_init(void) 1601{ 1602 unsigned int i; 1603 int allow_gen2, linkfail; 1604 uint origidx; 1605 unsigned long flags; 1606 1607 1608 hndpci_init(sih); 1609 1610 spin_lock_irqsave(&sih_lock, flags); 1611 1612 /* Save current core index */ 1613 origidx = si_coreidx(sih); 1614 1615 /* Get pcie coreid and corerev */ 1616 si_setcore(sih, NS_PCIEG2_CORE_ID, 0); 1617 pcie_coreid = si_coreid(sih); 1618 pcie_corerev = si_corerev(sih); 1619 1620 /* Restore core index */ 1621 si_setcoreidx(sih, origidx); 1622 1623 spin_unlock_irqrestore(&sih_lock, flags); 1624 1625 /* For NS-B0, overwrite the start and end values for PCIE port 1 and port 2 */ 1626 if (pcie_coreid == NS_PCIEG2_CORE_ID && pcie_corerev == 0x7) { 1627 soc_pcie_owin[1].start = 0x20000000; 1628 soc_pcie_owin[1].end = 0x20000000 + SZ_128M - 1; 1629 1630 soc_pcie_owin[2].start = 0x28000000; 1631 soc_pcie_owin[2].end = 0x28000000 + SZ_128M - 1; 1632 } 1633 1634 /* Scan the SB bus */ 1635 printk(KERN_INFO "PCI: scanning bus %x\n", 0); 1636 pci_scan_bus(0, &pcibios_ops, &soc_pcie_ports[0].hw_pci); 1637 1638 bcm5301x_3rd_pcie_init(); 1639 1640 bcm5301x_pcie_phy_init(); 1641 1642 for (i = 1; i < ARRAY_SIZE(soc_pcie_ports); i++) { 1643 struct soc_pcie_port *port = &soc_pcie_ports[i]; 1644 1645 /* Check if this port needs to be enabled */ 1646 if (!port->enable) 1647 continue; 1648 1649 /* Setup PCIe controller registers */ 1650 BUG_ON(request_resource(&iomem_resource, port->regs_res)); 1651 port->reg_base = 1652 ioremap(port->regs_res->start, 1653 resource_size(port->regs_res)); 1654 BUG_ON(IS_ERR_OR_NULL(port->reg_base)); 1655 1656 for (allow_gen2 = 0; allow_gen2 <= 1; allow_gen2++) { 1657 soc_pcie_hw_init(port); 1658 soc_pcie_map_init(port); 1659 1660 /* 1661 * Skip inactive ports - 1662 * will need to change this for hot-plugging 1663 */ 1664 linkfail = soc_pcie_check_link(port, allow_gen2); 1665 if (linkfail) 1666 break; 1667 1668 soc_pcie_bridge_init(port); 1669 1670 if (allow_gen2 == 0) { 1671 if (allow_gen2_rc(port) == 0) 1672 break; 1673 pr_info("PCIE%d switching to GEN2\n", port->hw_pci.domain); 1674 } 1675 } 1676 1677 if (linkfail) 1678 continue; 1679 1680 /* Announce this port to ARM/PCI common code */ 1681 pci_common_init(&port->hw_pci); 1682 1683 /* Setup virtual-wire interrupts */ 1684 __raw_writel(0xf, port->reg_base + SOC_PCIE_SYS_RC_INTX_EN); 1685 1686 /* Enable memory and bus master */ 1687 __raw_writel(0x6, port->reg_base + SOC_PCIE_HDR_OFF + 4); 1688 } 1689 1690 return 0; 1691} 1692 1693device_initcall(soc_pcie_init); 1694 1695#endif /* CONFIG_PCI */ 1696