1/* Modified by Broadcom Corp. Portions Copyright (c) Broadcom Corp, 2012. */ 2/* 3 * linux/arch/arm/mm/proc-v7.S 4 * 5 * Copyright (C) 2001 Deep Blue Solutions Ltd. 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 * 11 * This is the "shell" of the ARMv7 processor support. 12 */ 13#include <linux/init.h> 14#include <linux/linkage.h> 15#include <asm/assembler.h> 16#include <asm/memory.h> 17#include <asm/asm-offsets.h> 18#include <asm/hwcap.h> 19#include <asm/pgtable-hwdef.h> 20#include <asm/pgtable.h> 21 22#include "proc-macros.S" 23 24#define TTB_S (1 << 1) 25#define TTB_RGN_NC (0 << 3) 26#define TTB_RGN_OC_WBWA (1 << 3) 27#define TTB_RGN_OC_WT (2 << 3) 28#define TTB_RGN_OC_WB (3 << 3) 29#define TTB_NOS (1 << 5) 30#define TTB_IRGN_NC ((0 << 0) | (0 << 6)) 31#define TTB_IRGN_WBWA ((0 << 0) | (1 << 6)) 32#define TTB_IRGN_WT ((1 << 0) | (0 << 6)) 33#define TTB_IRGN_WB ((1 << 0) | (1 << 6)) 34 35#ifndef CONFIG_SMP 36/* PTWs cacheable, inner WB not shareable, outer WB not shareable */ 37#define TTB_FLAGS TTB_IRGN_WB|TTB_RGN_OC_WB 38#define PMD_FLAGS PMD_SECT_WB 39#else 40/* PTWs cacheable, inner WBWA shareable, outer WBWA not shareable */ 41#define TTB_FLAGS TTB_IRGN_WBWA|TTB_S|TTB_NOS|TTB_RGN_OC_WBWA 42#define PMD_FLAGS PMD_SECT_WBWA|PMD_SECT_S 43#endif 44 45ENTRY(cpu_v7_proc_init) 46 mov pc, lr 47ENDPROC(cpu_v7_proc_init) 48 49ENTRY(cpu_v7_proc_fin) 50 mrc p15, 0, r0, c1, c0, 0 @ ctrl register 51 bic r0, r0, #0x1000 @ ...i............ 52 bic r0, r0, #0x0006 @ .............ca. 53 mcr p15, 0, r0, c1, c0, 0 @ disable caches 54 mov pc, lr 55ENDPROC(cpu_v7_proc_fin) 56 57/* 58 * cpu_v7_reset(loc) 59 * 60 * Perform a soft reset of the system. Put the CPU into the 61 * same state as it would be if it had been reset, and branch 62 * to what would be the reset vector. 63 * 64 * - loc - location to jump to for soft reset 65 */ 66 .align 5 67ENTRY(cpu_v7_reset) 68 mov pc, r0 69ENDPROC(cpu_v7_reset) 70 71/* 72 * cpu_v7_do_idle() 73 * 74 * Idle the processor (eg, wait for interrupt). 75 * 76 * IRQs are already disabled. 77 */ 78ENTRY(cpu_v7_do_idle) 79 dsb @ WFI may enter a low-power mode 80 wfi 81 mov pc, lr 82ENDPROC(cpu_v7_do_idle) 83 84ENTRY(cpu_v7_dcache_clean_area) 85#ifndef TLB_CAN_READ_FROM_L1_CACHE 86 dcache_line_size r2, r3 871: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 88 add r0, r0, r2 89 subs r1, r1, r2 90 bhi 1b 91 dsb 92#endif 93 mov pc, lr 94ENDPROC(cpu_v7_dcache_clean_area) 95 96/* 97 * cpu_v7_switch_mm(pgd_phys, tsk) 98 * 99 * Set the translation table base pointer to be pgd_phys 100 * 101 * - pgd_phys - physical address of new TTB 102 * 103 * It is assumed that: 104 * - we are not using split page tables 105 */ 106ENTRY(cpu_v7_switch_mm) 107#ifdef CONFIG_MMU 108 mov r2, #0 109 ldr r1, [r1, #MM_CONTEXT_ID] @ get mm->context.id 110 orr r0, r0, #TTB_FLAGS 111#ifdef CONFIG_ARM_ERRATA_430973 112 mcr p15, 0, r2, c7, c5, 6 @ flush BTAC/BTB 113#endif 114 mcr p15, 0, r2, c13, c0, 1 @ set reserved context ID 115 isb 1161: mcr p15, 0, r0, c2, c0, 0 @ set TTB 0 117 isb 118 mcr p15, 0, r1, c13, c0, 1 @ set context ID 119 isb 120#endif 121 mov pc, lr 122ENDPROC(cpu_v7_switch_mm) 123 124/* 125 * cpu_v7_set_pte_ext(ptep, pte) 126 * 127 * Set a level 2 translation table entry. 128 * 129 * - ptep - pointer to level 2 translation table entry 130 * (hardware version is stored at -1024 bytes) 131 * - pte - PTE value to store 132 * - ext - value for extended PTE bits 133 */ 134ENTRY(cpu_v7_set_pte_ext) 135#ifdef CONFIG_MMU 136 ARM( str r1, [r0], #-2048 ) @ linux version 137 THUMB( str r1, [r0] ) @ linux version 138 THUMB( sub r0, r0, #2048 ) 139 140 bic r3, r1, #0x000003f0 141 bic r3, r3, #PTE_TYPE_MASK 142 orr r3, r3, r2 143 orr r3, r3, #PTE_EXT_AP0 | 2 144 145 tst r1, #1 << 4 146 orrne r3, r3, #PTE_EXT_TEX(1) 147 148 tst r1, #L_PTE_WRITE 149 tstne r1, #L_PTE_DIRTY 150 orreq r3, r3, #PTE_EXT_APX 151 152 tst r1, #L_PTE_USER 153 orrne r3, r3, #PTE_EXT_AP1 154 tstne r3, #PTE_EXT_APX 155 bicne r3, r3, #PTE_EXT_APX | PTE_EXT_AP0 156 157 tst r1, #L_PTE_EXEC 158 orreq r3, r3, #PTE_EXT_XN 159 160 tst r1, #L_PTE_YOUNG 161 tstne r1, #L_PTE_PRESENT 162 moveq r3, #0 163 164 str r3, [r0] 165 mcr p15, 0, r0, c7, c10, 1 @ flush_pte 166#endif 167 mov pc, lr 168ENDPROC(cpu_v7_set_pte_ext) 169 170cpu_v7_name: 171 .ascii "ARMv7 Processor" 172 .align 173 174 __INIT 175 176/* 177 * __v7_setup 178 * 179 * Initialise TLB, Caches, and MMU state ready to switch the MMU 180 * on. Return in r0 the new CP15 C1 control register setting. 181 * 182 * We automatically detect if we have a Harvard cache, and use the 183 * Harvard cache control instructions insead of the unified cache 184 * control instructions. 185 * 186 * This should be able to cover all ARMv7 cores. 187 * 188 * It is assumed that: 189 * - cache type register is implemented 190 */ 191__v7_ca9mp_setup: 192#ifdef CONFIG_SMP 193 mrc p15, 0, r0, c1, c0, 1 194 tst r0, #(1 << 6) @ SMP/nAMP mode enabled? 195 orreq r0, r0, #(1 << 6) | (1 << 0) @ Enable SMP/nAMP mode and 196 mcreq p15, 0, r0, c1, c0, 1 @ TLB ops broadcasting 197#else 198 ldr r8, =ddr_phys_offset_va 199 ldr r1, =PAGE_OFFSET 200 sub r8, r8, r1 201 ldr r1, =CONFIG_DRAM_BASE 202 add r8, r8, r1 203 ldr r8, [r8, #0x0] @ get real PHYS_OFFSET value 204 ldr r12, =0xC0000000 @ the upper two bits of NS Ax/Bx ACP address 205 and r12, r12, r8 206 cmp r12, #0 207 beq __v7_setup 208 209 /* For NS Ax/Bx ACP on UP mode */ 210acp_up: 211 mrc p15, 0, r0, c1, c0, 1 212 orr r0, r0, #(1 << 6) @ Enable SMP bit for ACP on UP 213 mcr p15, 0, r0, c1, c0, 1 @ TLB ops broadcasting 214#endif /* CONFIG_SMP */ 215 216__v7_setup: 217 @ temporary local stack in RAM, physical address, MMU is off 218 /* The __v7_setup_stack is located at < 128MB address */ 219 ldr r12, =__v7_setup_stack 220 ldr r8, =PAGE_OFFSET 221 sub r12, r12, r8 @ get offset 222 ldr r8, =ddr_phys_offset_va 223 ldr r1, =PAGE_OFFSET 224 sub r8, r8, r1 225 ldr r1, =CONFIG_DRAM_BASE 226 add r8, r8, r1 227 ldr r8, [r8, #0x0] @ get real PHYS_OFFSET value 228 add r12, r12, r8 229 230 stmia r12, {r0-r5, r7, r9, r11, lr} 231 bl v7_flush_dcache_all 232 ldmia r12, {r0-r5, r7, r9, r11, lr} 233 234 mrc p15, 0, r0, c0, c0, 0 @ read main ID register 235 and r10, r0, #0xff000000 @ ARM? 236 teq r10, #0x41000000 237 bne 3f 238 and r5, r0, #0x00f00000 @ variant 239 and r6, r0, #0x0000000f @ revision 240 orr r6, r6, r5, lsr #20-4 @ combine variant and revision 241 ubfx r0, r0, #4, #12 @ primary part number 242 243 /* Cortex-A8 Errata */ 244 ldr r10, =0x00000c08 @ Cortex-A8 primary part number 245 teq r0, r10 246 bne 2f 247#ifdef CONFIG_ARM_ERRATA_430973 248 teq r5, #0x00100000 @ only present in r1p* 249 mrceq p15, 0, r10, c1, c0, 1 @ read aux control register 250 orreq r10, r10, #(1 << 6) @ set IBE to 1 251 mcreq p15, 0, r10, c1, c0, 1 @ write aux control register 252#endif 253#ifdef CONFIG_ARM_ERRATA_458693 254 teq r6, #0x20 @ only present in r2p0 255 mrceq p15, 0, r10, c1, c0, 1 @ read aux control register 256 orreq r10, r10, #(1 << 5) @ set L1NEON to 1 257 orreq r10, r10, #(1 << 9) @ set PLDNOP to 1 258 mcreq p15, 0, r10, c1, c0, 1 @ write aux control register 259#endif 260#ifdef CONFIG_ARM_ERRATA_460075 261 teq r6, #0x20 @ only present in r2p0 262 mrceq p15, 1, r10, c9, c0, 2 @ read L2 cache aux ctrl register 263 tsteq r10, #1 << 22 264 orreq r10, r10, #(1 << 22) @ set the Write Allocate disable bit 265 mcreq p15, 1, r10, c9, c0, 2 @ write the L2 cache aux ctrl register 266#endif 267 b 3f 268 269 /* Cortex-A9 Errata */ 2702: ldr r10, =0x00000c09 @ Cortex-A9 primary part number 271 teq r0, r10 272 bne 3f 273#ifdef CONFIG_ARM_ERRATA_742230 274 cmp r6, #0x22 @ only present up to r2p2 275 mrcle p15, 0, r10, c15, c0, 1 @ read diagnostic register 276 orrle r10, r10, #1 << 4 @ set bit #4 277 mcrle p15, 0, r10, c15, c0, 1 @ write diagnostic register 278#endif 279#ifdef CONFIG_ARM_ERRATA_742231 280 teq r6, #0x20 @ present in r2p0 281 teqne r6, #0x21 @ present in r2p1 282 teqne r6, #0x22 @ present in r2p2 283 mrceq p15, 0, r10, c15, c0, 1 @ read diagnostic register 284 orreq r10, r10, #1 << 12 @ set bit #12 285 orreq r10, r10, #1 << 22 @ set bit #22 286 mcreq p15, 0, r10, c15, c0, 1 @ write diagnostic register 287#endif 288#ifdef CONFIG_ARM_ERRATA_743622 289 teq r6, #0x20 @ present in r2p0 290 teqne r6, #0x21 @ present in r2p1 291 teqne r6, #0x22 @ present in r2p2 292 mrceq p15, 0, r10, c15, c0, 1 @ read diagnostic register 293 orreq r10, r10, #1 << 6 @ set bit #6 294 mcreq p15, 0, r10, c15, c0, 1 @ write diagnostic register 295#endif 296 2973: mov r10, #0 298#ifdef HARVARD_CACHE 299 mcr p15, 0, r10, c7, c5, 0 @ I+BTB cache invalidate 300#endif 301 dsb 302#ifdef CONFIG_MMU 303 mcr p15, 0, r10, c8, c7, 0 @ invalidate I + D TLBs 304 mcr p15, 0, r10, c2, c0, 2 @ TTB control register 305 orr r4, r4, #TTB_FLAGS 306 mcr p15, 0, r4, c2, c0, 1 @ load TTB1 307 mov r10, #0x1f @ domains 0, 1 = manager 308 mcr p15, 0, r10, c3, c0, 0 @ load domain access register 309 /* 310 * Memory region attributes with SCTLR.TRE=1 311 * 312 * n = TEX[0],C,B 313 * TR = PRRR[2n+1:2n] - memory type 314 * IR = NMRR[2n+1:2n] - inner cacheable property 315 * OR = NMRR[2n+17:2n+16] - outer cacheable property 316 * 317 * n TR IR OR 318 * UNCACHED 000 00 319 * BUFFERABLE 001 10 00 00 320 * WRITETHROUGH 010 10 10 10 321 * WRITEBACK 011 10 11 11 322 * reserved 110 323 * WRITEALLOC 111 10 01 01 324 * DEV_SHARED 100 01 325 * DEV_NONSHARED 100 01 326 * DEV_WC 001 10 327 * DEV_CACHED 011 10 328 * 329 * Other attributes: 330 * 331 * DS0 = PRRR[16] = 0 - device shareable property 332 * DS1 = PRRR[17] = 1 - device shareable property 333 * NS0 = PRRR[18] = 0 - normal shareable property 334 * NS1 = PRRR[19] = 1 - normal shareable property 335 * NOS = PRRR[24+n] = 1 - not outer shareable 336 */ 337 ldr r5, =0xff0a81a8 @ PRRR 338 ldr r6, =0x40e040e0 @ NMRR 339 mcr p15, 0, r5, c10, c2, 0 @ write PRRR 340 mcr p15, 0, r6, c10, c2, 1 @ write NMRR 341#endif 342 adr r5, v7_crval 343 ldmia r5, {r5, r6} 344#ifdef CONFIG_CPU_ENDIAN_BE8 345 orr r6, r6, #1 << 25 @ big-endian page tables 346#endif 347 mrc p15, 0, r0, c1, c0, 0 @ read control register 348 bic r0, r0, r5 @ clear bits them 349 orr r0, r0, r6 @ set them 350 THUMB( orr r0, r0, #1 << 30 ) @ Thumb exceptions 351 mov pc, lr @ return to head.S:__ret 352ENDPROC(__v7_setup) 353 .ltorg 354 355 .type v7_crval, #object 356v7_crval: 357 crval clear=0x0120c302, mmuset=0x10c03c7d, ucset=0x00c01c7c 358 359 .type v7_processor_functions, #object 360ENTRY(v7_processor_functions) 361 .word v7_early_abort 362 .word v7_pabort 363 .word cpu_v7_proc_init 364 .word cpu_v7_proc_fin 365 .word cpu_v7_reset 366 .word cpu_v7_do_idle 367 .word cpu_v7_dcache_clean_area 368 .word cpu_v7_switch_mm 369 .word cpu_v7_set_pte_ext 370 .size v7_processor_functions, . - v7_processor_functions 371 372 .type cpu_arch_name, #object 373cpu_arch_name: 374 .asciz "armv7" 375 .size cpu_arch_name, . - cpu_arch_name 376 377 .type cpu_elf_name, #object 378cpu_elf_name: 379 .asciz "v7" 380 .size cpu_elf_name, . - cpu_elf_name 381 .align 382 383 .section ".proc.info.init", #alloc, #execinstr 384 385 .type __v7_ca9mp_proc_info, #object 386__v7_ca9mp_proc_info: 387 .long 0x410fc090 @ Required ID value 388 .long 0xff0ffff0 @ Mask for ID 389 .long PMD_TYPE_SECT | \ 390 PMD_SECT_AP_WRITE | \ 391 PMD_SECT_AP_READ | \ 392 PMD_FLAGS 393 .long PMD_TYPE_SECT | \ 394 PMD_SECT_XN | \ 395 PMD_SECT_AP_WRITE | \ 396 PMD_SECT_AP_READ 397 b __v7_ca9mp_setup 398 .long cpu_arch_name 399 .long cpu_elf_name 400 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP|HWCAP_TLS 401 .long cpu_v7_name 402 .long v7_processor_functions 403 .long v7wbi_tlb_fns 404 .long v6_user_fns 405 .long v7_cache_fns 406 .size __v7_ca9mp_proc_info, . - __v7_ca9mp_proc_info 407 408 /* 409 * Match any ARMv7 processor core. 410 */ 411 .type __v7_proc_info, #object 412__v7_proc_info: 413 .long 0x000f0000 @ Required ID value 414 .long 0x000f0000 @ Mask for ID 415 .long PMD_TYPE_SECT | \ 416 PMD_SECT_AP_WRITE | \ 417 PMD_SECT_AP_READ | \ 418 PMD_FLAGS 419 .long PMD_TYPE_SECT | \ 420 PMD_SECT_XN | \ 421 PMD_SECT_AP_WRITE | \ 422 PMD_SECT_AP_READ 423 b __v7_setup 424 .long cpu_arch_name 425 .long cpu_elf_name 426 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP|HWCAP_TLS 427 .long cpu_v7_name 428 .long v7_processor_functions 429 .long v7wbi_tlb_fns 430 .long v6_user_fns 431 .long v7_cache_fns 432 .size __v7_proc_info, . - __v7_proc_info 433 434 .bss 435 .align 436__v7_setup_stack: 437 .space 4 * 11 @ 11 registers 438