1/* 2 * Copyright (C) 2010 ST-Ericsson 3 * Copyright (C) 2009 STMicroelectronics 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License version 2 as 7 * published by the Free Software Foundation. 8 */ 9 10/** 11 * struct clkops - ux500 clock operations 12 * @enable: function to enable the clock 13 * @disable: function to disable the clock 14 * @get_rate: function to get the current clock rate 15 * 16 * This structure contains function pointers to functions that will be used to 17 * control the clock. All of these functions are optional. If get_rate is 18 * NULL, the rate in the struct clk will be used. 19 */ 20struct clkops { 21 void (*enable) (struct clk *); 22 void (*disable) (struct clk *); 23 unsigned long (*get_rate) (struct clk *); 24}; 25 26/** 27 * struct clk - ux500 clock structure 28 * @ops: pointer to clkops struct used to control this clock 29 * @name: name, for debugging 30 * @enabled: refcount. positive if enabled, zero if disabled 31 * @get_rate: custom callback for getting the clock rate 32 * @data: custom per-clock data for example for the get_rate 33 * callback 34 * @rate: fixed rate for clocks which don't implement 35 * ops->getrate 36 * @prcmu_cg_off: address offset of the combined enable/disable register 37 * (used on u8500v1) 38 * @prcmu_cg_bit: bit in the combined enable/disable register (used on 39 * u8500v1) 40 * @prcmu_cg_mgt: address of the enable/disable register (used on 41 * u8500ed) 42 * @cluster: peripheral cluster number 43 * @prcc_bus: bit for the bus clock in the peripheral's CLKRST 44 * @prcc_kernel: bit for the kernel clock in the peripheral's CLKRST. 45 * -1 if no kernel clock exists. 46 * @parent_cluster: pointer to parent's cluster clk struct 47 * @parent_periph: pointer to parent's peripheral clk struct 48 * 49 * Peripherals are organised into clusters, and each cluster has an associated 50 * bus clock. Some peripherals also have a parent peripheral clock. 51 * 52 * In order to enable a clock for a peripheral, we need to enable: 53 * (1) the parent cluster (bus) clock at the PRCMU level 54 * (2) the parent peripheral clock (if any) at the PRCMU level 55 * (3) the peripheral's bus & kernel clock at the PRCC level 56 * 57 * (1) and (2) are handled by defining clk structs (DEFINE_PRCMU_CLK) for each 58 * of the cluster and peripheral clocks, and hooking these as the parents of 59 * the individual peripheral clocks. 60 * 61 * (3) is handled by specifying the bits in the PRCC control registers required 62 * to enable these clocks and modifying them in the ->enable and 63 * ->disable callbacks of the peripheral clocks (DEFINE_PRCC_CLK). 64 * 65 * This structure describes both the PRCMU-level clocks and PRCC-level clocks. 66 * The prcmu_* fields are only used for the PRCMU clocks, and the cluster, 67 * prcc, and parent pointers are only used for the PRCC-level clocks. 68 */ 69struct clk { 70 const struct clkops *ops; 71 const char *name; 72 unsigned int enabled; 73 unsigned long (*get_rate)(struct clk *); 74 void *data; 75 76 unsigned long rate; 77 struct list_head list; 78 79 /* These three are only for PRCMU clks */ 80 81 unsigned int prcmu_cg_off; 82 unsigned int prcmu_cg_bit; 83 unsigned int prcmu_cg_mgt; 84 85 /* The rest are only for PRCC clks */ 86 87 int cluster; 88 unsigned int prcc_bus; 89 unsigned int prcc_kernel; 90 91 struct clk *parent_cluster; 92 struct clk *parent_periph; 93}; 94 95#define DEFINE_PRCMU_CLK(_name, _cg_off, _cg_bit, _reg) \ 96struct clk clk_##_name = { \ 97 .name = #_name, \ 98 .ops = &clk_prcmu_ops, \ 99 .prcmu_cg_off = _cg_off, \ 100 .prcmu_cg_bit = _cg_bit, \ 101 .prcmu_cg_mgt = PRCM_##_reg##_MGT \ 102 } 103 104#define DEFINE_PRCMU_CLK_RATE(_name, _cg_off, _cg_bit, _reg, _rate) \ 105struct clk clk_##_name = { \ 106 .name = #_name, \ 107 .ops = &clk_prcmu_ops, \ 108 .prcmu_cg_off = _cg_off, \ 109 .prcmu_cg_bit = _cg_bit, \ 110 .rate = _rate, \ 111 .prcmu_cg_mgt = PRCM_##_reg##_MGT \ 112 } 113 114#define DEFINE_PRCC_CLK(_pclust, _name, _bus_en, _kernel_en, _kernclk) \ 115struct clk clk_##_name = { \ 116 .name = #_name, \ 117 .ops = &clk_prcc_ops, \ 118 .cluster = _pclust, \ 119 .prcc_bus = _bus_en, \ 120 .prcc_kernel = _kernel_en, \ 121 .parent_cluster = &clk_per##_pclust##clk, \ 122 .parent_periph = _kernclk \ 123 } 124 125#define DEFINE_PRCC_CLK_CUSTOM(_pclust, _name, _bus_en, _kernel_en, _kernclk, _callback, _data) \ 126struct clk clk_##_name = { \ 127 .name = #_name, \ 128 .ops = &clk_prcc_ops, \ 129 .cluster = _pclust, \ 130 .prcc_bus = _bus_en, \ 131 .prcc_kernel = _kernel_en, \ 132 .parent_cluster = &clk_per##_pclust##clk, \ 133 .parent_periph = _kernclk, \ 134 .get_rate = _callback, \ 135 .data = (void *) _data \ 136 } 137 138 139#define CLK(_clk, _devname, _conname) \ 140 { \ 141 .clk = &clk_##_clk, \ 142 .dev_id = _devname, \ 143 .con_id = _conname, \ 144 } 145 146int __init clk_db8500_ed_fixup(void); 147int __init clk_init(void); 148