1/* 2 * 3 * arch/arm/mach-u300/timer.c 4 * 5 * 6 * Copyright (C) 2007-2009 ST-Ericsson AB 7 * License terms: GNU General Public License (GPL) version 2 8 * Timer COH 901 328, runs the OS timer interrupt. 9 * Author: Linus Walleij <linus.walleij@stericsson.com> 10 */ 11#include <linux/interrupt.h> 12#include <linux/time.h> 13#include <linux/timex.h> 14#include <linux/clockchips.h> 15#include <linux/clocksource.h> 16#include <linux/types.h> 17#include <linux/io.h> 18#include <linux/clk.h> 19#include <linux/err.h> 20 21#include <mach/hardware.h> 22 23/* Generic stuff */ 24#include <asm/mach/map.h> 25#include <asm/mach/time.h> 26#include <asm/mach/irq.h> 27 28/* Be able to sleep for atleast 4 seconds (usually more) */ 29#define APPTIMER_MIN_RANGE 4 30 31/* 32 * APP side special timer registers 33 * This timer contains four timers which can fire an interrupt each. 34 * OS (operating system) timer @ 32768 Hz 35 * DD (device driver) timer @ 1 kHz 36 * GP1 (general purpose 1) timer @ 1MHz 37 * GP2 (general purpose 2) timer @ 1MHz 38 */ 39 40/* Reset OS Timer 32bit (-/W) */ 41#define U300_TIMER_APP_ROST (0x0000) 42#define U300_TIMER_APP_ROST_TIMER_RESET (0x00000000) 43/* Enable OS Timer 32bit (-/W) */ 44#define U300_TIMER_APP_EOST (0x0004) 45#define U300_TIMER_APP_EOST_TIMER_ENABLE (0x00000000) 46/* Disable OS Timer 32bit (-/W) */ 47#define U300_TIMER_APP_DOST (0x0008) 48#define U300_TIMER_APP_DOST_TIMER_DISABLE (0x00000000) 49/* OS Timer Mode Register 32bit (-/W) */ 50#define U300_TIMER_APP_SOSTM (0x000c) 51#define U300_TIMER_APP_SOSTM_MODE_CONTINUOUS (0x00000000) 52#define U300_TIMER_APP_SOSTM_MODE_ONE_SHOT (0x00000001) 53/* OS Timer Status Register 32bit (R/-) */ 54#define U300_TIMER_APP_OSTS (0x0010) 55#define U300_TIMER_APP_OSTS_TIMER_STATE_MASK (0x0000000F) 56#define U300_TIMER_APP_OSTS_TIMER_STATE_IDLE (0x00000001) 57#define U300_TIMER_APP_OSTS_TIMER_STATE_ACTIVE (0x00000002) 58#define U300_TIMER_APP_OSTS_ENABLE_IND (0x00000010) 59#define U300_TIMER_APP_OSTS_MODE_MASK (0x00000020) 60#define U300_TIMER_APP_OSTS_MODE_CONTINUOUS (0x00000000) 61#define U300_TIMER_APP_OSTS_MODE_ONE_SHOT (0x00000020) 62#define U300_TIMER_APP_OSTS_IRQ_ENABLED_IND (0x00000040) 63#define U300_TIMER_APP_OSTS_IRQ_PENDING_IND (0x00000080) 64/* OS Timer Current Count Register 32bit (R/-) */ 65#define U300_TIMER_APP_OSTCC (0x0014) 66/* OS Timer Terminal Count Register 32bit (R/W) */ 67#define U300_TIMER_APP_OSTTC (0x0018) 68/* OS Timer Interrupt Enable Register 32bit (-/W) */ 69#define U300_TIMER_APP_OSTIE (0x001c) 70#define U300_TIMER_APP_OSTIE_IRQ_DISABLE (0x00000000) 71#define U300_TIMER_APP_OSTIE_IRQ_ENABLE (0x00000001) 72/* OS Timer Interrupt Acknowledge Register 32bit (-/W) */ 73#define U300_TIMER_APP_OSTIA (0x0020) 74#define U300_TIMER_APP_OSTIA_IRQ_ACK (0x00000080) 75 76/* Reset DD Timer 32bit (-/W) */ 77#define U300_TIMER_APP_RDDT (0x0040) 78#define U300_TIMER_APP_RDDT_TIMER_RESET (0x00000000) 79/* Enable DD Timer 32bit (-/W) */ 80#define U300_TIMER_APP_EDDT (0x0044) 81#define U300_TIMER_APP_EDDT_TIMER_ENABLE (0x00000000) 82/* Disable DD Timer 32bit (-/W) */ 83#define U300_TIMER_APP_DDDT (0x0048) 84#define U300_TIMER_APP_DDDT_TIMER_DISABLE (0x00000000) 85/* DD Timer Mode Register 32bit (-/W) */ 86#define U300_TIMER_APP_SDDTM (0x004c) 87#define U300_TIMER_APP_SDDTM_MODE_CONTINUOUS (0x00000000) 88#define U300_TIMER_APP_SDDTM_MODE_ONE_SHOT (0x00000001) 89/* DD Timer Status Register 32bit (R/-) */ 90#define U300_TIMER_APP_DDTS (0x0050) 91#define U300_TIMER_APP_DDTS_TIMER_STATE_MASK (0x0000000F) 92#define U300_TIMER_APP_DDTS_TIMER_STATE_IDLE (0x00000001) 93#define U300_TIMER_APP_DDTS_TIMER_STATE_ACTIVE (0x00000002) 94#define U300_TIMER_APP_DDTS_ENABLE_IND (0x00000010) 95#define U300_TIMER_APP_DDTS_MODE_MASK (0x00000020) 96#define U300_TIMER_APP_DDTS_MODE_CONTINUOUS (0x00000000) 97#define U300_TIMER_APP_DDTS_MODE_ONE_SHOT (0x00000020) 98#define U300_TIMER_APP_DDTS_IRQ_ENABLED_IND (0x00000040) 99#define U300_TIMER_APP_DDTS_IRQ_PENDING_IND (0x00000080) 100/* DD Timer Current Count Register 32bit (R/-) */ 101#define U300_TIMER_APP_DDTCC (0x0054) 102/* DD Timer Terminal Count Register 32bit (R/W) */ 103#define U300_TIMER_APP_DDTTC (0x0058) 104/* DD Timer Interrupt Enable Register 32bit (-/W) */ 105#define U300_TIMER_APP_DDTIE (0x005c) 106#define U300_TIMER_APP_DDTIE_IRQ_DISABLE (0x00000000) 107#define U300_TIMER_APP_DDTIE_IRQ_ENABLE (0x00000001) 108/* DD Timer Interrupt Acknowledge Register 32bit (-/W) */ 109#define U300_TIMER_APP_DDTIA (0x0060) 110#define U300_TIMER_APP_DDTIA_IRQ_ACK (0x00000080) 111 112/* Reset GP1 Timer 32bit (-/W) */ 113#define U300_TIMER_APP_RGPT1 (0x0080) 114#define U300_TIMER_APP_RGPT1_TIMER_RESET (0x00000000) 115/* Enable GP1 Timer 32bit (-/W) */ 116#define U300_TIMER_APP_EGPT1 (0x0084) 117#define U300_TIMER_APP_EGPT1_TIMER_ENABLE (0x00000000) 118/* Disable GP1 Timer 32bit (-/W) */ 119#define U300_TIMER_APP_DGPT1 (0x0088) 120#define U300_TIMER_APP_DGPT1_TIMER_DISABLE (0x00000000) 121/* GP1 Timer Mode Register 32bit (-/W) */ 122#define U300_TIMER_APP_SGPT1M (0x008c) 123#define U300_TIMER_APP_SGPT1M_MODE_CONTINUOUS (0x00000000) 124#define U300_TIMER_APP_SGPT1M_MODE_ONE_SHOT (0x00000001) 125/* GP1 Timer Status Register 32bit (R/-) */ 126#define U300_TIMER_APP_GPT1S (0x0090) 127#define U300_TIMER_APP_GPT1S_TIMER_STATE_MASK (0x0000000F) 128#define U300_TIMER_APP_GPT1S_TIMER_STATE_IDLE (0x00000001) 129#define U300_TIMER_APP_GPT1S_TIMER_STATE_ACTIVE (0x00000002) 130#define U300_TIMER_APP_GPT1S_ENABLE_IND (0x00000010) 131#define U300_TIMER_APP_GPT1S_MODE_MASK (0x00000020) 132#define U300_TIMER_APP_GPT1S_MODE_CONTINUOUS (0x00000000) 133#define U300_TIMER_APP_GPT1S_MODE_ONE_SHOT (0x00000020) 134#define U300_TIMER_APP_GPT1S_IRQ_ENABLED_IND (0x00000040) 135#define U300_TIMER_APP_GPT1S_IRQ_PENDING_IND (0x00000080) 136/* GP1 Timer Current Count Register 32bit (R/-) */ 137#define U300_TIMER_APP_GPT1CC (0x0094) 138/* GP1 Timer Terminal Count Register 32bit (R/W) */ 139#define U300_TIMER_APP_GPT1TC (0x0098) 140/* GP1 Timer Interrupt Enable Register 32bit (-/W) */ 141#define U300_TIMER_APP_GPT1IE (0x009c) 142#define U300_TIMER_APP_GPT1IE_IRQ_DISABLE (0x00000000) 143#define U300_TIMER_APP_GPT1IE_IRQ_ENABLE (0x00000001) 144/* GP1 Timer Interrupt Acknowledge Register 32bit (-/W) */ 145#define U300_TIMER_APP_GPT1IA (0x00a0) 146#define U300_TIMER_APP_GPT1IA_IRQ_ACK (0x00000080) 147 148/* Reset GP2 Timer 32bit (-/W) */ 149#define U300_TIMER_APP_RGPT2 (0x00c0) 150#define U300_TIMER_APP_RGPT2_TIMER_RESET (0x00000000) 151/* Enable GP2 Timer 32bit (-/W) */ 152#define U300_TIMER_APP_EGPT2 (0x00c4) 153#define U300_TIMER_APP_EGPT2_TIMER_ENABLE (0x00000000) 154/* Disable GP2 Timer 32bit (-/W) */ 155#define U300_TIMER_APP_DGPT2 (0x00c8) 156#define U300_TIMER_APP_DGPT2_TIMER_DISABLE (0x00000000) 157/* GP2 Timer Mode Register 32bit (-/W) */ 158#define U300_TIMER_APP_SGPT2M (0x00cc) 159#define U300_TIMER_APP_SGPT2M_MODE_CONTINUOUS (0x00000000) 160#define U300_TIMER_APP_SGPT2M_MODE_ONE_SHOT (0x00000001) 161/* GP2 Timer Status Register 32bit (R/-) */ 162#define U300_TIMER_APP_GPT2S (0x00d0) 163#define U300_TIMER_APP_GPT2S_TIMER_STATE_MASK (0x0000000F) 164#define U300_TIMER_APP_GPT2S_TIMER_STATE_IDLE (0x00000001) 165#define U300_TIMER_APP_GPT2S_TIMER_STATE_ACTIVE (0x00000002) 166#define U300_TIMER_APP_GPT2S_ENABLE_IND (0x00000010) 167#define U300_TIMER_APP_GPT2S_MODE_MASK (0x00000020) 168#define U300_TIMER_APP_GPT2S_MODE_CONTINUOUS (0x00000000) 169#define U300_TIMER_APP_GPT2S_MODE_ONE_SHOT (0x00000020) 170#define U300_TIMER_APP_GPT2S_IRQ_ENABLED_IND (0x00000040) 171#define U300_TIMER_APP_GPT2S_IRQ_PENDING_IND (0x00000080) 172/* GP2 Timer Current Count Register 32bit (R/-) */ 173#define U300_TIMER_APP_GPT2CC (0x00d4) 174/* GP2 Timer Terminal Count Register 32bit (R/W) */ 175#define U300_TIMER_APP_GPT2TC (0x00d8) 176/* GP2 Timer Interrupt Enable Register 32bit (-/W) */ 177#define U300_TIMER_APP_GPT2IE (0x00dc) 178#define U300_TIMER_APP_GPT2IE_IRQ_DISABLE (0x00000000) 179#define U300_TIMER_APP_GPT2IE_IRQ_ENABLE (0x00000001) 180/* GP2 Timer Interrupt Acknowledge Register 32bit (-/W) */ 181#define U300_TIMER_APP_GPT2IA (0x00e0) 182#define U300_TIMER_APP_GPT2IA_IRQ_ACK (0x00000080) 183 184/* Clock request control register - all four timers */ 185#define U300_TIMER_APP_CRC (0x100) 186#define U300_TIMER_APP_CRC_CLOCK_REQUEST_ENABLE (0x00000001) 187 188#define TICKS_PER_JIFFY ((CLOCK_TICK_RATE + (HZ/2)) / HZ) 189#define US_PER_TICK ((1000000 + (HZ/2)) / HZ) 190 191/* 192 * The u300_set_mode() function is always called first, if we 193 * have oneshot timer active, the oneshot scheduling function 194 * u300_set_next_event() is called immediately after. 195 */ 196static void u300_set_mode(enum clock_event_mode mode, 197 struct clock_event_device *evt) 198{ 199 switch (mode) { 200 case CLOCK_EVT_MODE_PERIODIC: 201 /* Disable interrupts on GPT1 */ 202 writel(U300_TIMER_APP_GPT1IE_IRQ_DISABLE, 203 U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1IE); 204 /* Disable GP1 while we're reprogramming it. */ 205 writel(U300_TIMER_APP_DGPT1_TIMER_DISABLE, 206 U300_TIMER_APP_VBASE + U300_TIMER_APP_DGPT1); 207 /* 208 * Set the periodic mode to a certain number of ticks per 209 * jiffy. 210 */ 211 writel(TICKS_PER_JIFFY, 212 U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1TC); 213 /* 214 * Set continuous mode, so the timer keeps triggering 215 * interrupts. 216 */ 217 writel(U300_TIMER_APP_SGPT1M_MODE_CONTINUOUS, 218 U300_TIMER_APP_VBASE + U300_TIMER_APP_SGPT1M); 219 /* Enable timer interrupts */ 220 writel(U300_TIMER_APP_GPT1IE_IRQ_ENABLE, 221 U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1IE); 222 /* Then enable the OS timer again */ 223 writel(U300_TIMER_APP_EGPT1_TIMER_ENABLE, 224 U300_TIMER_APP_VBASE + U300_TIMER_APP_EGPT1); 225 break; 226 case CLOCK_EVT_MODE_ONESHOT: 227 /* Just break; here? */ 228 /* 229 * The actual event will be programmed by the next event hook, 230 * so we just set a dummy value somewhere at the end of the 231 * universe here. 232 */ 233 /* Disable interrupts on GPT1 */ 234 writel(U300_TIMER_APP_GPT1IE_IRQ_DISABLE, 235 U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1IE); 236 /* Disable GP1 while we're reprogramming it. */ 237 writel(U300_TIMER_APP_DGPT1_TIMER_DISABLE, 238 U300_TIMER_APP_VBASE + U300_TIMER_APP_DGPT1); 239 /* 240 * Expire far in the future, u300_set_next_event() will be 241 * called soon... 242 */ 243 writel(0xFFFFFFFF, U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1TC); 244 /* We run one shot per tick here! */ 245 writel(U300_TIMER_APP_SGPT1M_MODE_ONE_SHOT, 246 U300_TIMER_APP_VBASE + U300_TIMER_APP_SGPT1M); 247 /* Enable interrupts for this timer */ 248 writel(U300_TIMER_APP_GPT1IE_IRQ_ENABLE, 249 U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1IE); 250 /* Enable timer */ 251 writel(U300_TIMER_APP_EGPT1_TIMER_ENABLE, 252 U300_TIMER_APP_VBASE + U300_TIMER_APP_EGPT1); 253 break; 254 case CLOCK_EVT_MODE_UNUSED: 255 case CLOCK_EVT_MODE_SHUTDOWN: 256 /* Disable interrupts on GP1 */ 257 writel(U300_TIMER_APP_GPT1IE_IRQ_DISABLE, 258 U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1IE); 259 /* Disable GP1 */ 260 writel(U300_TIMER_APP_DGPT1_TIMER_DISABLE, 261 U300_TIMER_APP_VBASE + U300_TIMER_APP_DGPT1); 262 break; 263 case CLOCK_EVT_MODE_RESUME: 264 /* Ignore this call */ 265 break; 266 } 267} 268 269/* 270 * The app timer in one shot mode obviously has to be reprogrammed 271 * in EXACTLY this sequence to work properly. Do NOT try to e.g. replace 272 * the interrupt disable + timer disable commands with a reset command, 273 * it will fail miserably. Apparently (and I found this the hard way) 274 * the timer is very sensitive to the instruction order, though you don't 275 * get that impression from the data sheet. 276 */ 277static int u300_set_next_event(unsigned long cycles, 278 struct clock_event_device *evt) 279 280{ 281 /* Disable interrupts on GPT1 */ 282 writel(U300_TIMER_APP_GPT1IE_IRQ_DISABLE, 283 U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1IE); 284 /* Disable GP1 while we're reprogramming it. */ 285 writel(U300_TIMER_APP_DGPT1_TIMER_DISABLE, 286 U300_TIMER_APP_VBASE + U300_TIMER_APP_DGPT1); 287 /* Reset the General Purpose timer 1. */ 288 writel(U300_TIMER_APP_RGPT1_TIMER_RESET, 289 U300_TIMER_APP_VBASE + U300_TIMER_APP_RGPT1); 290 /* IRQ in n * cycles */ 291 writel(cycles, U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1TC); 292 /* 293 * We run one shot per tick here! (This is necessary to reconfigure, 294 * the timer will tilt if you don't!) 295 */ 296 writel(U300_TIMER_APP_SGPT1M_MODE_ONE_SHOT, 297 U300_TIMER_APP_VBASE + U300_TIMER_APP_SGPT1M); 298 /* Enable timer interrupts */ 299 writel(U300_TIMER_APP_GPT1IE_IRQ_ENABLE, 300 U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1IE); 301 /* Then enable the OS timer again */ 302 writel(U300_TIMER_APP_EGPT1_TIMER_ENABLE, 303 U300_TIMER_APP_VBASE + U300_TIMER_APP_EGPT1); 304 return 0; 305} 306 307 308/* Use general purpose timer 1 as clock event */ 309static struct clock_event_device clockevent_u300_1mhz = { 310 .name = "GPT1", 311 .rating = 300, /* Reasonably fast and accurate clock event */ 312 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, 313 .set_next_event = u300_set_next_event, 314 .set_mode = u300_set_mode, 315}; 316 317/* Clock event timer interrupt handler */ 318static irqreturn_t u300_timer_interrupt(int irq, void *dev_id) 319{ 320 struct clock_event_device *evt = &clockevent_u300_1mhz; 321 /* ACK/Clear timer IRQ for the APP GPT1 Timer */ 322 writel(U300_TIMER_APP_GPT1IA_IRQ_ACK, 323 U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1IA); 324 evt->event_handler(evt); 325 return IRQ_HANDLED; 326} 327 328static struct irqaction u300_timer_irq = { 329 .name = "U300 Timer Tick", 330 .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, 331 .handler = u300_timer_interrupt, 332}; 333 334/* Use general purpose timer 2 as clock source */ 335static cycle_t u300_get_cycles(struct clocksource *cs) 336{ 337 return (cycles_t) readl(U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT2CC); 338} 339 340static struct clocksource clocksource_u300_1mhz = { 341 .name = "GPT2", 342 .rating = 300, /* Reasonably fast and accurate clock source */ 343 .read = u300_get_cycles, 344 .mask = CLOCKSOURCE_MASK(32), /* 32 bits */ 345 .flags = CLOCK_SOURCE_IS_CONTINUOUS, 346}; 347 348/* 349 * Override the global weak sched_clock symbol with this 350 * local implementation which uses the clocksource to get some 351 * better resolution when scheduling the kernel. We accept that 352 * this wraps around for now, since it is just a relative time 353 * stamp. (Inspired by OMAP implementation.) 354 */ 355unsigned long long notrace sched_clock(void) 356{ 357 return clocksource_cyc2ns(clocksource_u300_1mhz.read( 358 &clocksource_u300_1mhz), 359 clocksource_u300_1mhz.mult, 360 clocksource_u300_1mhz.shift); 361} 362 363 364/* 365 * This sets up the system timers, clock source and clock event. 366 */ 367static void __init u300_timer_init(void) 368{ 369 struct clk *clk; 370 unsigned long rate; 371 372 /* Clock the interrupt controller */ 373 clk = clk_get_sys("apptimer", NULL); 374 BUG_ON(IS_ERR(clk)); 375 clk_enable(clk); 376 rate = clk_get_rate(clk); 377 378 /* 379 * Disable the "OS" and "DD" timers - these are designed for Symbian! 380 * Example usage in cnh1601578 cpu subsystem pd_timer_app.c 381 */ 382 writel(U300_TIMER_APP_CRC_CLOCK_REQUEST_ENABLE, 383 U300_TIMER_APP_VBASE + U300_TIMER_APP_CRC); 384 writel(U300_TIMER_APP_ROST_TIMER_RESET, 385 U300_TIMER_APP_VBASE + U300_TIMER_APP_ROST); 386 writel(U300_TIMER_APP_DOST_TIMER_DISABLE, 387 U300_TIMER_APP_VBASE + U300_TIMER_APP_DOST); 388 writel(U300_TIMER_APP_RDDT_TIMER_RESET, 389 U300_TIMER_APP_VBASE + U300_TIMER_APP_RDDT); 390 writel(U300_TIMER_APP_DDDT_TIMER_DISABLE, 391 U300_TIMER_APP_VBASE + U300_TIMER_APP_DDDT); 392 393 /* Reset the General Purpose timer 1. */ 394 writel(U300_TIMER_APP_RGPT1_TIMER_RESET, 395 U300_TIMER_APP_VBASE + U300_TIMER_APP_RGPT1); 396 397 /* Set up the IRQ handler */ 398 setup_irq(IRQ_U300_TIMER_APP_GP1, &u300_timer_irq); 399 400 /* Reset the General Purpose timer 2 */ 401 writel(U300_TIMER_APP_RGPT2_TIMER_RESET, 402 U300_TIMER_APP_VBASE + U300_TIMER_APP_RGPT2); 403 /* Set this timer to run around forever */ 404 writel(0xFFFFFFFFU, U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT2TC); 405 /* Set continuous mode so it wraps around */ 406 writel(U300_TIMER_APP_SGPT2M_MODE_CONTINUOUS, 407 U300_TIMER_APP_VBASE + U300_TIMER_APP_SGPT2M); 408 /* Disable timer interrupts */ 409 writel(U300_TIMER_APP_GPT2IE_IRQ_DISABLE, 410 U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT2IE); 411 /* Then enable the GP2 timer to use as a free running us counter */ 412 writel(U300_TIMER_APP_EGPT2_TIMER_ENABLE, 413 U300_TIMER_APP_VBASE + U300_TIMER_APP_EGPT2); 414 415 clocksource_calc_mult_shift(&clocksource_u300_1mhz, 416 rate, APPTIMER_MIN_RANGE); 417 if (clocksource_register(&clocksource_u300_1mhz)) 418 printk(KERN_ERR "timer: failed to initialize clock " 419 "source %s\n", clocksource_u300_1mhz.name); 420 421 clockevents_calc_mult_shift(&clockevent_u300_1mhz, 422 rate, APPTIMER_MIN_RANGE); 423 /* 32bit counter, so 32bits delta is max */ 424 clockevent_u300_1mhz.max_delta_ns = 425 clockevent_delta2ns(0xffffffff, &clockevent_u300_1mhz); 426 /* This timer is slow enough to set for 1 cycle == 1 MHz */ 427 clockevent_u300_1mhz.min_delta_ns = 428 clockevent_delta2ns(1, &clockevent_u300_1mhz); 429 clockevent_u300_1mhz.cpumask = cpumask_of(0); 430 clockevents_register_device(&clockevent_u300_1mhz); 431 /* 432 * TODO: init and register the rest of the timers too, they can be 433 * used by hrtimers! 434 */ 435} 436 437/* 438 * Very simple system timer that only register the clock event and 439 * clock source. 440 */ 441struct sys_timer u300_timer = { 442 .init = u300_timer_init, 443}; 444