1/* 2 * arch/arm/mach-tegra/include/mach/iomap.h 3 * 4 * Copyright (C) 2010 Google, Inc. 5 * 6 * Author: 7 * Colin Cross <ccross@google.com> 8 * Erik Gilling <konkers@google.com> 9 * 10 * This software is licensed under the terms of the GNU General Public 11 * License version 2, as published by the Free Software Foundation, and 12 * may be copied, distributed, and modified under those terms. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 */ 20 21#ifndef __MACH_TEGRA_IOMAP_H 22#define __MACH_TEGRA_IOMAP_H 23 24#include <asm/sizes.h> 25 26#define TEGRA_ARM_PERIF_BASE 0x50040000 27#define TEGRA_ARM_PERIF_SIZE SZ_8K 28 29#define TEGRA_ARM_INT_DIST_BASE 0x50041000 30#define TEGRA_ARM_INT_DIST_SIZE SZ_4K 31 32#define TEGRA_DISPLAY_BASE 0x54200000 33#define TEGRA_DISPLAY_SIZE SZ_256K 34 35#define TEGRA_DISPLAY2_BASE 0x54240000 36#define TEGRA_DISPLAY2_SIZE SZ_256K 37 38#define TEGRA_PRIMARY_ICTLR_BASE 0x60004000 39#define TEGRA_PRIMARY_ICTLR_SIZE SZ_64 40 41#define TEGRA_SECONDARY_ICTLR_BASE 0x60004100 42#define TEGRA_SECONDARY_ICTLR_SIZE SZ_64 43 44#define TEGRA_TERTIARY_ICTLR_BASE 0x60004200 45#define TEGRA_TERTIARY_ICTLR_SIZE SZ_64 46 47#define TEGRA_QUATERNARY_ICTLR_BASE 0x60004300 48#define TEGRA_QUATERNARY_ICTLR_SIZE SZ_64 49 50#define TEGRA_TMR1_BASE 0x60005000 51#define TEGRA_TMR1_SIZE SZ_8 52 53#define TEGRA_TMR2_BASE 0x60005008 54#define TEGRA_TMR2_SIZE SZ_8 55 56#define TEGRA_TMRUS_BASE 0x60005010 57#define TEGRA_TMRUS_SIZE SZ_64 58 59#define TEGRA_TMR3_BASE 0x60005050 60#define TEGRA_TMR3_SIZE SZ_8 61 62#define TEGRA_TMR4_BASE 0x60005058 63#define TEGRA_TMR4_SIZE SZ_8 64 65#define TEGRA_CLK_RESET_BASE 0x60006000 66#define TEGRA_CLK_RESET_SIZE SZ_4K 67 68#define TEGRA_FLOW_CTRL_BASE 0x60007000 69#define TEGRA_FLOW_CTRL_SIZE 20 70 71#define TEGRA_STATMON_BASE 0x6000C4000 72#define TEGRA_STATMON_SIZE SZ_1K 73 74#define TEGRA_GPIO_BASE 0x6000D000 75#define TEGRA_GPIO_SIZE SZ_4K 76 77#define TEGRA_EXCEPTION_VECTORS_BASE 0x6000F000 78#define TEGRA_EXCEPTION_VECTORS_SIZE SZ_4K 79 80#define TEGRA_APB_MISC_BASE 0x70000000 81#define TEGRA_APB_MISC_SIZE SZ_4K 82 83#define TEGRA_AC97_BASE 0x70002000 84#define TEGRA_AC97_SIZE SZ_512 85 86#define TEGRA_SPDIF_BASE 0x70002400 87#define TEGRA_SPDIF_SIZE SZ_512 88 89#define TEGRA_I2S1_BASE 0x70002800 90#define TEGRA_I2S1_SIZE SZ_256 91 92#define TEGRA_I2S2_BASE 0x70002A00 93#define TEGRA_I2S2_SIZE SZ_256 94 95#define TEGRA_UARTA_BASE 0x70006000 96#define TEGRA_UARTA_SIZE SZ_64 97 98#define TEGRA_UARTB_BASE 0x70006040 99#define TEGRA_UARTB_SIZE SZ_64 100 101#define TEGRA_UARTC_BASE 0x70006200 102#define TEGRA_UARTC_SIZE SZ_256 103 104#define TEGRA_UARTD_BASE 0x70006300 105#define TEGRA_UARTD_SIZE SZ_256 106 107#define TEGRA_UARTE_BASE 0x70006400 108#define TEGRA_UARTE_SIZE SZ_256 109 110#define TEGRA_NAND_BASE 0x70008000 111#define TEGRA_NAND_SIZE SZ_256 112 113#define TEGRA_HSMMC_BASE 0x70008500 114#define TEGRA_HSMMC_SIZE SZ_256 115 116#define TEGRA_SNOR_BASE 0x70009000 117#define TEGRA_SNOR_SIZE SZ_4K 118 119#define TEGRA_PWFM_BASE 0x7000A000 120#define TEGRA_PWFM_SIZE SZ_256 121 122#define TEGRA_MIPI_BASE 0x7000B000 123#define TEGRA_MIPI_SIZE SZ_256 124 125#define TEGRA_I2C_BASE 0x7000C000 126#define TEGRA_I2C_SIZE SZ_256 127 128#define TEGRA_TWC_BASE 0x7000C100 129#define TEGRA_TWC_SIZE SZ_256 130 131#define TEGRA_SPI_BASE 0x7000C380 132#define TEGRA_SPI_SIZE 48 133 134#define TEGRA_I2C2_BASE 0x7000C400 135#define TEGRA_I2C2_SIZE SZ_256 136 137#define TEGRA_I2C3_BASE 0x7000C500 138#define TEGRA_I2C3_SIZE SZ_256 139 140#define TEGRA_OWR_BASE 0x7000D000 141#define TEGRA_OWR_SIZE 80 142 143#define TEGRA_DVC_BASE 0x7000D000 144#define TEGRA_DVC_SIZE SZ_512 145 146#define TEGRA_SPI1_BASE 0x7000D400 147#define TEGRA_SPI1_SIZE SZ_512 148 149#define TEGRA_SPI2_BASE 0x7000D600 150#define TEGRA_SPI2_SIZE SZ_512 151 152#define TEGRA_SPI3_BASE 0x7000D800 153#define TEGRA_SPI3_SIZE SZ_512 154 155#define TEGRA_SPI4_BASE 0x7000DA00 156#define TEGRA_SPI4_SIZE SZ_512 157 158#define TEGRA_RTC_BASE 0x7000E000 159#define TEGRA_RTC_SIZE SZ_256 160 161#define TEGRA_KBC_BASE 0x7000E200 162#define TEGRA_KBC_SIZE SZ_256 163 164#define TEGRA_PMC_BASE 0x7000E400 165#define TEGRA_PMC_SIZE SZ_256 166 167#define TEGRA_MC_BASE 0x7000F000 168#define TEGRA_MC_SIZE SZ_1K 169 170#define TEGRA_EMC_BASE 0x7000F400 171#define TEGRA_EMC_SIZE SZ_1K 172 173#define TEGRA_FUSE_BASE 0x7000F800 174#define TEGRA_FUSE_SIZE SZ_1K 175 176#define TEGRA_KFUSE_BASE 0x7000FC00 177#define TEGRA_KFUSE_SIZE SZ_1K 178 179#define TEGRA_CSITE_BASE 0x70040000 180#define TEGRA_CSITE_SIZE SZ_256K 181 182#define TEGRA_USB_BASE 0xC5000000 183#define TEGRA_USB_SIZE SZ_16K 184 185#define TEGRA_USB1_BASE 0xC5004000 186#define TEGRA_USB1_SIZE SZ_16K 187 188#define TEGRA_USB2_BASE 0xC5008000 189#define TEGRA_USB2_SIZE SZ_16K 190 191#define TEGRA_SDMMC1_BASE 0xC8000000 192#define TEGRA_SDMMC1_SIZE SZ_512 193 194#define TEGRA_SDMMC2_BASE 0xC8000200 195#define TEGRA_SDMMC2_SIZE SZ_512 196 197#define TEGRA_SDMMC3_BASE 0xC8000400 198#define TEGRA_SDMMC3_SIZE SZ_512 199 200#define TEGRA_SDMMC4_BASE 0xC8000600 201#define TEGRA_SDMMC4_SIZE SZ_512 202 203#endif 204