1/* arch/arm/mach-tegra/include/mach/entry-macro.S 2 * 3 * Copyright (C) 2009 Palm, Inc. 4 * 5 * This software is licensed under the terms of the GNU General Public 6 * License version 2, as published by the Free Software Foundation, and 7 * may be copied, distributed, and modified under those terms. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 */ 15#include <mach/iomap.h> 16#include <mach/io.h> 17 18#if defined(CONFIG_ARM_GIC) 19 20#include <asm/hardware/gic.h> 21 22 /* Uses the GIC interrupt controller built into the cpu */ 23#define ICTRL_BASE (IO_CPU_VIRT + 0x100) 24 25 .macro disable_fiq 26 .endm 27 28 .macro get_irqnr_preamble, base, tmp 29 movw \base, #(ICTRL_BASE & 0x0000ffff) 30 movt \base, #((ICTRL_BASE & 0xffff0000) >> 16) 31 .endm 32 33 .macro arch_ret_to_user, tmp1, tmp2 34 .endm 35 36 /* 37 * The interrupt numbering scheme is defined in the 38 * interrupt controller spec. To wit: 39 * 40 * Interrupts 0-15 are IPI 41 * 16-28 are reserved 42 * 29-31 are local. We allow 30 to be used for the watchdog. 43 * 32-1020 are global 44 * 1021-1022 are reserved 45 * 1023 is "spurious" (no interrupt) 46 * 47 * For now, we ignore all local interrupts so only return an interrupt 48 * if it's between 30 and 1020. The test_for_ipi routine below will 49 * pick up on IPIs. 50 * 51 * A simple read from the controller will tell us the number of the 52 * highest priority enabled interrupt. We then just need to check 53 * whether it is in the valid range for an IRQ (30-1020 inclusive). 54 */ 55 56 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp 57 58 /* bits 12-10 = src CPU, 9-0 = int # */ 59 ldr \irqstat, [\base, #GIC_CPU_INTACK] 60 61 ldr \tmp, =1021 62 63 bic \irqnr, \irqstat, #0x1c00 64 65 cmp \irqnr, #29 66 cmpcc \irqnr, \irqnr 67 cmpne \irqnr, \tmp 68 cmpcs \irqnr, \irqnr 69 70 .endm 71 72 /* We assume that irqstat (the raw value of the IRQ acknowledge 73 * register) is preserved from the macro above. 74 * If there is an IPI, we immediately signal end of interrupt on the 75 * controller, since this requires the original irqstat value which 76 * we won't easily be able to recreate later. 77 */ 78 79 .macro test_for_ipi, irqnr, irqstat, base, tmp 80 bic \irqnr, \irqstat, #0x1c00 81 cmp \irqnr, #16 82 strcc \irqstat, [\base, #GIC_CPU_EOI] 83 cmpcs \irqnr, \irqnr 84 .endm 85 86 /* As above, this assumes that irqstat and base are preserved.. */ 87 88 .macro test_for_ltirq, irqnr, irqstat, base, tmp 89 bic \irqnr, \irqstat, #0x1c00 90 mov \tmp, #0 91 cmp \irqnr, #29 92 moveq \tmp, #1 93 streq \irqstat, [\base, #GIC_CPU_EOI] 94 cmp \tmp, #0 95 .endm 96 97#else 98 /* legacy interrupt controller for AP16 */ 99 .macro disable_fiq 100 .endm 101 102 .macro get_irqnr_preamble, base, tmp 103 @ enable imprecise aborts 104 cpsie a 105 @ EVP base at 0xf010f000 106 mov \base, #0xf0000000 107 orr \base, #0x00100000 108 orr \base, #0x0000f000 109 .endm 110 111 .macro arch_ret_to_user, tmp1, tmp2 112 .endm 113 114 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp 115 ldr \irqnr, [\base, #0x20] @ EVT_IRQ_STS 116 cmp \irqnr, #0x80 117 .endm 118#endif 119