1/* 2 * arch/arm/mach-sa1100/include/mach/dma.h 3 * 4 * Generic SA1100 DMA support 5 * 6 * Copyright (C) 2000 Nicolas Pitre 7 * 8 */ 9 10#ifndef __ASM_ARCH_DMA_H 11#define __ASM_ARCH_DMA_H 12 13#include "hardware.h" 14 15 16/* 17 * The SA1100 has six internal DMA channels. 18 */ 19#define SA1100_DMA_CHANNELS 6 20 21/* 22 * Maximum physical DMA buffer size 23 */ 24#define MAX_DMA_SIZE 0x1fff 25#define CUT_DMA_SIZE 0x1000 26 27/* 28 * All possible SA1100 devices a DMA channel can be attached to. 29 */ 30typedef enum { 31 DMA_Ser0UDCWr = DDAR_Ser0UDCWr, /* Ser. port 0 UDC Write */ 32 DMA_Ser0UDCRd = DDAR_Ser0UDCRd, /* Ser. port 0 UDC Read */ 33 DMA_Ser1UARTWr = DDAR_Ser1UARTWr, /* Ser. port 1 UART Write */ 34 DMA_Ser1UARTRd = DDAR_Ser1UARTRd, /* Ser. port 1 UART Read */ 35 DMA_Ser1SDLCWr = DDAR_Ser1SDLCWr, /* Ser. port 1 SDLC Write */ 36 DMA_Ser1SDLCRd = DDAR_Ser1SDLCRd, /* Ser. port 1 SDLC Read */ 37 DMA_Ser2UARTWr = DDAR_Ser2UARTWr, /* Ser. port 2 UART Write */ 38 DMA_Ser2UARTRd = DDAR_Ser2UARTRd, /* Ser. port 2 UART Read */ 39 DMA_Ser2HSSPWr = DDAR_Ser2HSSPWr, /* Ser. port 2 HSSP Write */ 40 DMA_Ser2HSSPRd = DDAR_Ser2HSSPRd, /* Ser. port 2 HSSP Read */ 41 DMA_Ser3UARTWr = DDAR_Ser3UARTWr, /* Ser. port 3 UART Write */ 42 DMA_Ser3UARTRd = DDAR_Ser3UARTRd, /* Ser. port 3 UART Read */ 43 DMA_Ser4MCP0Wr = DDAR_Ser4MCP0Wr, /* Ser. port 4 MCP 0 Write (audio) */ 44 DMA_Ser4MCP0Rd = DDAR_Ser4MCP0Rd, /* Ser. port 4 MCP 0 Read (audio) */ 45 DMA_Ser4MCP1Wr = DDAR_Ser4MCP1Wr, /* Ser. port 4 MCP 1 Write */ 46 DMA_Ser4MCP1Rd = DDAR_Ser4MCP1Rd, /* Ser. port 4 MCP 1 Read */ 47 DMA_Ser4SSPWr = DDAR_Ser4SSPWr, /* Ser. port 4 SSP Write (16 bits) */ 48 DMA_Ser4SSPRd = DDAR_Ser4SSPRd /* Ser. port 4 SSP Read (16 bits) */ 49} dma_device_t; 50 51typedef struct { 52 volatile u_long DDAR; 53 volatile u_long SetDCSR; 54 volatile u_long ClrDCSR; 55 volatile u_long RdDCSR; 56 volatile dma_addr_t DBSA; 57 volatile u_long DBTA; 58 volatile dma_addr_t DBSB; 59 volatile u_long DBTB; 60} dma_regs_t; 61 62typedef void (*dma_callback_t)(void *data); 63 64/* 65 * DMA function prototypes 66 */ 67 68extern int sa1100_request_dma( dma_device_t device, const char *device_id, 69 dma_callback_t callback, void *data, 70 dma_regs_t **regs ); 71extern void sa1100_free_dma( dma_regs_t *regs ); 72extern int sa1100_start_dma( dma_regs_t *regs, dma_addr_t dma_ptr, u_int size ); 73extern dma_addr_t sa1100_get_dma_pos(dma_regs_t *regs); 74extern void sa1100_reset_dma(dma_regs_t *regs); 75 76/** 77 * sa1100_stop_dma - stop DMA in progress 78 * @regs: identifier for the channel to use 79 * 80 * This stops DMA without clearing buffer pointers. Unlike 81 * sa1100_clear_dma() this allows subsequent use of sa1100_resume_dma() 82 * or sa1100_get_dma_pos(). 83 * 84 * The @regs identifier is provided by a successful call to 85 * sa1100_request_dma(). 86 **/ 87 88#define sa1100_stop_dma(regs) ((regs)->ClrDCSR = DCSR_IE|DCSR_RUN) 89 90/** 91 * sa1100_resume_dma - resume DMA on a stopped channel 92 * @regs: identifier for the channel to use 93 * 94 * This resumes DMA on a channel previously stopped with 95 * sa1100_stop_dma(). 96 * 97 * The @regs identifier is provided by a successful call to 98 * sa1100_request_dma(). 99 **/ 100 101#define sa1100_resume_dma(regs) ((regs)->SetDCSR = DCSR_IE|DCSR_RUN) 102 103/** 104 * sa1100_clear_dma - clear DMA pointers 105 * @regs: identifier for the channel to use 106 * 107 * This clear any DMA state so the DMA engine is ready to restart 108 * with new buffers through sa1100_start_dma(). Any buffers in flight 109 * are discarded. 110 * 111 * The @regs identifier is provided by a successful call to 112 * sa1100_request_dma(). 113 **/ 114 115#define sa1100_clear_dma(regs) ((regs)->ClrDCSR = DCSR_IE|DCSR_RUN|DCSR_STRTA|DCSR_STRTB) 116 117#endif /* _ASM_ARCH_DMA_H */ 118