1/* arch/arm/mach-s3c2410/include/mach/regs-gpio.h 2 * 3 * Copyright (c) 2003-2004 Simtec Electronics <linux@simtec.co.uk> 4 * http://www.simtec.co.uk/products/SWLINUX/ 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 * 10 * S3C2410 GPIO register definitions 11*/ 12 13 14#ifndef __ASM_ARCH_REGS_GPIO_H 15#define __ASM_ARCH_REGS_GPIO_H 16 17#include <mach/gpio-nrs.h> 18 19#ifdef CONFIG_CPU_S3C2400 20#define S3C24XX_MISCCR S3C2400_MISCCR 21#else 22#define S3C24XX_MISCCR S3C24XX_GPIOREG2(0x80) 23#endif /* CONFIG_CPU_S3C2400 */ 24 25/* general configuration options */ 26 27#define S3C2410_GPIO_LEAVE (0xFFFFFFFF) 28#define S3C2410_GPIO_INPUT (0xFFFFFFF0) /* not available on A */ 29#define S3C2410_GPIO_OUTPUT (0xFFFFFFF1) 30#define S3C2410_GPIO_IRQ (0xFFFFFFF2) /* not available for all */ 31#define S3C2410_GPIO_SFN2 (0xFFFFFFF2) /* bank A => addr/cs/nand */ 32#define S3C2410_GPIO_SFN3 (0xFFFFFFF3) /* not available on A */ 33 34/* register address for the GPIO registers. 35 * S3C24XX_GPIOREG2 is for the second set of registers in the 36 * GPIO which move between s3c2410 and s3c2412 type systems */ 37 38#define S3C2410_GPIOREG(x) ((x) + S3C24XX_VA_GPIO) 39#define S3C24XX_GPIOREG2(x) ((x) + S3C24XX_VA_GPIO2) 40 41 42/* configure GPIO ports A..G */ 43 44/* port A - S3C2410: 22bits, zero in bit X makes pin X output 45 * S3C2400: 18bits, zero in bit X makes pin X output 46 * 1 makes port special function, this is default 47*/ 48#define S3C2410_GPACON S3C2410_GPIOREG(0x00) 49#define S3C2410_GPADAT S3C2410_GPIOREG(0x04) 50 51#define S3C2400_GPACON S3C2410_GPIOREG(0x00) 52#define S3C2400_GPADAT S3C2410_GPIOREG(0x04) 53 54#define S3C2410_GPA0_ADDR0 (1<<0) 55 56#define S3C2410_GPA1_ADDR16 (1<<1) 57 58#define S3C2410_GPA2_ADDR17 (1<<2) 59 60#define S3C2410_GPA3_ADDR18 (1<<3) 61 62#define S3C2410_GPA4_ADDR19 (1<<4) 63 64#define S3C2410_GPA5_ADDR20 (1<<5) 65 66#define S3C2410_GPA6_ADDR21 (1<<6) 67 68#define S3C2410_GPA7_ADDR22 (1<<7) 69 70#define S3C2410_GPA8_ADDR23 (1<<8) 71 72#define S3C2410_GPA9_ADDR24 (1<<9) 73 74#define S3C2410_GPA10_ADDR25 (1<<10) 75#define S3C2400_GPA10_SCKE (1<<10) 76 77#define S3C2410_GPA11_ADDR26 (1<<11) 78#define S3C2400_GPA11_nCAS0 (1<<11) 79 80#define S3C2410_GPA12_nGCS1 (1<<12) 81#define S3C2400_GPA12_nCAS1 (1<<12) 82 83#define S3C2410_GPA13_nGCS2 (1<<13) 84#define S3C2400_GPA13_nGCS1 (1<<13) 85 86#define S3C2410_GPA14_nGCS3 (1<<14) 87#define S3C2400_GPA14_nGCS2 (1<<14) 88 89#define S3C2410_GPA15_nGCS4 (1<<15) 90#define S3C2400_GPA15_nGCS3 (1<<15) 91 92#define S3C2410_GPA16_nGCS5 (1<<16) 93#define S3C2400_GPA16_nGCS4 (1<<16) 94 95#define S3C2410_GPA17_CLE (1<<17) 96#define S3C2400_GPA17_nGCS5 (1<<17) 97 98#define S3C2410_GPA18_ALE (1<<18) 99 100#define S3C2410_GPA19_nFWE (1<<19) 101 102#define S3C2410_GPA20_nFRE (1<<20) 103 104#define S3C2410_GPA21_nRSTOUT (1<<21) 105 106#define S3C2410_GPA22_nFCE (1<<22) 107 108/* 0x08 and 0x0c are reserved on S3C2410 */ 109 110/* S3C2410: 111 * GPB is 10 IO pins, each configured by 2 bits each in GPBCON. 112 * 00 = input, 01 = output, 10=special function, 11=reserved 113 114 * S3C2400: 115 * GPB is 16 IO pins, each configured by 2 bits each in GPBCON. 116 * 00 = input, 01 = output, 10=data, 11=special function 117 118 * bit 0,1 = pin 0, 2,3= pin 1... 119 * 120 * CPBUP = pull up resistor control, 1=disabled, 0=enabled 121*/ 122 123#define S3C2410_GPBCON S3C2410_GPIOREG(0x10) 124#define S3C2410_GPBDAT S3C2410_GPIOREG(0x14) 125#define S3C2410_GPBUP S3C2410_GPIOREG(0x18) 126 127#define S3C2400_GPBCON S3C2410_GPIOREG(0x08) 128#define S3C2400_GPBDAT S3C2410_GPIOREG(0x0C) 129#define S3C2400_GPBUP S3C2410_GPIOREG(0x10) 130 131/* no i/o pin in port b can have value 3 (unless it is a s3c2443) ! */ 132 133#define S3C2410_GPB0_TOUT0 (0x02 << 0) 134#define S3C2400_GPB0_DATA16 (0x02 << 0) 135 136#define S3C2410_GPB1_TOUT1 (0x02 << 2) 137#define S3C2400_GPB1_DATA17 (0x02 << 2) 138 139#define S3C2410_GPB2_TOUT2 (0x02 << 4) 140#define S3C2400_GPB2_DATA18 (0x02 << 4) 141#define S3C2400_GPB2_TCLK1 (0x03 << 4) 142 143#define S3C2410_GPB3_TOUT3 (0x02 << 6) 144#define S3C2400_GPB3_DATA19 (0x02 << 6) 145#define S3C2400_GPB3_TXD1 (0x03 << 6) 146 147#define S3C2410_GPB4_TCLK0 (0x02 << 8) 148#define S3C2400_GPB4_DATA20 (0x02 << 8) 149#define S3C2410_GPB4_MASK (0x03 << 8) 150#define S3C2400_GPB4_RXD1 (0x03 << 8) 151#define S3C2400_GPB4_MASK (0x03 << 8) 152 153#define S3C2410_GPB5_nXBACK (0x02 << 10) 154#define S3C2443_GPB5_XBACK (0x03 << 10) 155#define S3C2400_GPB5_DATA21 (0x02 << 10) 156#define S3C2400_GPB5_nCTS1 (0x03 << 10) 157 158#define S3C2410_GPB6_nXBREQ (0x02 << 12) 159#define S3C2443_GPB6_XBREQ (0x03 << 12) 160#define S3C2400_GPB6_DATA22 (0x02 << 12) 161#define S3C2400_GPB6_nRTS1 (0x03 << 12) 162 163#define S3C2410_GPB7_nXDACK1 (0x02 << 14) 164#define S3C2443_GPB7_XDACK1 (0x03 << 14) 165#define S3C2400_GPB7_DATA23 (0x02 << 14) 166 167#define S3C2410_GPB8_nXDREQ1 (0x02 << 16) 168#define S3C2400_GPB8_DATA24 (0x02 << 16) 169 170#define S3C2410_GPB9_nXDACK0 (0x02 << 18) 171#define S3C2443_GPB9_XDACK0 (0x03 << 18) 172#define S3C2400_GPB9_DATA25 (0x02 << 18) 173#define S3C2400_GPB9_I2SSDI (0x03 << 18) 174 175#define S3C2410_GPB10_nXDRE0 (0x02 << 20) 176#define S3C2443_GPB10_XDREQ0 (0x03 << 20) 177#define S3C2400_GPB10_DATA26 (0x02 << 20) 178#define S3C2400_GPB10_nSS (0x03 << 20) 179 180#define S3C2400_GPB11_INP (0x00 << 22) 181#define S3C2400_GPB11_OUTP (0x01 << 22) 182#define S3C2400_GPB11_DATA27 (0x02 << 22) 183 184#define S3C2400_GPB12_INP (0x00 << 24) 185#define S3C2400_GPB12_OUTP (0x01 << 24) 186#define S3C2400_GPB12_DATA28 (0x02 << 24) 187 188#define S3C2400_GPB13_INP (0x00 << 26) 189#define S3C2400_GPB13_OUTP (0x01 << 26) 190#define S3C2400_GPB13_DATA29 (0x02 << 26) 191 192#define S3C2400_GPB14_INP (0x00 << 28) 193#define S3C2400_GPB14_OUTP (0x01 << 28) 194#define S3C2400_GPB14_DATA30 (0x02 << 28) 195 196#define S3C2400_GPB15_INP (0x00 << 30) 197#define S3C2400_GPB15_OUTP (0x01 << 30) 198#define S3C2400_GPB15_DATA31 (0x02 << 30) 199 200#define S3C2410_GPB_PUPDIS(x) (1<<(x)) 201 202/* Port C consits of 16 GPIO/Special function 203 * 204 * almost identical setup to port b, but the special functions are mostly 205 * to do with the video system's sync/etc. 206*/ 207 208#define S3C2410_GPCCON S3C2410_GPIOREG(0x20) 209#define S3C2410_GPCDAT S3C2410_GPIOREG(0x24) 210#define S3C2410_GPCUP S3C2410_GPIOREG(0x28) 211 212#define S3C2400_GPCCON S3C2410_GPIOREG(0x14) 213#define S3C2400_GPCDAT S3C2410_GPIOREG(0x18) 214#define S3C2400_GPCUP S3C2410_GPIOREG(0x1C) 215 216#define S3C2410_GPC0_LEND (0x02 << 0) 217#define S3C2400_GPC0_VD0 (0x02 << 0) 218 219#define S3C2410_GPC1_VCLK (0x02 << 2) 220#define S3C2400_GPC1_VD1 (0x02 << 2) 221 222#define S3C2410_GPC2_VLINE (0x02 << 4) 223#define S3C2400_GPC2_VD2 (0x02 << 4) 224 225#define S3C2410_GPC3_VFRAME (0x02 << 6) 226#define S3C2400_GPC3_VD3 (0x02 << 6) 227 228#define S3C2410_GPC4_VM (0x02 << 8) 229#define S3C2400_GPC4_VD4 (0x02 << 8) 230 231#define S3C2410_GPC5_LCDVF0 (0x02 << 10) 232#define S3C2400_GPC5_VD5 (0x02 << 10) 233 234#define S3C2410_GPC6_LCDVF1 (0x02 << 12) 235#define S3C2400_GPC6_VD6 (0x02 << 12) 236 237#define S3C2410_GPC7_LCDVF2 (0x02 << 14) 238#define S3C2400_GPC7_VD7 (0x02 << 14) 239 240#define S3C2410_GPC8_VD0 (0x02 << 16) 241#define S3C2400_GPC8_VD8 (0x02 << 16) 242 243#define S3C2410_GPC9_VD1 (0x02 << 18) 244#define S3C2400_GPC9_VD9 (0x02 << 18) 245 246#define S3C2410_GPC10_VD2 (0x02 << 20) 247#define S3C2400_GPC10_VD10 (0x02 << 20) 248 249#define S3C2410_GPC11_VD3 (0x02 << 22) 250#define S3C2400_GPC11_VD11 (0x02 << 22) 251 252#define S3C2410_GPC12_VD4 (0x02 << 24) 253#define S3C2400_GPC12_VD12 (0x02 << 24) 254 255#define S3C2410_GPC13_VD5 (0x02 << 26) 256#define S3C2400_GPC13_VD13 (0x02 << 26) 257 258#define S3C2410_GPC14_VD6 (0x02 << 28) 259#define S3C2400_GPC14_VD14 (0x02 << 28) 260 261#define S3C2410_GPC15_VD7 (0x02 << 30) 262#define S3C2400_GPC15_VD15 (0x02 << 30) 263 264#define S3C2410_GPC_PUPDIS(x) (1<<(x)) 265 266/* 267 * S3C2410: Port D consists of 16 GPIO/Special function 268 * 269 * almost identical setup to port b, but the special functions are mostly 270 * to do with the video system's data. 271 * 272 * S3C2400: Port D consists of 11 GPIO/Special function 273 * 274 * almost identical setup to port c 275*/ 276 277#define S3C2410_GPDCON S3C2410_GPIOREG(0x30) 278#define S3C2410_GPDDAT S3C2410_GPIOREG(0x34) 279#define S3C2410_GPDUP S3C2410_GPIOREG(0x38) 280 281#define S3C2400_GPDCON S3C2410_GPIOREG(0x20) 282#define S3C2400_GPDDAT S3C2410_GPIOREG(0x24) 283#define S3C2400_GPDUP S3C2410_GPIOREG(0x28) 284 285#define S3C2410_GPD0_VD8 (0x02 << 0) 286#define S3C2400_GPD0_VFRAME (0x02 << 0) 287#define S3C2442_GPD0_nSPICS1 (0x03 << 0) 288 289#define S3C2410_GPD1_VD9 (0x02 << 2) 290#define S3C2400_GPD1_VM (0x02 << 2) 291#define S3C2442_GPD1_SPICLK1 (0x03 << 2) 292 293#define S3C2410_GPD2_VD10 (0x02 << 4) 294#define S3C2400_GPD2_VLINE (0x02 << 4) 295 296#define S3C2410_GPD3_VD11 (0x02 << 6) 297#define S3C2400_GPD3_VCLK (0x02 << 6) 298 299#define S3C2410_GPD4_VD12 (0x02 << 8) 300#define S3C2400_GPD4_LEND (0x02 << 8) 301 302#define S3C2410_GPD5_VD13 (0x02 << 10) 303#define S3C2400_GPD5_TOUT0 (0x02 << 10) 304 305#define S3C2410_GPD6_VD14 (0x02 << 12) 306#define S3C2400_GPD6_TOUT1 (0x02 << 12) 307 308#define S3C2410_GPD7_VD15 (0x02 << 14) 309#define S3C2400_GPD7_TOUT2 (0x02 << 14) 310 311#define S3C2410_GPD8_VD16 (0x02 << 16) 312#define S3C2400_GPD8_TOUT3 (0x02 << 16) 313#define S3C2440_GPD8_SPIMISO1 (0x03 << 16) 314 315#define S3C2410_GPD9_VD17 (0x02 << 18) 316#define S3C2400_GPD9_TCLK0 (0x02 << 18) 317#define S3C2440_GPD9_SPIMOSI1 (0x03 << 18) 318 319#define S3C2410_GPD10_VD18 (0x02 << 20) 320#define S3C2400_GPD10_nWAIT (0x02 << 20) 321#define S3C2440_GPD10_SPICLK1 (0x03 << 20) 322 323#define S3C2410_GPD11_VD19 (0x02 << 22) 324 325#define S3C2410_GPD12_VD20 (0x02 << 24) 326 327#define S3C2410_GPD13_VD21 (0x02 << 26) 328 329#define S3C2410_GPD14_VD22 (0x02 << 28) 330#define S3C2410_GPD14_nSS1 (0x03 << 28) 331 332#define S3C2410_GPD15_VD23 (0x02 << 30) 333#define S3C2410_GPD15_nSS0 (0x03 << 30) 334 335#define S3C2410_GPD_PUPDIS(x) (1<<(x)) 336 337/* S3C2410: 338 * Port E consists of 16 GPIO/Special function 339 * 340 * again, the same as port B, but dealing with I2S, SDI, and 341 * more miscellaneous functions 342 * 343 * S3C2400: 344 * Port E consists of 12 GPIO/Special function 345 * 346 * GPIO / interrupt inputs 347*/ 348 349#define S3C2410_GPECON S3C2410_GPIOREG(0x40) 350#define S3C2410_GPEDAT S3C2410_GPIOREG(0x44) 351#define S3C2410_GPEUP S3C2410_GPIOREG(0x48) 352 353#define S3C2400_GPECON S3C2410_GPIOREG(0x2C) 354#define S3C2400_GPEDAT S3C2410_GPIOREG(0x30) 355#define S3C2400_GPEUP S3C2410_GPIOREG(0x34) 356 357#define S3C2410_GPE0_I2SLRCK (0x02 << 0) 358#define S3C2443_GPE0_AC_nRESET (0x03 << 0) 359#define S3C2400_GPE0_EINT0 (0x02 << 0) 360#define S3C2410_GPE0_MASK (0x03 << 0) 361 362#define S3C2410_GPE1_I2SSCLK (0x02 << 2) 363#define S3C2443_GPE1_AC_SYNC (0x03 << 2) 364#define S3C2400_GPE1_EINT1 (0x02 << 2) 365#define S3C2400_GPE1_nSS (0x03 << 2) 366#define S3C2410_GPE1_MASK (0x03 << 2) 367 368#define S3C2410_GPE2_CDCLK (0x02 << 4) 369#define S3C2443_GPE2_AC_BITCLK (0x03 << 4) 370#define S3C2400_GPE2_EINT2 (0x02 << 4) 371#define S3C2400_GPE2_I2SSDI (0x03 << 4) 372 373#define S3C2410_GPE3_I2SSDI (0x02 << 6) 374#define S3C2443_GPE3_AC_SDI (0x03 << 6) 375#define S3C2400_GPE3_EINT3 (0x02 << 6) 376#define S3C2400_GPE3_nCTS1 (0x03 << 6) 377#define S3C2410_GPE3_nSS0 (0x03 << 6) 378#define S3C2410_GPE3_MASK (0x03 << 6) 379 380#define S3C2410_GPE4_I2SSDO (0x02 << 8) 381#define S3C2443_GPE4_AC_SDO (0x03 << 8) 382#define S3C2400_GPE4_EINT4 (0x02 << 8) 383#define S3C2400_GPE4_nRTS1 (0x03 << 8) 384#define S3C2410_GPE4_I2SSDI (0x03 << 8) 385#define S3C2410_GPE4_MASK (0x03 << 8) 386 387#define S3C2410_GPE5_SDCLK (0x02 << 10) 388#define S3C2443_GPE5_SD1_CLK (0x02 << 10) 389#define S3C2400_GPE5_EINT5 (0x02 << 10) 390#define S3C2400_GPE5_TCLK1 (0x03 << 10) 391#define S3C2443_GPE5_AC_BITCLK (0x03 << 10) 392 393#define S3C2410_GPE6_SDCMD (0x02 << 12) 394#define S3C2443_GPE6_SD1_CMD (0x02 << 12) 395#define S3C2443_GPE6_AC_SDI (0x03 << 12) 396#define S3C2400_GPE6_EINT6 (0x02 << 12) 397 398#define S3C2410_GPE7_SDDAT0 (0x02 << 14) 399#define S3C2443_GPE5_SD1_DAT0 (0x02 << 14) 400#define S3C2443_GPE7_AC_SDO (0x03 << 14) 401#define S3C2400_GPE7_EINT7 (0x02 << 14) 402 403#define S3C2410_GPE8_SDDAT1 (0x02 << 16) 404#define S3C2443_GPE8_SD1_DAT1 (0x02 << 16) 405#define S3C2443_GPE8_AC_SYNC (0x03 << 16) 406#define S3C2400_GPE8_nXDACK0 (0x02 << 16) 407 408#define S3C2410_GPE9_SDDAT2 (0x02 << 18) 409#define S3C2443_GPE9_SD1_DAT2 (0x02 << 18) 410#define S3C2443_GPE9_AC_nRESET (0x03 << 18) 411#define S3C2400_GPE9_nXDACK1 (0x02 << 18) 412#define S3C2400_GPE9_nXBACK (0x03 << 18) 413 414#define S3C2410_GPE10_SDDAT3 (0x02 << 20) 415#define S3C2443_GPE10_SD1_DAT3 (0x02 << 20) 416#define S3C2400_GPE10_nXDREQ0 (0x02 << 20) 417 418#define S3C2410_GPE11_SPIMISO0 (0x02 << 22) 419#define S3C2400_GPE11_nXDREQ1 (0x02 << 22) 420#define S3C2400_GPE11_nXBREQ (0x03 << 22) 421 422#define S3C2410_GPE12_SPIMOSI0 (0x02 << 24) 423 424#define S3C2410_GPE13_SPICLK0 (0x02 << 26) 425 426#define S3C2410_GPE14_IICSCL (0x02 << 28) 427#define S3C2410_GPE14_MASK (0x03 << 28) 428 429#define S3C2410_GPE15_IICSDA (0x02 << 30) 430#define S3C2410_GPE15_MASK (0x03 << 30) 431 432#define S3C2440_GPE0_ACSYNC (0x03 << 0) 433#define S3C2440_GPE1_ACBITCLK (0x03 << 2) 434#define S3C2440_GPE2_ACRESET (0x03 << 4) 435#define S3C2440_GPE3_ACIN (0x03 << 6) 436#define S3C2440_GPE4_ACOUT (0x03 << 8) 437 438#define S3C2410_GPE_PUPDIS(x) (1<<(x)) 439 440/* S3C2410: 441 * Port F consists of 8 GPIO/Special function 442 * 443 * GPIO / interrupt inputs 444 * 445 * GPFCON has 2 bits for each of the input pins on port F 446 * 00 = 0 input, 1 output, 2 interrupt (EINT0..7), 3 undefined 447 * 448 * pull up works like all other ports. 449 * 450 * S3C2400: 451 * Port F consists of 7 GPIO/Special function 452 * 453 * GPIO/serial/misc pins 454*/ 455 456#define S3C2410_GPFCON S3C2410_GPIOREG(0x50) 457#define S3C2410_GPFDAT S3C2410_GPIOREG(0x54) 458#define S3C2410_GPFUP S3C2410_GPIOREG(0x58) 459 460#define S3C2400_GPFCON S3C2410_GPIOREG(0x38) 461#define S3C2400_GPFDAT S3C2410_GPIOREG(0x3C) 462#define S3C2400_GPFUP S3C2410_GPIOREG(0x40) 463 464#define S3C2410_GPF0_EINT0 (0x02 << 0) 465#define S3C2400_GPF0_RXD0 (0x02 << 0) 466 467#define S3C2410_GPF1_EINT1 (0x02 << 2) 468#define S3C2400_GPF1_RXD1 (0x02 << 2) 469#define S3C2400_GPF1_IICSDA (0x03 << 2) 470 471#define S3C2410_GPF2_EINT2 (0x02 << 4) 472#define S3C2400_GPF2_TXD0 (0x02 << 4) 473 474#define S3C2410_GPF3_EINT3 (0x02 << 6) 475#define S3C2400_GPF3_TXD1 (0x02 << 6) 476#define S3C2400_GPF3_IICSCL (0x03 << 6) 477 478#define S3C2410_GPF4_EINT4 (0x02 << 8) 479#define S3C2400_GPF4_nRTS0 (0x02 << 8) 480#define S3C2400_GPF4_nXBACK (0x03 << 8) 481 482#define S3C2410_GPF5_EINT5 (0x02 << 10) 483#define S3C2400_GPF5_nCTS0 (0x02 << 10) 484#define S3C2400_GPF5_nXBREQ (0x03 << 10) 485 486#define S3C2410_GPF6_EINT6 (0x02 << 12) 487#define S3C2400_GPF6_CLKOUT (0x02 << 12) 488 489#define S3C2410_GPF7_EINT7 (0x02 << 14) 490 491#define S3C2410_GPF_PUPDIS(x) (1<<(x)) 492 493/* S3C2410: 494 * Port G consists of 8 GPIO/IRQ/Special function 495 * 496 * GPGCON has 2 bits for each of the input pins on port F 497 * 00 = 0 input, 1 output, 2 interrupt (EINT0..7), 3 special func 498 * 499 * pull up works like all other ports. 500 * 501 * S3C2400: 502 * Port G consists of 10 GPIO/Special function 503*/ 504 505#define S3C2410_GPGCON S3C2410_GPIOREG(0x60) 506#define S3C2410_GPGDAT S3C2410_GPIOREG(0x64) 507#define S3C2410_GPGUP S3C2410_GPIOREG(0x68) 508 509#define S3C2400_GPGCON S3C2410_GPIOREG(0x44) 510#define S3C2400_GPGDAT S3C2410_GPIOREG(0x48) 511#define S3C2400_GPGUP S3C2410_GPIOREG(0x4C) 512 513#define S3C2410_GPG0_EINT8 (0x02 << 0) 514#define S3C2400_GPG0_I2SLRCK (0x02 << 0) 515 516#define S3C2410_GPG1_EINT9 (0x02 << 2) 517#define S3C2400_GPG1_I2SSCLK (0x02 << 2) 518 519#define S3C2410_GPG2_EINT10 (0x02 << 4) 520#define S3C2410_GPG2_nSS0 (0x03 << 4) 521#define S3C2400_GPG2_CDCLK (0x02 << 4) 522 523#define S3C2410_GPG3_EINT11 (0x02 << 6) 524#define S3C2410_GPG3_nSS1 (0x03 << 6) 525#define S3C2400_GPG3_I2SSDO (0x02 << 6) 526#define S3C2400_GPG3_I2SSDI (0x03 << 6) 527 528#define S3C2410_GPG4_EINT12 (0x02 << 8) 529#define S3C2400_GPG4_MMCCLK (0x02 << 8) 530#define S3C2400_GPG4_I2SSDI (0x03 << 8) 531#define S3C2410_GPG4_LCDPWREN (0x03 << 8) 532#define S3C2443_GPG4_LCDPWRDN (0x03 << 8) 533 534#define S3C2410_GPG5_EINT13 (0x02 << 10) 535#define S3C2400_GPG5_MMCCMD (0x02 << 10) 536#define S3C2400_GPG5_IICSDA (0x03 << 10) 537#define S3C2410_GPG5_SPIMISO1 (0x03 << 10) /* not s3c2443 */ 538 539#define S3C2410_GPG6_EINT14 (0x02 << 12) 540#define S3C2400_GPG6_MMCDAT (0x02 << 12) 541#define S3C2400_GPG6_IICSCL (0x03 << 12) 542#define S3C2410_GPG6_SPIMOSI1 (0x03 << 12) 543 544#define S3C2410_GPG7_EINT15 (0x02 << 14) 545#define S3C2410_GPG7_SPICLK1 (0x03 << 14) 546#define S3C2400_GPG7_SPIMISO (0x02 << 14) 547#define S3C2400_GPG7_IICSDA (0x03 << 14) 548 549#define S3C2410_GPG8_EINT16 (0x02 << 16) 550#define S3C2400_GPG8_SPIMOSI (0x02 << 16) 551#define S3C2400_GPG8_IICSCL (0x03 << 16) 552 553#define S3C2410_GPG9_EINT17 (0x02 << 18) 554#define S3C2400_GPG9_SPICLK (0x02 << 18) 555#define S3C2400_GPG9_MMCCLK (0x03 << 18) 556 557#define S3C2410_GPG10_EINT18 (0x02 << 20) 558 559#define S3C2410_GPG11_EINT19 (0x02 << 22) 560#define S3C2410_GPG11_TCLK1 (0x03 << 22) 561#define S3C2443_GPG11_CF_nIREQ (0x03 << 22) 562 563#define S3C2410_GPG12_EINT20 (0x02 << 24) 564#define S3C2410_GPG12_XMON (0x03 << 24) 565#define S3C2442_GPG12_nSPICS0 (0x03 << 24) 566#define S3C2443_GPG12_nINPACK (0x03 << 24) 567 568#define S3C2410_GPG13_EINT21 (0x02 << 26) 569#define S3C2410_GPG13_nXPON (0x03 << 26) 570#define S3C2443_GPG13_CF_nREG (0x03 << 26) 571 572#define S3C2410_GPG14_EINT22 (0x02 << 28) 573#define S3C2410_GPG14_YMON (0x03 << 28) 574#define S3C2443_GPG14_CF_RESET (0x03 << 28) 575 576#define S3C2410_GPG15_EINT23 (0x02 << 30) 577#define S3C2410_GPG15_nYPON (0x03 << 30) 578#define S3C2443_GPG15_CF_PWR (0x03 << 30) 579 580#define S3C2410_GPG_PUPDIS(x) (1<<(x)) 581 582/* Port H consists of11 GPIO/serial/Misc pins 583 * 584 * GPGCON has 2 bits for each of the input pins on port F 585 * 00 = 0 input, 1 output, 2 interrupt (EINT0..7), 3 special func 586 * 587 * pull up works like all other ports. 588*/ 589 590#define S3C2410_GPHCON S3C2410_GPIOREG(0x70) 591#define S3C2410_GPHDAT S3C2410_GPIOREG(0x74) 592#define S3C2410_GPHUP S3C2410_GPIOREG(0x78) 593 594#define S3C2410_GPH0_nCTS0 (0x02 << 0) 595#define S3C2416_GPH0_TXD0 (0x02 << 0) 596 597#define S3C2410_GPH1_nRTS0 (0x02 << 2) 598#define S3C2416_GPH1_RXD0 (0x02 << 2) 599 600#define S3C2410_GPH2_TXD0 (0x02 << 4) 601#define S3C2416_GPH2_TXD1 (0x02 << 4) 602 603#define S3C2410_GPH3_RXD0 (0x02 << 6) 604#define S3C2416_GPH3_RXD1 (0x02 << 6) 605 606#define S3C2410_GPH4_TXD1 (0x02 << 8) 607#define S3C2416_GPH4_TXD2 (0x02 << 8) 608 609#define S3C2410_GPH5_RXD1 (0x02 << 10) 610#define S3C2416_GPH5_RXD2 (0x02 << 10) 611 612#define S3C2410_GPH6_TXD2 (0x02 << 12) 613#define S3C2416_GPH6_TXD3 (0x02 << 12) 614#define S3C2410_GPH6_nRTS1 (0x03 << 12) 615#define S3C2416_GPH6_nRTS2 (0x03 << 12) 616 617#define S3C2410_GPH7_RXD2 (0x02 << 14) 618#define S3C2416_GPH7_RXD3 (0x02 << 14) 619#define S3C2410_GPH7_nCTS1 (0x03 << 14) 620#define S3C2416_GPH7_nCTS2 (0x03 << 14) 621 622#define S3C2410_GPH8_UCLK (0x02 << 16) 623#define S3C2416_GPH8_nCTS0 (0x02 << 16) 624 625#define S3C2410_GPH9_CLKOUT0 (0x02 << 18) 626#define S3C2442_GPH9_nSPICS0 (0x03 << 18) 627#define S3C2416_GPH9_nRTS0 (0x02 << 18) 628 629#define S3C2410_GPH10_CLKOUT1 (0x02 << 20) 630#define S3C2416_GPH10_nCTS1 (0x02 << 20) 631 632#define S3C2416_GPH11_nRTS1 (0x02 << 22) 633 634#define S3C2416_GPH12_EXTUARTCLK (0x02 << 24) 635 636#define S3C2416_GPH13_CLKOUT0 (0x02 << 26) 637 638#define S3C2416_GPH14_CLKOUT1 (0x02 << 28) 639 640/* The S3C2412 and S3C2413 move the GPJ register set to after 641 * GPH, which means all registers after 0x80 are now offset by 0x10 642 * for the 2412/2413 from the 2410/2440/2442 643*/ 644 645/* S3C2443 and above */ 646#define S3C2440_GPJCON S3C2410_GPIOREG(0xD0) 647#define S3C2440_GPJDAT S3C2410_GPIOREG(0xD4) 648#define S3C2440_GPJUP S3C2410_GPIOREG(0xD8) 649 650#define S3C2443_GPKCON S3C2410_GPIOREG(0xE0) 651#define S3C2443_GPKDAT S3C2410_GPIOREG(0xE4) 652#define S3C2443_GPKUP S3C2410_GPIOREG(0xE8) 653 654#define S3C2443_GPLCON S3C2410_GPIOREG(0xF0) 655#define S3C2443_GPLDAT S3C2410_GPIOREG(0xF4) 656#define S3C2443_GPLUP S3C2410_GPIOREG(0xF8) 657 658#define S3C2443_GPMCON S3C2410_GPIOREG(0x100) 659#define S3C2443_GPMDAT S3C2410_GPIOREG(0x104) 660#define S3C2443_GPMUP S3C2410_GPIOREG(0x108) 661 662/* miscellaneous control */ 663#define S3C2400_MISCCR S3C2410_GPIOREG(0x54) 664#define S3C2410_MISCCR S3C2410_GPIOREG(0x80) 665#define S3C2410_DCLKCON S3C2410_GPIOREG(0x84) 666 667#define S3C24XX_DCLKCON S3C24XX_GPIOREG2(0x84) 668 669/* see clock.h for dclk definitions */ 670 671/* pullup control on databus */ 672#define S3C2410_MISCCR_SPUCR_HEN (0<<0) 673#define S3C2410_MISCCR_SPUCR_HDIS (1<<0) 674#define S3C2410_MISCCR_SPUCR_LEN (0<<1) 675#define S3C2410_MISCCR_SPUCR_LDIS (1<<1) 676 677#define S3C2400_MISCCR_SPUCR_LEN (0<<0) 678#define S3C2400_MISCCR_SPUCR_LDIS (1<<0) 679#define S3C2400_MISCCR_SPUCR_HEN (0<<1) 680#define S3C2400_MISCCR_SPUCR_HDIS (1<<1) 681 682#define S3C2400_MISCCR_HZ_STOPEN (0<<2) 683#define S3C2400_MISCCR_HZ_STOPPREV (1<<2) 684 685#define S3C2410_MISCCR_USBDEV (0<<3) 686#define S3C2410_MISCCR_USBHOST (1<<3) 687 688#define S3C2410_MISCCR_CLK0_MPLL (0<<4) 689#define S3C2410_MISCCR_CLK0_UPLL (1<<4) 690#define S3C2410_MISCCR_CLK0_FCLK (2<<4) 691#define S3C2410_MISCCR_CLK0_HCLK (3<<4) 692#define S3C2410_MISCCR_CLK0_PCLK (4<<4) 693#define S3C2410_MISCCR_CLK0_DCLK0 (5<<4) 694#define S3C2410_MISCCR_CLK0_MASK (7<<4) 695 696#define S3C2412_MISCCR_CLK0_RTC (2<<4) 697 698#define S3C2410_MISCCR_CLK1_MPLL (0<<8) 699#define S3C2410_MISCCR_CLK1_UPLL (1<<8) 700#define S3C2410_MISCCR_CLK1_FCLK (2<<8) 701#define S3C2410_MISCCR_CLK1_HCLK (3<<8) 702#define S3C2410_MISCCR_CLK1_PCLK (4<<8) 703#define S3C2410_MISCCR_CLK1_DCLK1 (5<<8) 704#define S3C2410_MISCCR_CLK1_MASK (7<<8) 705 706#define S3C2412_MISCCR_CLK1_CLKsrc (0<<8) 707 708#define S3C2410_MISCCR_USBSUSPND0 (1<<12) 709#define S3C2416_MISCCR_SEL_SUSPND (1<<12) 710#define S3C2410_MISCCR_USBSUSPND1 (1<<13) 711 712#define S3C2410_MISCCR_nRSTCON (1<<16) 713 714#define S3C2410_MISCCR_nEN_SCLK0 (1<<17) 715#define S3C2410_MISCCR_nEN_SCLK1 (1<<18) 716#define S3C2410_MISCCR_nEN_SCLKE (1<<19) /* not 2412 */ 717#define S3C2410_MISCCR_SDSLEEP (7<<17) 718 719#define S3C2416_MISCCR_FLT_I2C (1<<24) 720#define S3C2416_MISCCR_HSSPI_EN2 (1<<31) 721 722/* external interrupt control... */ 723/* S3C2410_EXTINT0 -> irq sense control for EINT0..EINT7 724 * S3C2410_EXTINT1 -> irq sense control for EINT8..EINT15 725 * S3C2410_EXTINT2 -> irq sense control for EINT16..EINT23 726 * 727 * note S3C2410_EXTINT2 has filtering options for EINT16..EINT23 728 * 729 * Samsung datasheet p9-25 730*/ 731#define S3C2400_EXTINT0 S3C2410_GPIOREG(0x58) 732#define S3C2410_EXTINT0 S3C2410_GPIOREG(0x88) 733#define S3C2410_EXTINT1 S3C2410_GPIOREG(0x8C) 734#define S3C2410_EXTINT2 S3C2410_GPIOREG(0x90) 735 736#define S3C24XX_EXTINT0 S3C24XX_GPIOREG2(0x88) 737#define S3C24XX_EXTINT1 S3C24XX_GPIOREG2(0x8C) 738#define S3C24XX_EXTINT2 S3C24XX_GPIOREG2(0x90) 739 740/* interrupt filtering conrrol for EINT16..EINT23 */ 741#define S3C2410_EINFLT0 S3C2410_GPIOREG(0x94) 742#define S3C2410_EINFLT1 S3C2410_GPIOREG(0x98) 743#define S3C2410_EINFLT2 S3C2410_GPIOREG(0x9C) 744#define S3C2410_EINFLT3 S3C2410_GPIOREG(0xA0) 745 746#define S3C24XX_EINFLT0 S3C24XX_GPIOREG2(0x94) 747#define S3C24XX_EINFLT1 S3C24XX_GPIOREG2(0x98) 748#define S3C24XX_EINFLT2 S3C24XX_GPIOREG2(0x9C) 749#define S3C24XX_EINFLT3 S3C24XX_GPIOREG2(0xA0) 750 751/* values for interrupt filtering */ 752#define S3C2410_EINTFLT_PCLK (0x00) 753#define S3C2410_EINTFLT_EXTCLK (1<<7) 754#define S3C2410_EINTFLT_WIDTHMSK(x) ((x) & 0x3f) 755 756/* removed EINTxxxx defs from here, not meant for this */ 757 758/* GSTATUS have miscellaneous information in them 759 * 760 * These move between s3c2410 and s3c2412 style systems. 761 */ 762 763#define S3C2410_GSTATUS0 S3C2410_GPIOREG(0x0AC) 764#define S3C2410_GSTATUS1 S3C2410_GPIOREG(0x0B0) 765#define S3C2410_GSTATUS2 S3C2410_GPIOREG(0x0B4) 766#define S3C2410_GSTATUS3 S3C2410_GPIOREG(0x0B8) 767#define S3C2410_GSTATUS4 S3C2410_GPIOREG(0x0BC) 768 769#define S3C2412_GSTATUS0 S3C2410_GPIOREG(0x0BC) 770#define S3C2412_GSTATUS1 S3C2410_GPIOREG(0x0C0) 771#define S3C2412_GSTATUS2 S3C2410_GPIOREG(0x0C4) 772#define S3C2412_GSTATUS3 S3C2410_GPIOREG(0x0C8) 773#define S3C2412_GSTATUS4 S3C2410_GPIOREG(0x0CC) 774 775#define S3C24XX_GSTATUS0 S3C24XX_GPIOREG2(0x0AC) 776#define S3C24XX_GSTATUS1 S3C24XX_GPIOREG2(0x0B0) 777#define S3C24XX_GSTATUS2 S3C24XX_GPIOREG2(0x0B4) 778#define S3C24XX_GSTATUS3 S3C24XX_GPIOREG2(0x0B8) 779#define S3C24XX_GSTATUS4 S3C24XX_GPIOREG2(0x0BC) 780 781#define S3C2410_GSTATUS0_nWAIT (1<<3) 782#define S3C2410_GSTATUS0_NCON (1<<2) 783#define S3C2410_GSTATUS0_RnB (1<<1) 784#define S3C2410_GSTATUS0_nBATTFLT (1<<0) 785 786#define S3C2410_GSTATUS1_IDMASK (0xffff0000) 787#define S3C2410_GSTATUS1_2410 (0x32410000) 788#define S3C2410_GSTATUS1_2412 (0x32412001) 789#define S3C2410_GSTATUS1_2416 (0x32416003) 790#define S3C2410_GSTATUS1_2440 (0x32440000) 791#define S3C2410_GSTATUS1_2442 (0x32440aaa) 792/* some 2416 CPUs report this value also */ 793#define S3C2410_GSTATUS1_2450 (0x32450003) 794 795#define S3C2410_GSTATUS2_WTRESET (1<<2) 796#define S3C2410_GSTATUS2_OFFRESET (1<<1) 797#define S3C2410_GSTATUS2_PONRESET (1<<0) 798 799/* open drain control register */ 800#define S3C2400_OPENCR S3C2410_GPIOREG(0x50) 801 802#define S3C2400_OPENCR_OPC_RXD1DIS (0<<0) 803#define S3C2400_OPENCR_OPC_RXD1EN (1<<0) 804#define S3C2400_OPENCR_OPC_TXD1DIS (0<<1) 805#define S3C2400_OPENCR_OPC_TXD1EN (1<<1) 806#define S3C2400_OPENCR_OPC_CMDDIS (0<<2) 807#define S3C2400_OPENCR_OPC_CMDEN (1<<2) 808#define S3C2400_OPENCR_OPC_DATDIS (0<<3) 809#define S3C2400_OPENCR_OPC_DATEN (1<<3) 810#define S3C2400_OPENCR_OPC_MISODIS (0<<4) 811#define S3C2400_OPENCR_OPC_MISOEN (1<<4) 812#define S3C2400_OPENCR_OPC_MOSIDIS (0<<5) 813#define S3C2400_OPENCR_OPC_MOSIEN (1<<5) 814 815/* 2412/2413 sleep configuration registers */ 816 817#define S3C2412_GPBSLPCON S3C2410_GPIOREG(0x1C) 818#define S3C2412_GPCSLPCON S3C2410_GPIOREG(0x2C) 819#define S3C2412_GPDSLPCON S3C2410_GPIOREG(0x3C) 820#define S3C2412_GPFSLPCON S3C2410_GPIOREG(0x5C) 821#define S3C2412_GPGSLPCON S3C2410_GPIOREG(0x6C) 822#define S3C2412_GPHSLPCON S3C2410_GPIOREG(0x7C) 823 824/* definitions for each pin bit */ 825#define S3C2412_GPIO_SLPCON_LOW ( 0x00 ) 826#define S3C2412_GPIO_SLPCON_HIGH ( 0x01 ) 827#define S3C2412_GPIO_SLPCON_IN ( 0x02 ) 828#define S3C2412_GPIO_SLPCON_PULL ( 0x03 ) 829 830#define S3C2412_SLPCON_LOW(x) ( 0x00 << ((x) * 2)) 831#define S3C2412_SLPCON_HIGH(x) ( 0x01 << ((x) * 2)) 832#define S3C2412_SLPCON_IN(x) ( 0x02 << ((x) * 2)) 833#define S3C2412_SLPCON_PULL(x) ( 0x03 << ((x) * 2)) 834#define S3C2412_SLPCON_EINT(x) ( 0x02 << ((x) * 2)) /* only IRQ pins */ 835#define S3C2412_SLPCON_MASK(x) ( 0x03 << ((x) * 2)) 836 837#define S3C2412_SLPCON_ALL_LOW (0x0) 838#define S3C2412_SLPCON_ALL_HIGH (0x11111111 | 0x44444444) 839#define S3C2412_SLPCON_ALL_IN (0x22222222 | 0x88888888) 840#define S3C2412_SLPCON_ALL_PULL (0x33333333) 841 842#endif /* __ASM_ARCH_REGS_GPIO_H */ 843