1/* arch/arm/mach-s3c2410/include/mach/bast-cpld.h 2 * 3 * Copyright (c) 2003-2004 Simtec Electronics 4 * Ben Dooks <ben@simtec.co.uk> 5 * 6 * BAST - CPLD control constants 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11*/ 12 13#ifndef __ASM_ARCH_BASTCPLD_H 14#define __ASM_ARCH_BASTCPLD_H 15 16/* CTRL1 - Audio LR routing */ 17 18#define BAST_CPLD_CTRL1_LRCOFF (0x00) 19#define BAST_CPLD_CTRL1_LRCADC (0x01) 20#define BAST_CPLD_CTRL1_LRCDAC (0x02) 21#define BAST_CPLD_CTRL1_LRCARM (0x03) 22#define BAST_CPLD_CTRL1_LRMASK (0x03) 23 24/* CTRL2 - NAND WP control, IDE Reset assert/check */ 25 26#define BAST_CPLD_CTRL2_WNAND (0x04) 27#define BAST_CPLD_CTLR2_IDERST (0x08) 28 29/* CTRL3 - rom write control, CPLD identity */ 30 31#define BAST_CPLD_CTRL3_IDMASK (0x0e) 32#define BAST_CPLD_CTRL3_ROMWEN (0x01) 33 34/* CTRL4 - 8bit LCD interface control/status */ 35 36#define BAST_CPLD_CTRL4_LLAT (0x01) 37#define BAST_CPLD_CTRL4_LCDRW (0x02) 38#define BAST_CPLD_CTRL4_LCDCMD (0x04) 39#define BAST_CPLD_CTRL4_LCDE2 (0x01) 40 41/* CTRL5 - DMA routing */ 42 43#define BAST_CPLD_DMA0_PRIIDE (0<<0) 44#define BAST_CPLD_DMA0_SECIDE (1<<0) 45#define BAST_CPLD_DMA0_ISA15 (2<<0) 46#define BAST_CPLD_DMA0_ISA36 (3<<0) 47 48#define BAST_CPLD_DMA1_PRIIDE (0<<2) 49#define BAST_CPLD_DMA1_SECIDE (1<<2) 50#define BAST_CPLD_DMA1_ISA15 (2<<2) 51#define BAST_CPLD_DMA1_ISA36 (3<<2) 52 53#endif /* __ASM_ARCH_BASTCPLD_H */ 54