1/* 2 * linux/arch/arm/mach-pxa/cm-x255.c 3 * 4 * Copyright (C) 2007, 2008 CompuLab, Ltd. 5 * Mike Rapoport <mike@compulab.co.il> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 */ 11 12#include <linux/platform_device.h> 13#include <linux/irq.h> 14#include <linux/gpio.h> 15#include <linux/mtd/partitions.h> 16#include <linux/mtd/physmap.h> 17#include <linux/mtd/nand-gpio.h> 18 19#include <linux/spi/spi.h> 20 21#include <asm/mach/arch.h> 22#include <asm/mach-types.h> 23#include <asm/mach/map.h> 24 25#include <mach/pxa25x.h> 26#include <mach/pxa2xx_spi.h> 27 28#include "generic.h" 29 30#define GPIO_NAND_CS (5) 31#define GPIO_NAND_ALE (4) 32#define GPIO_NAND_CLE (3) 33#define GPIO_NAND_RB (10) 34 35static unsigned long cmx255_pin_config[] = { 36 /* AC'97 */ 37 GPIO28_AC97_BITCLK, 38 GPIO29_AC97_SDATA_IN_0, 39 GPIO30_AC97_SDATA_OUT, 40 GPIO31_AC97_SYNC, 41 42 /* BTUART */ 43 GPIO42_BTUART_RXD, 44 GPIO43_BTUART_TXD, 45 GPIO44_BTUART_CTS, 46 GPIO45_BTUART_RTS, 47 48 /* STUART */ 49 GPIO46_STUART_RXD, 50 GPIO47_STUART_TXD, 51 52 /* LCD */ 53 GPIOxx_LCD_TFT_16BPP, 54 55 /* SSP1 */ 56 GPIO23_SSP1_SCLK, 57 GPIO24_SSP1_SFRM, 58 GPIO25_SSP1_TXD, 59 GPIO26_SSP1_RXD, 60 61 /* SSP2 */ 62 GPIO81_SSP2_CLK_OUT, 63 GPIO82_SSP2_FRM_OUT, 64 GPIO83_SSP2_TXD, 65 GPIO84_SSP2_RXD, 66 67 /* PC Card */ 68 GPIO48_nPOE, 69 GPIO49_nPWE, 70 GPIO50_nPIOR, 71 GPIO51_nPIOW, 72 GPIO52_nPCE_1, 73 GPIO53_nPCE_2, 74 GPIO54_nPSKTSEL, 75 GPIO55_nPREG, 76 GPIO56_nPWAIT, 77 GPIO57_nIOIS16, 78 79 /* SDRAM and local bus */ 80 GPIO15_nCS_1, 81 GPIO78_nCS_2, 82 GPIO79_nCS_3, 83 GPIO80_nCS_4, 84 GPIO33_nCS_5, 85 GPIO18_RDY, 86 87 /* GPIO */ 88 GPIO0_GPIO | WAKEUP_ON_EDGE_BOTH, 89 GPIO9_GPIO, /* PC card reset */ 90 91 /* NAND controls */ 92 GPIO5_GPIO | MFP_LPM_DRIVE_HIGH, /* NAND CE# */ 93 GPIO4_GPIO | MFP_LPM_DRIVE_LOW, /* NAND ALE */ 94 GPIO3_GPIO | MFP_LPM_DRIVE_LOW, /* NAND CLE */ 95 GPIO10_GPIO, /* NAND Ready/Busy */ 96 97 /* interrupts */ 98 GPIO22_GPIO, /* DM9000 interrupt */ 99}; 100 101#if defined(CONFIG_SPI_PXA2XX) 102static struct pxa2xx_spi_master pxa_ssp_master_info = { 103 .num_chipselect = 1, 104}; 105 106static struct spi_board_info spi_board_info[] __initdata = { 107 [0] = { 108 .modalias = "rtc-max6902", 109 .max_speed_hz = 1000000, 110 .bus_num = 1, 111 .chip_select = 0, 112 }, 113}; 114 115static void __init cmx255_init_rtc(void) 116{ 117 pxa2xx_set_spi_info(1, &pxa_ssp_master_info); 118 spi_register_board_info(ARRAY_AND_SIZE(spi_board_info)); 119} 120#else 121static inline void cmx255_init_rtc(void) {} 122#endif 123 124#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE) 125static struct mtd_partition cmx255_nor_partitions[] = { 126 { 127 .name = "ARMmon", 128 .size = 0x00030000, 129 .offset = 0, 130 .mask_flags = MTD_WRITEABLE /* force read-only */ 131 } , { 132 .name = "ARMmon setup block", 133 .size = 0x00010000, 134 .offset = MTDPART_OFS_APPEND, 135 .mask_flags = MTD_WRITEABLE /* force read-only */ 136 } , { 137 .name = "kernel", 138 .size = 0x00160000, 139 .offset = MTDPART_OFS_APPEND, 140 } , { 141 .name = "ramdisk", 142 .size = MTDPART_SIZ_FULL, 143 .offset = MTDPART_OFS_APPEND 144 } 145}; 146 147static struct physmap_flash_data cmx255_nor_flash_data[] = { 148 { 149 .width = 2, /* bankwidth in bytes */ 150 .parts = cmx255_nor_partitions, 151 .nr_parts = ARRAY_SIZE(cmx255_nor_partitions) 152 } 153}; 154 155static struct resource cmx255_nor_resource = { 156 .start = PXA_CS0_PHYS, 157 .end = PXA_CS0_PHYS + SZ_8M - 1, 158 .flags = IORESOURCE_MEM, 159}; 160 161static struct platform_device cmx255_nor = { 162 .name = "physmap-flash", 163 .id = -1, 164 .dev = { 165 .platform_data = cmx255_nor_flash_data, 166 }, 167 .resource = &cmx255_nor_resource, 168 .num_resources = 1, 169}; 170 171static void __init cmx255_init_nor(void) 172{ 173 platform_device_register(&cmx255_nor); 174} 175#else 176static inline void cmx255_init_nor(void) {} 177#endif 178 179#if defined(CONFIG_MTD_NAND_GPIO) || defined(CONFIG_MTD_NAND_GPIO_MODULE) 180static struct resource cmx255_nand_resource[] = { 181 [0] = { 182 .start = PXA_CS1_PHYS, 183 .end = PXA_CS1_PHYS + 11, 184 .flags = IORESOURCE_MEM, 185 }, 186 [1] = { 187 .start = PXA_CS5_PHYS, 188 .end = PXA_CS5_PHYS + 3, 189 .flags = IORESOURCE_MEM, 190 }, 191}; 192 193static struct mtd_partition cmx255_nand_parts[] = { 194 [0] = { 195 .name = "cmx255-nand", 196 .size = MTDPART_SIZ_FULL, 197 .offset = 0, 198 }, 199}; 200 201static struct gpio_nand_platdata cmx255_nand_platdata = { 202 .gpio_nce = GPIO_NAND_CS, 203 .gpio_cle = GPIO_NAND_CLE, 204 .gpio_ale = GPIO_NAND_ALE, 205 .gpio_rdy = GPIO_NAND_RB, 206 .gpio_nwp = -1, 207 .parts = cmx255_nand_parts, 208 .num_parts = ARRAY_SIZE(cmx255_nand_parts), 209 .chip_delay = 25, 210}; 211 212static struct platform_device cmx255_nand = { 213 .name = "gpio-nand", 214 .num_resources = ARRAY_SIZE(cmx255_nand_resource), 215 .resource = cmx255_nand_resource, 216 .id = -1, 217 .dev = { 218 .platform_data = &cmx255_nand_platdata, 219 } 220}; 221 222static void __init cmx255_init_nand(void) 223{ 224 platform_device_register(&cmx255_nand); 225} 226#else 227static inline void cmx255_init_nand(void) {} 228#endif 229 230void __init cmx255_init(void) 231{ 232 pxa2xx_mfp_config(ARRAY_AND_SIZE(cmx255_pin_config)); 233 234 cmx255_init_rtc(); 235 cmx255_init_nor(); 236 cmx255_init_nand(); 237} 238