1/* 2 * arch/arm/mach-pnx4008/include/mach/gpio.h 3 * 4 * PNX4008 GPIO driver - header file 5 * 6 * Author: Dmitry Chigirev <source@mvista.com> 7 * 8 * Based on reference code by Iwo Mergler and Z.Tabaaloute from Philips: 9 * Copyright (c) 2005 Koninklijke Philips Electronics N.V. 10 * 11 * 2005 (c) MontaVista Software, Inc. This file is licensed under 12 * the terms of the GNU General Public License version 2. This program 13 * is licensed "as is" without any warranty of any kind, whether express 14 * or implied. 15 */ 16 17#ifndef _PNX4008_GPIO_H_ 18#define _PNX4008_GPIO_H_ 19 20 21/* Block numbers */ 22#define GPIO_IN (0) 23#define GPIO_OUT (0x100) 24#define GPIO_BID (0x200) 25#define GPIO_RAM (0x300) 26#define GPIO_MUX (0x400) 27 28#define GPIO_TYPE_MASK(K) ((K) & 0x700) 29 30/* INPUT GPIOs */ 31/* GPI */ 32#define GPI_00 (GPIO_IN | 0) 33#define GPI_01 (GPIO_IN | 1) 34#define GPI_02 (GPIO_IN | 2) 35#define GPI_03 (GPIO_IN | 3) 36#define GPI_04 (GPIO_IN | 4) 37#define GPI_05 (GPIO_IN | 5) 38#define GPI_06 (GPIO_IN | 6) 39#define GPI_07 (GPIO_IN | 7) 40#define GPI_08 (GPIO_IN | 8) 41#define GPI_09 (GPIO_IN | 9) 42#define U1_RX (GPIO_IN | 15) 43#define U2_HTCS (GPIO_IN | 16) 44#define U2_RX (GPIO_IN | 17) 45#define U3_RX (GPIO_IN | 18) 46#define U4_RX (GPIO_IN | 19) 47#define U5_RX (GPIO_IN | 20) 48#define U6_IRRX (GPIO_IN | 21) 49#define U7_HCTS (GPIO_IN | 22) 50#define U7_RX (GPIO_IN | 23) 51/* MISC IN */ 52#define SPI1_DATIN (GPIO_IN | 25) 53#define DISP_SYNC (GPIO_IN | 26) 54#define SPI2_DATIN (GPIO_IN | 27) 55#define GPI_11 (GPIO_IN | 28) 56 57#define GPIO_IN_MASK 0x1eff83ff 58 59/* OUTPUT GPIOs */ 60/* GPO */ 61#define GPO_00 (GPIO_OUT | 0) 62#define GPO_01 (GPIO_OUT | 1) 63#define GPO_02 (GPIO_OUT | 2) 64#define GPO_03 (GPIO_OUT | 3) 65#define GPO_04 (GPIO_OUT | 4) 66#define GPO_05 (GPIO_OUT | 5) 67#define GPO_06 (GPIO_OUT | 6) 68#define GPO_07 (GPIO_OUT | 7) 69#define GPO_08 (GPIO_OUT | 8) 70#define GPO_09 (GPIO_OUT | 9) 71#define GPO_10 (GPIO_OUT | 10) 72#define GPO_11 (GPIO_OUT | 11) 73#define GPO_12 (GPIO_OUT | 12) 74#define GPO_13 (GPIO_OUT | 13) 75#define GPO_14 (GPIO_OUT | 14) 76#define GPO_15 (GPIO_OUT | 15) 77#define GPO_16 (GPIO_OUT | 16) 78#define GPO_17 (GPIO_OUT | 17) 79#define GPO_18 (GPIO_OUT | 18) 80#define GPO_19 (GPIO_OUT | 19) 81#define GPO_20 (GPIO_OUT | 20) 82#define GPO_21 (GPIO_OUT | 21) 83#define GPO_22 (GPIO_OUT | 22) 84#define GPO_23 (GPIO_OUT | 23) 85 86#define GPIO_OUT_MASK 0xffffff 87 88/* BIDIRECTIONAL GPIOs */ 89/* RAM pins */ 90#define RAM_D19 (GPIO_RAM | 0) 91#define RAM_D20 (GPIO_RAM | 1) 92#define RAM_D21 (GPIO_RAM | 2) 93#define RAM_D22 (GPIO_RAM | 3) 94#define RAM_D23 (GPIO_RAM | 4) 95#define RAM_D24 (GPIO_RAM | 5) 96#define RAM_D25 (GPIO_RAM | 6) 97#define RAM_D26 (GPIO_RAM | 7) 98#define RAM_D27 (GPIO_RAM | 8) 99#define RAM_D28 (GPIO_RAM | 9) 100#define RAM_D29 (GPIO_RAM | 10) 101#define RAM_D30 (GPIO_RAM | 11) 102#define RAM_D31 (GPIO_RAM | 12) 103 104#define GPIO_RAM_MASK 0x1fff 105 106/* I/O pins */ 107#define GPIO_00 (GPIO_BID | 25) 108#define GPIO_01 (GPIO_BID | 26) 109#define GPIO_02 (GPIO_BID | 27) 110#define GPIO_03 (GPIO_BID | 28) 111#define GPIO_04 (GPIO_BID | 29) 112#define GPIO_05 (GPIO_BID | 30) 113 114#define GPIO_BID_MASK 0x7e000000 115 116/* Non-GPIO multiplexed PIOs. For multiplexing with GPIO, please use GPIO macros */ 117#define GPIO_SDRAM_SEL (GPIO_MUX | 3) 118 119#define GPIO_MUX_MASK 0x8 120 121/* Extraction/assembly macros */ 122#define GPIO_BIT_MASK(K) ((K) & 0x1F) 123#define GPIO_BIT(K) (1 << GPIO_BIT_MASK(K)) 124#define GPIO_ISMUX(K) ((GPIO_TYPE_MASK(K) == GPIO_MUX) && (GPIO_BIT(K) & GPIO_MUX_MASK)) 125#define GPIO_ISRAM(K) ((GPIO_TYPE_MASK(K) == GPIO_RAM) && (GPIO_BIT(K) & GPIO_RAM_MASK)) 126#define GPIO_ISBID(K) ((GPIO_TYPE_MASK(K) == GPIO_BID) && (GPIO_BIT(K) & GPIO_BID_MASK)) 127#define GPIO_ISOUT(K) ((GPIO_TYPE_MASK(K) == GPIO_OUT) && (GPIO_BIT(K) & GPIO_OUT_MASK)) 128#define GPIO_ISIN(K) ((GPIO_TYPE_MASK(K) == GPIO_IN) && (GPIO_BIT(K) & GPIO_IN_MASK)) 129 130/* Start Enable Pin Interrupts - table 58 page 66 */ 131 132#define SE_PIN_BASE_INT 32 133 134#define SE_U7_RX_INT 63 135#define SE_U7_HCTS_INT 62 136#define SE_BT_CLKREQ_INT 61 137#define SE_U6_IRRX_INT 60 138/*59 unused*/ 139#define SE_U5_RX_INT 58 140#define SE_GPI_11_INT 57 141#define SE_U3_RX_INT 56 142#define SE_U2_HCTS_INT 55 143#define SE_U2_RX_INT 54 144#define SE_U1_RX_INT 53 145#define SE_DISP_SYNC_INT 52 146/*51 unused*/ 147#define SE_SDIO_INT_N 50 148#define SE_MSDIO_START_INT 49 149#define SE_GPI_06_INT 48 150#define SE_GPI_05_INT 47 151#define SE_GPI_04_INT 46 152#define SE_GPI_03_INT 45 153#define SE_GPI_02_INT 44 154#define SE_GPI_01_INT 43 155#define SE_GPI_00_INT 42 156#define SE_SYSCLKEN_PIN_INT 41 157#define SE_SPI1_DATAIN_INT 40 158#define SE_GPI_07_INT 39 159#define SE_SPI2_DATAIN_INT 38 160#define SE_GPI_10_INT 37 161#define SE_GPI_09_INT 36 162#define SE_GPI_08_INT 35 163/*34-32 unused*/ 164 165/* Start Enable Internal Interrupts - table 57 page 65 */ 166 167#define SE_INT_BASE_INT 0 168 169#define SE_TS_IRQ 31 170#define SE_TS_P_INT 30 171#define SE_TS_AUX_INT 29 172/*27-28 unused*/ 173#define SE_USB_AHB_NEED_CLK_INT 26 174#define SE_MSTIMER_INT 25 175#define SE_RTC_INT 24 176#define SE_USB_NEED_CLK_INT 23 177#define SE_USB_INT 22 178#define SE_USB_I2C_INT 21 179#define SE_USB_OTG_TIMER_INT 20 180#define SE_USB_OTG_ATX_INT_N 19 181/*18 unused*/ 182#define SE_DSP_GPIO4_INT 17 183#define SE_KEY_IRQ 16 184#define SE_DSP_SLAVEPORT_INT 15 185#define SE_DSP_GPIO1_INT 14 186#define SE_DSP_GPIO0_INT 13 187#define SE_DSP_AHB_INT 12 188/*11-6 unused*/ 189#define SE_GPIO_05_INT 5 190#define SE_GPIO_04_INT 4 191#define SE_GPIO_03_INT 3 192#define SE_GPIO_02_INT 2 193#define SE_GPIO_01_INT 1 194#define SE_GPIO_00_INT 0 195 196#define START_INT_REG_BIT(irq) (1<<((irq)&0x1F)) 197 198#define START_INT_ER_REG(irq) IO_ADDRESS((PNX4008_PWRMAN_BASE + 0x20 + (((irq)&(0x1<<5))>>1))) 199#define START_INT_RSR_REG(irq) IO_ADDRESS((PNX4008_PWRMAN_BASE + 0x24 + (((irq)&(0x1<<5))>>1))) 200#define START_INT_SR_REG(irq) IO_ADDRESS((PNX4008_PWRMAN_BASE + 0x28 + (((irq)&(0x1<<5))>>1))) 201#define START_INT_APR_REG(irq) IO_ADDRESS((PNX4008_PWRMAN_BASE + 0x2C + (((irq)&(0x1<<5))>>1))) 202 203extern int pnx4008_gpio_register_pin(unsigned short pin); 204extern int pnx4008_gpio_unregister_pin(unsigned short pin); 205extern unsigned long pnx4008_gpio_read_pin(unsigned short pin); 206extern int pnx4008_gpio_write_pin(unsigned short pin, int output); 207extern int pnx4008_gpio_set_pin_direction(unsigned short pin, int output); 208extern int pnx4008_gpio_read_pin_direction(unsigned short pin); 209extern int pnx4008_gpio_set_pin_mux(unsigned short pin, int output); 210extern int pnx4008_gpio_read_pin_mux(unsigned short pin); 211 212static inline void start_int_umask(u8 irq) 213{ 214 __raw_writel(__raw_readl(START_INT_ER_REG(irq)) | 215 START_INT_REG_BIT(irq), START_INT_ER_REG(irq)); 216} 217 218static inline void start_int_mask(u8 irq) 219{ 220 __raw_writel(__raw_readl(START_INT_ER_REG(irq)) & 221 ~START_INT_REG_BIT(irq), START_INT_ER_REG(irq)); 222} 223 224static inline void start_int_ack(u8 irq) 225{ 226 __raw_writel(START_INT_REG_BIT(irq), START_INT_RSR_REG(irq)); 227} 228 229static inline void start_int_set_falling_edge(u8 irq) 230{ 231 __raw_writel(__raw_readl(START_INT_APR_REG(irq)) & 232 ~START_INT_REG_BIT(irq), START_INT_APR_REG(irq)); 233} 234 235static inline void start_int_set_rising_edge(u8 irq) 236{ 237 __raw_writel(__raw_readl(START_INT_APR_REG(irq)) | 238 START_INT_REG_BIT(irq), START_INT_APR_REG(irq)); 239} 240 241#endif /* _PNX4008_GPIO_H_ */ 242