1 2 3#include "opp2xxx.h" 4#include "sdrc.h" 5#include "clock.h" 6 7/* 8 * Key dividers which make up a PRCM set. Ratios for a PRCM are mandated. 9 * xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU, 10 * CM_CLKSEL_DSP, CM_CLKSEL_GFX, CM_CLKSEL1_CORE, CM_CLKSEL1_PLL, 11 * CM_CLKSEL2_PLL, CM_CLKSEL_MDM 12 * 13 * Filling in table based on 2430-SDPs variants available. There are 14 * quite a few more rate combinations which could be defined. 15 * 16 * When multiple values are defined the start up will try and choose 17 * the fastest one. If a 'fast' value is defined, then automatically, 18 * the /2 one should be included as it can be used. Generally having 19 * more than one fast set does not make sense, as static timings need 20 * to be changed to change the set. The exception is the bypass 21 * setting which is available for low power bypass. 22 * 23 * Note: This table needs to be sorted, fastest to slowest. 24 */ 25const struct prcm_config omap2430_rate_table[] = { 26 /* PRCM #4 - ratio2 (ES2.1) - FAST */ 27 {S13M, S798M, S399M, R2_CM_CLKSEL_MPU_VAL, /* 399MHz ARM */ 28 R2_CM_CLKSEL_DSP_VAL, R2_CM_CLKSEL_GFX_VAL, 29 R2_CM_CLKSEL1_CORE_VAL, M4_CM_CLKSEL1_PLL_13_VAL, 30 MX_CLKSEL2_PLL_2x_VAL, R2_CM_CLKSEL_MDM_VAL, 31 SDRC_RFR_CTRL_133MHz, 32 RATE_IN_243X}, 33 34 /* PRCM #2 - ratio1 (ES2) - FAST */ 35 {S13M, S658M, S329M, R1_CM_CLKSEL_MPU_VAL, /* 330MHz ARM */ 36 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL, 37 R1_CM_CLKSEL1_CORE_VAL, M2_CM_CLKSEL1_PLL_13_VAL, 38 MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL, 39 SDRC_RFR_CTRL_165MHz, 40 RATE_IN_243X}, 41 42 /* PRCM #5a - ratio1 - FAST */ 43 {S13M, S532M, S266M, R1_CM_CLKSEL_MPU_VAL, /* 266MHz ARM */ 44 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL, 45 R1_CM_CLKSEL1_CORE_VAL, M5A_CM_CLKSEL1_PLL_13_VAL, 46 MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL, 47 SDRC_RFR_CTRL_133MHz, 48 RATE_IN_243X}, 49 50 /* PRCM #5b - ratio1 - FAST */ 51 {S13M, S400M, S200M, R1_CM_CLKSEL_MPU_VAL, /* 200MHz ARM */ 52 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL, 53 R1_CM_CLKSEL1_CORE_VAL, M5B_CM_CLKSEL1_PLL_13_VAL, 54 MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL, 55 SDRC_RFR_CTRL_100MHz, 56 RATE_IN_243X}, 57 58 /* PRCM #4 - ratio1 (ES2.1) - SLOW */ 59 {S13M, S399M, S199M, R2_CM_CLKSEL_MPU_VAL, /* 200MHz ARM */ 60 R2_CM_CLKSEL_DSP_VAL, R2_CM_CLKSEL_GFX_VAL, 61 R2_CM_CLKSEL1_CORE_VAL, M4_CM_CLKSEL1_PLL_13_VAL, 62 MX_CLKSEL2_PLL_1x_VAL, R2_CM_CLKSEL_MDM_VAL, 63 SDRC_RFR_CTRL_133MHz, 64 RATE_IN_243X}, 65 66 /* PRCM #2 - ratio1 (ES2) - SLOW */ 67 {S13M, S329M, S164M, R1_CM_CLKSEL_MPU_VAL, /* 165MHz ARM */ 68 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL, 69 R1_CM_CLKSEL1_CORE_VAL, M2_CM_CLKSEL1_PLL_13_VAL, 70 MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL, 71 SDRC_RFR_CTRL_165MHz, 72 RATE_IN_243X}, 73 74 /* PRCM #5a - ratio1 - SLOW */ 75 {S13M, S266M, S133M, R1_CM_CLKSEL_MPU_VAL, /* 133MHz ARM */ 76 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL, 77 R1_CM_CLKSEL1_CORE_VAL, M5A_CM_CLKSEL1_PLL_13_VAL, 78 MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL, 79 SDRC_RFR_CTRL_133MHz, 80 RATE_IN_243X}, 81 82 /* PRCM #5b - ratio1 - SLOW*/ 83 {S13M, S200M, S100M, R1_CM_CLKSEL_MPU_VAL, /* 100MHz ARM */ 84 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL, 85 R1_CM_CLKSEL1_CORE_VAL, M5B_CM_CLKSEL1_PLL_13_VAL, 86 MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL, 87 SDRC_RFR_CTRL_100MHz, 88 RATE_IN_243X}, 89 90 /* PRCM-boot/bypass */ 91 {S13M, S13M, S13M, RB_CM_CLKSEL_MPU_VAL, /* 13Mhz */ 92 RB_CM_CLKSEL_DSP_VAL, RB_CM_CLKSEL_GFX_VAL, 93 RB_CM_CLKSEL1_CORE_VAL, MB_CM_CLKSEL1_PLL_13_VAL, 94 MX_CLKSEL2_PLL_2x_VAL, RB_CM_CLKSEL_MDM_VAL, 95 SDRC_RFR_CTRL_BYPASS, 96 RATE_IN_243X}, 97 98 /* PRCM-boot/bypass */ 99 {S12M, S12M, S12M, RB_CM_CLKSEL_MPU_VAL, /* 12Mhz */ 100 RB_CM_CLKSEL_DSP_VAL, RB_CM_CLKSEL_GFX_VAL, 101 RB_CM_CLKSEL1_CORE_VAL, MB_CM_CLKSEL1_PLL_12_VAL, 102 MX_CLKSEL2_PLL_2x_VAL, RB_CM_CLKSEL_MDM_VAL, 103 SDRC_RFR_CTRL_BYPASS, 104 RATE_IN_243X}, 105 106 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 107}; 108