1 2 3#include "opp2xxx.h" 4#include "sdrc.h" 5#include "clock.h" 6 7/* 8 * Key dividers which make up a PRCM set. Ratios for a PRCM are mandated. 9 * xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU, 10 * CM_CLKSEL_DSP, CM_CLKSEL_GFX, CM_CLKSEL1_CORE, CM_CLKSEL1_PLL, 11 * CM_CLKSEL2_PLL, CM_CLKSEL_MDM 12 * 13 * Filling in table based on H4 boards available. There are quite a 14 * few more rate combinations which could be defined. 15 * 16 * When multiple values are defined the start up will try and choose 17 * the fastest one. If a 'fast' value is defined, then automatically, 18 * the /2 one should be included as it can be used. Generally having 19 * more than one fast set does not make sense, as static timings need 20 * to be changed to change the set. The exception is the bypass 21 * setting which is available for low power bypass. 22 * 23 * Note: This table needs to be sorted, fastest to slowest. 24 **/ 25const struct prcm_config omap2420_rate_table[] = { 26 /* PRCM I - FAST */ 27 {S12M, S660M, S330M, RI_CM_CLKSEL_MPU_VAL, /* 330MHz ARM */ 28 RI_CM_CLKSEL_DSP_VAL, RI_CM_CLKSEL_GFX_VAL, 29 RI_CM_CLKSEL1_CORE_VAL, MI_CM_CLKSEL1_PLL_12_VAL, 30 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_165MHz, 31 RATE_IN_242X}, 32 33 /* PRCM II - FAST */ 34 {S12M, S600M, S300M, RII_CM_CLKSEL_MPU_VAL, /* 300MHz ARM */ 35 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL, 36 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_12_VAL, 37 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz, 38 RATE_IN_242X}, 39 40 {S13M, S600M, S300M, RII_CM_CLKSEL_MPU_VAL, /* 300MHz ARM */ 41 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL, 42 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_13_VAL, 43 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz, 44 RATE_IN_242X}, 45 46 /* PRCM III - FAST */ 47 {S12M, S532M, S266M, RIII_CM_CLKSEL_MPU_VAL, /* 266MHz ARM */ 48 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL, 49 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_12_VAL, 50 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz, 51 RATE_IN_242X}, 52 53 {S13M, S532M, S266M, RIII_CM_CLKSEL_MPU_VAL, /* 266MHz ARM */ 54 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL, 55 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_13_VAL, 56 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz, 57 RATE_IN_242X}, 58 59 /* PRCM II - SLOW */ 60 {S12M, S300M, S150M, RII_CM_CLKSEL_MPU_VAL, /* 150MHz ARM */ 61 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL, 62 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_12_VAL, 63 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz, 64 RATE_IN_242X}, 65 66 {S13M, S300M, S150M, RII_CM_CLKSEL_MPU_VAL, /* 150MHz ARM */ 67 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL, 68 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_13_VAL, 69 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz, 70 RATE_IN_242X}, 71 72 /* PRCM III - SLOW */ 73 {S12M, S266M, S133M, RIII_CM_CLKSEL_MPU_VAL, /* 133MHz ARM */ 74 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL, 75 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_12_VAL, 76 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz, 77 RATE_IN_242X}, 78 79 {S13M, S266M, S133M, RIII_CM_CLKSEL_MPU_VAL, /* 133MHz ARM */ 80 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL, 81 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_13_VAL, 82 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz, 83 RATE_IN_242X}, 84 85 /* PRCM-VII (boot-bypass) */ 86 {S12M, S12M, S12M, RVII_CM_CLKSEL_MPU_VAL, /* 12MHz ARM*/ 87 RVII_CM_CLKSEL_DSP_VAL, RVII_CM_CLKSEL_GFX_VAL, 88 RVII_CM_CLKSEL1_CORE_VAL, MVII_CM_CLKSEL1_PLL_12_VAL, 89 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_BYPASS, 90 RATE_IN_242X}, 91 92 /* PRCM-VII (boot-bypass) */ 93 {S13M, S13M, S13M, RVII_CM_CLKSEL_MPU_VAL, /* 13MHz ARM */ 94 RVII_CM_CLKSEL_DSP_VAL, RVII_CM_CLKSEL_GFX_VAL, 95 RVII_CM_CLKSEL1_CORE_VAL, MVII_CM_CLKSEL1_PLL_13_VAL, 96 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_BYPASS, 97 RATE_IN_242X}, 98 99 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 100}; 101