1/* 2 * omap iommu: omap2/3 architecture specific functions 3 * 4 * Copyright (C) 2008-2009 Nokia Corporation 5 * 6 * Written by Hiroshi DOYU <Hiroshi.DOYU@nokia.com>, 7 * Paul Mundt and Toshihiro Kobayashi 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License version 2 as 11 * published by the Free Software Foundation. 12 */ 13 14#include <linux/err.h> 15#include <linux/device.h> 16#include <linux/jiffies.h> 17#include <linux/module.h> 18#include <linux/slab.h> 19#include <linux/stringify.h> 20 21#include <plat/iommu.h> 22 23/* 24 * omap2 architecture specific register bit definitions 25 */ 26#define IOMMU_ARCH_VERSION 0x00000011 27 28/* SYSCONF */ 29#define MMU_SYS_IDLE_SHIFT 3 30#define MMU_SYS_IDLE_FORCE (0 << MMU_SYS_IDLE_SHIFT) 31#define MMU_SYS_IDLE_NONE (1 << MMU_SYS_IDLE_SHIFT) 32#define MMU_SYS_IDLE_SMART (2 << MMU_SYS_IDLE_SHIFT) 33#define MMU_SYS_IDLE_MASK (3 << MMU_SYS_IDLE_SHIFT) 34 35#define MMU_SYS_SOFTRESET (1 << 1) 36#define MMU_SYS_AUTOIDLE 1 37 38/* SYSSTATUS */ 39#define MMU_SYS_RESETDONE 1 40 41/* IRQSTATUS & IRQENABLE */ 42#define MMU_IRQ_MULTIHITFAULT (1 << 4) 43#define MMU_IRQ_TABLEWALKFAULT (1 << 3) 44#define MMU_IRQ_EMUMISS (1 << 2) 45#define MMU_IRQ_TRANSLATIONFAULT (1 << 1) 46#define MMU_IRQ_TLBMISS (1 << 0) 47 48#define __MMU_IRQ_FAULT \ 49 (MMU_IRQ_MULTIHITFAULT | MMU_IRQ_EMUMISS | MMU_IRQ_TRANSLATIONFAULT) 50#define MMU_IRQ_MASK \ 51 (__MMU_IRQ_FAULT | MMU_IRQ_TABLEWALKFAULT | MMU_IRQ_TLBMISS) 52#define MMU_IRQ_TWL_MASK (__MMU_IRQ_FAULT | MMU_IRQ_TABLEWALKFAULT) 53#define MMU_IRQ_TLB_MISS_MASK (__MMU_IRQ_FAULT | MMU_IRQ_TLBMISS) 54 55/* MMU_CNTL */ 56#define MMU_CNTL_SHIFT 1 57#define MMU_CNTL_MASK (7 << MMU_CNTL_SHIFT) 58#define MMU_CNTL_EML_TLB (1 << 3) 59#define MMU_CNTL_TWL_EN (1 << 2) 60#define MMU_CNTL_MMU_EN (1 << 1) 61 62#define get_cam_va_mask(pgsz) \ 63 (((pgsz) == MMU_CAM_PGSZ_16M) ? 0xff000000 : \ 64 ((pgsz) == MMU_CAM_PGSZ_1M) ? 0xfff00000 : \ 65 ((pgsz) == MMU_CAM_PGSZ_64K) ? 0xffff0000 : \ 66 ((pgsz) == MMU_CAM_PGSZ_4K) ? 0xfffff000 : 0) 67 68 69static void __iommu_set_twl(struct iommu *obj, bool on) 70{ 71 u32 l = iommu_read_reg(obj, MMU_CNTL); 72 73 if (on) 74 iommu_write_reg(obj, MMU_IRQ_TWL_MASK, MMU_IRQENABLE); 75 else 76 iommu_write_reg(obj, MMU_IRQ_TLB_MISS_MASK, MMU_IRQENABLE); 77 78 l &= ~MMU_CNTL_MASK; 79 if (on) 80 l |= (MMU_CNTL_MMU_EN | MMU_CNTL_TWL_EN); 81 else 82 l |= (MMU_CNTL_MMU_EN); 83 84 iommu_write_reg(obj, l, MMU_CNTL); 85} 86 87 88static int omap2_iommu_enable(struct iommu *obj) 89{ 90 u32 l, pa; 91 unsigned long timeout; 92 93 if (!obj->iopgd || !IS_ALIGNED((u32)obj->iopgd, SZ_16K)) 94 return -EINVAL; 95 96 pa = virt_to_phys(obj->iopgd); 97 if (!IS_ALIGNED(pa, SZ_16K)) 98 return -EINVAL; 99 100 iommu_write_reg(obj, MMU_SYS_SOFTRESET, MMU_SYSCONFIG); 101 102 timeout = jiffies + msecs_to_jiffies(20); 103 do { 104 l = iommu_read_reg(obj, MMU_SYSSTATUS); 105 if (l & MMU_SYS_RESETDONE) 106 break; 107 } while (!time_after(jiffies, timeout)); 108 109 if (!(l & MMU_SYS_RESETDONE)) { 110 dev_err(obj->dev, "can't take mmu out of reset\n"); 111 return -ENODEV; 112 } 113 114 l = iommu_read_reg(obj, MMU_REVISION); 115 dev_info(obj->dev, "%s: version %d.%d\n", obj->name, 116 (l >> 4) & 0xf, l & 0xf); 117 118 l = iommu_read_reg(obj, MMU_SYSCONFIG); 119 l &= ~MMU_SYS_IDLE_MASK; 120 l |= (MMU_SYS_IDLE_SMART | MMU_SYS_AUTOIDLE); 121 iommu_write_reg(obj, l, MMU_SYSCONFIG); 122 123 iommu_write_reg(obj, pa, MMU_TTB); 124 125 __iommu_set_twl(obj, true); 126 127 return 0; 128} 129 130static void omap2_iommu_disable(struct iommu *obj) 131{ 132 u32 l = iommu_read_reg(obj, MMU_CNTL); 133 134 l &= ~MMU_CNTL_MASK; 135 iommu_write_reg(obj, l, MMU_CNTL); 136 iommu_write_reg(obj, MMU_SYS_IDLE_FORCE, MMU_SYSCONFIG); 137 138 dev_dbg(obj->dev, "%s is shutting down\n", obj->name); 139} 140 141static void omap2_iommu_set_twl(struct iommu *obj, bool on) 142{ 143 __iommu_set_twl(obj, false); 144} 145 146static u32 omap2_iommu_fault_isr(struct iommu *obj, u32 *ra) 147{ 148 int i; 149 u32 stat, da; 150 const char *err_msg[] = { 151 "tlb miss", 152 "translation fault", 153 "emulation miss", 154 "table walk fault", 155 "multi hit fault", 156 }; 157 158 stat = iommu_read_reg(obj, MMU_IRQSTATUS); 159 stat &= MMU_IRQ_MASK; 160 if (!stat) 161 return 0; 162 163 da = iommu_read_reg(obj, MMU_FAULT_AD); 164 *ra = da; 165 166 dev_err(obj->dev, "%s:\tda:%08x ", __func__, da); 167 168 for (i = 0; i < ARRAY_SIZE(err_msg); i++) { 169 if (stat & (1 << i)) 170 printk("%s ", err_msg[i]); 171 } 172 printk("\n"); 173 174 iommu_write_reg(obj, stat, MMU_IRQSTATUS); 175 176 return stat; 177} 178 179static void omap2_tlb_read_cr(struct iommu *obj, struct cr_regs *cr) 180{ 181 cr->cam = iommu_read_reg(obj, MMU_READ_CAM); 182 cr->ram = iommu_read_reg(obj, MMU_READ_RAM); 183} 184 185static void omap2_tlb_load_cr(struct iommu *obj, struct cr_regs *cr) 186{ 187 iommu_write_reg(obj, cr->cam | MMU_CAM_V, MMU_CAM); 188 iommu_write_reg(obj, cr->ram, MMU_RAM); 189} 190 191static u32 omap2_cr_to_virt(struct cr_regs *cr) 192{ 193 u32 page_size = cr->cam & MMU_CAM_PGSZ_MASK; 194 u32 mask = get_cam_va_mask(cr->cam & page_size); 195 196 return cr->cam & mask; 197} 198 199static struct cr_regs *omap2_alloc_cr(struct iommu *obj, struct iotlb_entry *e) 200{ 201 struct cr_regs *cr; 202 203 if (e->da & ~(get_cam_va_mask(e->pgsz))) { 204 dev_err(obj->dev, "%s:\twrong alignment: %08x\n", __func__, 205 e->da); 206 return ERR_PTR(-EINVAL); 207 } 208 209 cr = kmalloc(sizeof(*cr), GFP_KERNEL); 210 if (!cr) 211 return ERR_PTR(-ENOMEM); 212 213 cr->cam = (e->da & MMU_CAM_VATAG_MASK) | e->prsvd | e->pgsz | e->valid; 214 cr->ram = e->pa | e->endian | e->elsz | e->mixed; 215 216 return cr; 217} 218 219static inline int omap2_cr_valid(struct cr_regs *cr) 220{ 221 return cr->cam & MMU_CAM_V; 222} 223 224static u32 omap2_get_pte_attr(struct iotlb_entry *e) 225{ 226 u32 attr; 227 228 attr = e->mixed << 5; 229 attr |= e->endian; 230 attr |= e->elsz >> 3; 231 attr <<= ((e->pgsz & MMU_CAM_PGSZ_4K) ? 0 : 6); 232 233 return attr; 234} 235 236static ssize_t omap2_dump_cr(struct iommu *obj, struct cr_regs *cr, char *buf) 237{ 238 char *p = buf; 239 240 p += sprintf(p, "%08x %08x %01x\n", cr->cam, cr->ram, 241 (cr->cam & MMU_CAM_P) ? 1 : 0); 242 243 return p - buf; 244} 245 246#define pr_reg(name) \ 247 do { \ 248 ssize_t bytes; \ 249 const char *str = "%20s: %08x\n"; \ 250 const int maxcol = 32; \ 251 bytes = snprintf(p, maxcol, str, __stringify(name), \ 252 iommu_read_reg(obj, MMU_##name)); \ 253 p += bytes; \ 254 len -= bytes; \ 255 if (len < maxcol) \ 256 goto out; \ 257 } while (0) 258 259static ssize_t omap2_iommu_dump_ctx(struct iommu *obj, char *buf, ssize_t len) 260{ 261 char *p = buf; 262 263 pr_reg(REVISION); 264 pr_reg(SYSCONFIG); 265 pr_reg(SYSSTATUS); 266 pr_reg(IRQSTATUS); 267 pr_reg(IRQENABLE); 268 pr_reg(WALKING_ST); 269 pr_reg(CNTL); 270 pr_reg(FAULT_AD); 271 pr_reg(TTB); 272 pr_reg(LOCK); 273 pr_reg(LD_TLB); 274 pr_reg(CAM); 275 pr_reg(RAM); 276 pr_reg(GFLUSH); 277 pr_reg(FLUSH_ENTRY); 278 pr_reg(READ_CAM); 279 pr_reg(READ_RAM); 280 pr_reg(EMU_FAULT_AD); 281out: 282 return p - buf; 283} 284 285static void omap2_iommu_save_ctx(struct iommu *obj) 286{ 287 int i; 288 u32 *p = obj->ctx; 289 290 for (i = 0; i < (MMU_REG_SIZE / sizeof(u32)); i++) { 291 p[i] = iommu_read_reg(obj, i * sizeof(u32)); 292 dev_dbg(obj->dev, "%s\t[%02d] %08x\n", __func__, i, p[i]); 293 } 294 295 BUG_ON(p[0] != IOMMU_ARCH_VERSION); 296} 297 298static void omap2_iommu_restore_ctx(struct iommu *obj) 299{ 300 int i; 301 u32 *p = obj->ctx; 302 303 for (i = 0; i < (MMU_REG_SIZE / sizeof(u32)); i++) { 304 iommu_write_reg(obj, p[i], i * sizeof(u32)); 305 dev_dbg(obj->dev, "%s\t[%02d] %08x\n", __func__, i, p[i]); 306 } 307 308 BUG_ON(p[0] != IOMMU_ARCH_VERSION); 309} 310 311static void omap2_cr_to_e(struct cr_regs *cr, struct iotlb_entry *e) 312{ 313 e->da = cr->cam & MMU_CAM_VATAG_MASK; 314 e->pa = cr->ram & MMU_RAM_PADDR_MASK; 315 e->valid = cr->cam & MMU_CAM_V; 316 e->pgsz = cr->cam & MMU_CAM_PGSZ_MASK; 317 e->endian = cr->ram & MMU_RAM_ENDIAN_MASK; 318 e->elsz = cr->ram & MMU_RAM_ELSZ_MASK; 319 e->mixed = cr->ram & MMU_RAM_MIXED; 320} 321 322static const struct iommu_functions omap2_iommu_ops = { 323 .version = IOMMU_ARCH_VERSION, 324 325 .enable = omap2_iommu_enable, 326 .disable = omap2_iommu_disable, 327 .set_twl = omap2_iommu_set_twl, 328 .fault_isr = omap2_iommu_fault_isr, 329 330 .tlb_read_cr = omap2_tlb_read_cr, 331 .tlb_load_cr = omap2_tlb_load_cr, 332 333 .cr_to_e = omap2_cr_to_e, 334 .cr_to_virt = omap2_cr_to_virt, 335 .alloc_cr = omap2_alloc_cr, 336 .cr_valid = omap2_cr_valid, 337 .dump_cr = omap2_dump_cr, 338 339 .get_pte_attr = omap2_get_pte_attr, 340 341 .save_ctx = omap2_iommu_save_ctx, 342 .restore_ctx = omap2_iommu_restore_ctx, 343 .dump_ctx = omap2_iommu_dump_ctx, 344}; 345 346static int __init omap2_iommu_init(void) 347{ 348 return install_iommu_arch(&omap2_iommu_ops); 349} 350module_init(omap2_iommu_init); 351 352static void __exit omap2_iommu_exit(void) 353{ 354 uninstall_iommu_arch(&omap2_iommu_ops); 355} 356module_exit(omap2_iommu_exit); 357 358MODULE_AUTHOR("Hiroshi DOYU, Paul Mundt and Toshihiro Kobayashi"); 359MODULE_DESCRIPTION("omap iommu: omap2/3 architecture specific functions"); 360MODULE_LICENSE("GPL v2"); 361