1 2#undef DEBUG 3 4#include <linux/kernel.h> 5#include <linux/errno.h> 6#include <linux/clk.h> 7#include <linux/io.h> 8 9#include <plat/clock.h> 10#include <plat/sram.h> 11#include <plat/sdrc.h> 12 13#include "clock.h" 14#include "clock2xxx.h" 15#include "opp2xxx.h" 16#include "cm.h" 17#include "cm-regbits-24xx.h" 18 19/* #define DOWN_VARIABLE_DPLL 1 */ /* Experimental */ 20 21/** 22 * omap2xxx_clk_get_core_rate - return the CORE_CLK rate 23 * @clk: pointer to the combined dpll_ck + core_ck (currently "dpll_ck") 24 * 25 * Returns the CORE_CLK rate. CORE_CLK can have one of three rate 26 * sources on OMAP2xxx: the DPLL CLKOUT rate, DPLL CLKOUTX2, or 32KHz 27 * (the latter is unusual). This currently should be called with 28 * struct clk *dpll_ck, which is a composite clock of dpll_ck and 29 * core_ck. 30 */ 31unsigned long omap2xxx_clk_get_core_rate(struct clk *clk) 32{ 33 long long core_clk; 34 u32 v; 35 36 core_clk = omap2_get_dpll_rate(clk); 37 38 v = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2); 39 v &= OMAP24XX_CORE_CLK_SRC_MASK; 40 41 if (v == CORE_CLK_SRC_32K) 42 core_clk = 32768; 43 else 44 core_clk *= v; 45 46 return core_clk; 47} 48 49/* 50 * Uses the current prcm set to tell if a rate is valid. 51 * You can go slower, but not faster within a given rate set. 52 */ 53static long omap2_dpllcore_round_rate(unsigned long target_rate) 54{ 55 u32 high, low, core_clk_src; 56 57 core_clk_src = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2); 58 core_clk_src &= OMAP24XX_CORE_CLK_SRC_MASK; 59 60 if (core_clk_src == CORE_CLK_SRC_DPLL) { /* DPLL clockout */ 61 high = curr_prcm_set->dpll_speed * 2; 62 low = curr_prcm_set->dpll_speed; 63 } else { /* DPLL clockout x 2 */ 64 high = curr_prcm_set->dpll_speed; 65 low = curr_prcm_set->dpll_speed / 2; 66 } 67 68#ifdef DOWN_VARIABLE_DPLL 69 if (target_rate > high) 70 return high; 71 else 72 return target_rate; 73#else 74 if (target_rate > low) 75 return high; 76 else 77 return low; 78#endif 79 80} 81 82unsigned long omap2_dpllcore_recalc(struct clk *clk) 83{ 84 return omap2xxx_clk_get_core_rate(clk); 85} 86 87int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate) 88{ 89 u32 cur_rate, low, mult, div, valid_rate, done_rate; 90 u32 bypass = 0; 91 struct prcm_config tmpset; 92 const struct dpll_data *dd; 93 94 cur_rate = omap2xxx_clk_get_core_rate(dclk); 95 mult = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2); 96 mult &= OMAP24XX_CORE_CLK_SRC_MASK; 97 98 if ((rate == (cur_rate / 2)) && (mult == 2)) { 99 omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL, 1); 100 } else if ((rate == (cur_rate * 2)) && (mult == 1)) { 101 omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL_X2, 1); 102 } else if (rate != cur_rate) { 103 valid_rate = omap2_dpllcore_round_rate(rate); 104 if (valid_rate != rate) 105 return -EINVAL; 106 107 if (mult == 1) 108 low = curr_prcm_set->dpll_speed; 109 else 110 low = curr_prcm_set->dpll_speed / 2; 111 112 dd = clk->dpll_data; 113 if (!dd) 114 return -EINVAL; 115 116 tmpset.cm_clksel1_pll = __raw_readl(dd->mult_div1_reg); 117 tmpset.cm_clksel1_pll &= ~(dd->mult_mask | 118 dd->div1_mask); 119 div = ((curr_prcm_set->xtal_speed / 1000000) - 1); 120 tmpset.cm_clksel2_pll = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2); 121 tmpset.cm_clksel2_pll &= ~OMAP24XX_CORE_CLK_SRC_MASK; 122 if (rate > low) { 123 tmpset.cm_clksel2_pll |= CORE_CLK_SRC_DPLL_X2; 124 mult = ((rate / 2) / 1000000); 125 done_rate = CORE_CLK_SRC_DPLL_X2; 126 } else { 127 tmpset.cm_clksel2_pll |= CORE_CLK_SRC_DPLL; 128 mult = (rate / 1000000); 129 done_rate = CORE_CLK_SRC_DPLL; 130 } 131 tmpset.cm_clksel1_pll |= (div << __ffs(dd->mult_mask)); 132 tmpset.cm_clksel1_pll |= (mult << __ffs(dd->div1_mask)); 133 134 /* Worst case */ 135 tmpset.base_sdrc_rfr = SDRC_RFR_CTRL_BYPASS; 136 137 if (rate == curr_prcm_set->xtal_speed) /* If asking for 1-1 */ 138 bypass = 1; 139 140 /* For omap2xxx_sdrc_init_params() */ 141 omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL_X2, 1); 142 143 /* Force dll lock mode */ 144 omap2_set_prcm(tmpset.cm_clksel1_pll, tmpset.base_sdrc_rfr, 145 bypass); 146 147 /* Errata: ret dll entry state */ 148 omap2xxx_sdrc_init_params(omap2xxx_sdrc_dll_is_unlocked()); 149 omap2xxx_sdrc_reprogram(done_rate, 0); 150 } 151 152 return 0; 153} 154