1/* 2 * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved. 3 * 4 * The code contained herein is licensed under the GNU General Public 5 * License. You may obtain a copy of the GNU General Public License 6 * Version 2 or later at the following locations: 7 * 8 * http://www.opensource.org/licenses/gpl-license.html 9 * http://www.gnu.org/copyleft/gpl.html 10 */ 11#ifndef __ARCH_ARM_MACH_MX51_CRM_REGS_H__ 12#define __ARCH_ARM_MACH_MX51_CRM_REGS_H__ 13 14#define MX51_CCM_BASE MX51_IO_ADDRESS(MX51_CCM_BASE_ADDR) 15#define MX51_DPLL1_BASE MX51_IO_ADDRESS(MX51_PLL1_BASE_ADDR) 16#define MX51_DPLL2_BASE MX51_IO_ADDRESS(MX51_PLL2_BASE_ADDR) 17#define MX51_DPLL3_BASE MX51_IO_ADDRESS(MX51_PLL3_BASE_ADDR) 18#define MX51_CORTEXA8_BASE MX51_IO_ADDRESS(MX51_ARM_BASE_ADDR) 19#define MX51_GPC_BASE MX51_IO_ADDRESS(MX51_GPC_BASE_ADDR) 20 21/* PLL Register Offsets */ 22#define MXC_PLL_DP_CTL 0x00 23#define MXC_PLL_DP_CONFIG 0x04 24#define MXC_PLL_DP_OP 0x08 25#define MXC_PLL_DP_MFD 0x0C 26#define MXC_PLL_DP_MFN 0x10 27#define MXC_PLL_DP_MFNMINUS 0x14 28#define MXC_PLL_DP_MFNPLUS 0x18 29#define MXC_PLL_DP_HFS_OP 0x1C 30#define MXC_PLL_DP_HFS_MFD 0x20 31#define MXC_PLL_DP_HFS_MFN 0x24 32#define MXC_PLL_DP_MFN_TOGC 0x28 33#define MXC_PLL_DP_DESTAT 0x2c 34 35/* PLL Register Bit definitions */ 36#define MXC_PLL_DP_CTL_MUL_CTRL 0x2000 37#define MXC_PLL_DP_CTL_DPDCK0_2_EN 0x1000 38#define MXC_PLL_DP_CTL_DPDCK0_2_OFFSET 12 39#define MXC_PLL_DP_CTL_ADE 0x800 40#define MXC_PLL_DP_CTL_REF_CLK_DIV 0x400 41#define MXC_PLL_DP_CTL_REF_CLK_SEL_MASK (3 << 8) 42#define MXC_PLL_DP_CTL_REF_CLK_SEL_OFFSET 8 43#define MXC_PLL_DP_CTL_HFSM 0x80 44#define MXC_PLL_DP_CTL_PRE 0x40 45#define MXC_PLL_DP_CTL_UPEN 0x20 46#define MXC_PLL_DP_CTL_RST 0x10 47#define MXC_PLL_DP_CTL_RCP 0x8 48#define MXC_PLL_DP_CTL_PLM 0x4 49#define MXC_PLL_DP_CTL_BRM0 0x2 50#define MXC_PLL_DP_CTL_LRF 0x1 51 52#define MXC_PLL_DP_CONFIG_BIST 0x8 53#define MXC_PLL_DP_CONFIG_SJC_CE 0x4 54#define MXC_PLL_DP_CONFIG_AREN 0x2 55#define MXC_PLL_DP_CONFIG_LDREQ 0x1 56 57#define MXC_PLL_DP_OP_MFI_OFFSET 4 58#define MXC_PLL_DP_OP_MFI_MASK (0xF << 4) 59#define MXC_PLL_DP_OP_PDF_OFFSET 0 60#define MXC_PLL_DP_OP_PDF_MASK 0xF 61 62#define MXC_PLL_DP_MFD_OFFSET 0 63#define MXC_PLL_DP_MFD_MASK 0x07FFFFFF 64 65#define MXC_PLL_DP_MFN_OFFSET 0x0 66#define MXC_PLL_DP_MFN_MASK 0x07FFFFFF 67 68#define MXC_PLL_DP_MFN_TOGC_TOG_DIS (1 << 17) 69#define MXC_PLL_DP_MFN_TOGC_TOG_EN (1 << 16) 70#define MXC_PLL_DP_MFN_TOGC_CNT_OFFSET 0x0 71#define MXC_PLL_DP_MFN_TOGC_CNT_MASK 0xFFFF 72 73#define MXC_PLL_DP_DESTAT_TOG_SEL (1 << 31) 74#define MXC_PLL_DP_DESTAT_MFN 0x07FFFFFF 75 76/* Register addresses of CCM*/ 77#define MXC_CCM_CCR (MX51_CCM_BASE + 0x00) 78#define MXC_CCM_CCDR (MX51_CCM_BASE + 0x04) 79#define MXC_CCM_CSR (MX51_CCM_BASE + 0x08) 80#define MXC_CCM_CCSR (MX51_CCM_BASE + 0x0C) 81#define MXC_CCM_CACRR (MX51_CCM_BASE + 0x10) 82#define MXC_CCM_CBCDR (MX51_CCM_BASE + 0x14) 83#define MXC_CCM_CBCMR (MX51_CCM_BASE + 0x18) 84#define MXC_CCM_CSCMR1 (MX51_CCM_BASE + 0x1C) 85#define MXC_CCM_CSCMR2 (MX51_CCM_BASE + 0x20) 86#define MXC_CCM_CSCDR1 (MX51_CCM_BASE + 0x24) 87#define MXC_CCM_CS1CDR (MX51_CCM_BASE + 0x28) 88#define MXC_CCM_CS2CDR (MX51_CCM_BASE + 0x2C) 89#define MXC_CCM_CDCDR (MX51_CCM_BASE + 0x30) 90#define MXC_CCM_CHSCDR (MX51_CCM_BASE + 0x34) 91#define MXC_CCM_CSCDR2 (MX51_CCM_BASE + 0x38) 92#define MXC_CCM_CSCDR3 (MX51_CCM_BASE + 0x3C) 93#define MXC_CCM_CSCDR4 (MX51_CCM_BASE + 0x40) 94#define MXC_CCM_CWDR (MX51_CCM_BASE + 0x44) 95#define MXC_CCM_CDHIPR (MX51_CCM_BASE + 0x48) 96#define MXC_CCM_CDCR (MX51_CCM_BASE + 0x4C) 97#define MXC_CCM_CTOR (MX51_CCM_BASE + 0x50) 98#define MXC_CCM_CLPCR (MX51_CCM_BASE + 0x54) 99#define MXC_CCM_CISR (MX51_CCM_BASE + 0x58) 100#define MXC_CCM_CIMR (MX51_CCM_BASE + 0x5C) 101#define MXC_CCM_CCOSR (MX51_CCM_BASE + 0x60) 102#define MXC_CCM_CGPR (MX51_CCM_BASE + 0x64) 103#define MXC_CCM_CCGR0 (MX51_CCM_BASE + 0x68) 104#define MXC_CCM_CCGR1 (MX51_CCM_BASE + 0x6C) 105#define MXC_CCM_CCGR2 (MX51_CCM_BASE + 0x70) 106#define MXC_CCM_CCGR3 (MX51_CCM_BASE + 0x74) 107#define MXC_CCM_CCGR4 (MX51_CCM_BASE + 0x78) 108#define MXC_CCM_CCGR5 (MX51_CCM_BASE + 0x7C) 109#define MXC_CCM_CCGR6 (MX51_CCM_BASE + 0x80) 110#define MXC_CCM_CMEOR (MX51_CCM_BASE + 0x84) 111 112/* Define the bits in register CCR */ 113#define MXC_CCM_CCR_COSC_EN (1 << 12) 114#define MXC_CCM_CCR_FPM_MULT_MASK (1 << 11) 115#define MXC_CCM_CCR_CAMP2_EN (1 << 10) 116#define MXC_CCM_CCR_CAMP1_EN (1 << 9) 117#define MXC_CCM_CCR_FPM_EN (1 << 8) 118#define MXC_CCM_CCR_OSCNT_OFFSET (0) 119#define MXC_CCM_CCR_OSCNT_MASK (0xFF) 120 121/* Define the bits in register CCDR */ 122#define MXC_CCM_CCDR_HSC_HS_MASK (0x1 << 18) 123#define MXC_CCM_CCDR_IPU_HS_MASK (0x1 << 17) 124#define MXC_CCM_CCDR_EMI_HS_MASK (0x1 << 16) 125 126/* Define the bits in register CSR */ 127#define MXC_CCM_CSR_COSR_READY (1 << 5) 128#define MXC_CCM_CSR_LVS_VALUE (1 << 4) 129#define MXC_CCM_CSR_CAMP2_READY (1 << 3) 130#define MXC_CCM_CSR_CAMP1_READY (1 << 2) 131#define MXC_CCM_CSR_FPM_READY (1 << 1) 132#define MXC_CCM_CSR_REF_EN_B (1 << 0) 133 134/* Define the bits in register CCSR */ 135#define MXC_CCM_CCSR_LP_APM_SEL (0x1 << 9) 136#define MXC_CCM_CCSR_STEP_SEL_OFFSET (7) 137#define MXC_CCM_CCSR_STEP_SEL_MASK (0x3 << 7) 138#define MXC_CCM_CCSR_STEP_SEL_LP_APM 0 139#define MXC_CCM_CCSR_STEP_SEL_PLL1_BYPASS 1 /* Only when JTAG connected? */ 140#define MXC_CCM_CCSR_STEP_SEL_PLL2_DIVIDED 2 141#define MXC_CCM_CCSR_STEP_SEL_PLL3_DIVIDED 3 142#define MXC_CCM_CCSR_PLL2_PODF_OFFSET (5) 143#define MXC_CCM_CCSR_PLL2_PODF_MASK (0x3 << 5) 144#define MXC_CCM_CCSR_PLL3_PODF_OFFSET (3) 145#define MXC_CCM_CCSR_PLL3_PODF_MASK (0x3 << 3) 146#define MXC_CCM_CCSR_PLL1_SW_CLK_SEL (1 << 2) /* 0: pll1_main_clk, 147 1: step_clk */ 148#define MXC_CCM_CCSR_PLL2_SW_CLK_SEL (1 << 1) 149#define MXC_CCM_CCSR_PLL3_SW_CLK_SEL (1 << 0) 150 151/* Define the bits in register CACRR */ 152#define MXC_CCM_CACRR_ARM_PODF_OFFSET (0) 153#define MXC_CCM_CACRR_ARM_PODF_MASK (0x7) 154 155/* Define the bits in register CBCDR */ 156#define MXC_CCM_CBCDR_EMI_CLK_SEL (0x1 << 26) 157#define MXC_CCM_CBCDR_PERIPH_CLK_SEL (0x1 << 25) 158#define MXC_CCM_CBCDR_DDR_HF_SEL_OFFSET (30) 159#define MXC_CCM_CBCDR_DDR_HF_SEL (0x1 << 30) 160#define MXC_CCM_CBCDR_DDR_PODF_OFFSET (27) 161#define MXC_CCM_CBCDR_DDR_PODF_MASK (0x7 << 27) 162#define MXC_CCM_CBCDR_EMI_PODF_OFFSET (22) 163#define MXC_CCM_CBCDR_EMI_PODF_MASK (0x7 << 22) 164#define MXC_CCM_CBCDR_AXI_B_PODF_OFFSET (19) 165#define MXC_CCM_CBCDR_AXI_B_PODF_MASK (0x7 << 19) 166#define MXC_CCM_CBCDR_AXI_A_PODF_OFFSET (16) 167#define MXC_CCM_CBCDR_AXI_A_PODF_MASK (0x7 << 16) 168#define MXC_CCM_CBCDR_NFC_PODF_OFFSET (13) 169#define MXC_CCM_CBCDR_NFC_PODF_MASK (0x7 << 13) 170#define MXC_CCM_CBCDR_AHB_PODF_OFFSET (10) 171#define MXC_CCM_CBCDR_AHB_PODF_MASK (0x7 << 10) 172#define MXC_CCM_CBCDR_IPG_PODF_OFFSET (8) 173#define MXC_CCM_CBCDR_IPG_PODF_MASK (0x3 << 8) 174#define MXC_CCM_CBCDR_PERCLK_PRED1_OFFSET (6) 175#define MXC_CCM_CBCDR_PERCLK_PRED1_MASK (0x3 << 6) 176#define MXC_CCM_CBCDR_PERCLK_PRED2_OFFSET (3) 177#define MXC_CCM_CBCDR_PERCLK_PRED2_MASK (0x7 << 3) 178#define MXC_CCM_CBCDR_PERCLK_PODF_OFFSET (0) 179#define MXC_CCM_CBCDR_PERCLK_PODF_MASK (0x7) 180 181/* Define the bits in register CBCMR */ 182#define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_OFFSET (14) 183#define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_MASK (0x3 << 14) 184#define MXC_CCM_CBCMR_PERIPH_CLK_SEL_OFFSET (12) 185#define MXC_CCM_CBCMR_PERIPH_CLK_SEL_MASK (0x3 << 12) 186#define MXC_CCM_CBCMR_DDR_CLK_SEL_OFFSET (10) 187#define MXC_CCM_CBCMR_DDR_CLK_SEL_MASK (0x3 << 10) 188#define MXC_CCM_CBCMR_ARM_AXI_CLK_SEL_OFFSET (8) 189#define MXC_CCM_CBCMR_ARM_AXI_CLK_SEL_MASK (0x3 << 8) 190#define MXC_CCM_CBCMR_IPU_HSP_CLK_SEL_OFFSET (6) 191#define MXC_CCM_CBCMR_IPU_HSP_CLK_SEL_MASK (0x3 << 6) 192#define MXC_CCM_CBCMR_GPU_CLK_SEL_OFFSET (4) 193#define MXC_CCM_CBCMR_GPU_CLK_SEL_MASK (0x3 << 4) 194#define MXC_CCM_CBCMR_GPU2D_CLK_SEL_OFFSET (14) 195#define MXC_CCM_CBCMR_GPU2D_CLK_SEL_MASK (0x3 << 14) 196#define MXC_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL (0x1 << 1) 197#define MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL (0x1 << 0) 198 199/* Define the bits in register CSCMR1 */ 200#define MXC_CCM_CSCMR1_SSI_EXT2_CLK_SEL_OFFSET (30) 201#define MXC_CCM_CSCMR1_SSI_EXT2_CLK_SEL_MASK (0x3 << 30) 202#define MXC_CCM_CSCMR1_SSI_EXT1_CLK_SEL_OFFSET (28) 203#define MXC_CCM_CSCMR1_SSI_EXT1_CLK_SEL_MASK (0x3 << 28) 204#define MXC_CCM_CSCMR1_USB_PHY_CLK_SEL_OFFSET (26) 205#define MXC_CCM_CSCMR1_USB_PHY_CLK_SEL (0x1 << 26) 206#define MXC_CCM_CSCMR1_UART_CLK_SEL_OFFSET (24) 207#define MXC_CCM_CSCMR1_UART_CLK_SEL_MASK (0x3 << 24) 208#define MXC_CCM_CSCMR1_USBOH3_CLK_SEL_OFFSET (22) 209#define MXC_CCM_CSCMR1_USBOH3_CLK_SEL_MASK (0x3 << 22) 210#define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_OFFSET (20) 211#define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_MASK (0x3 << 20) 212#define MXC_CCM_CSCMR1_ESDHC3_CLK_SEL (0x1 << 19) 213#define MXC_CCM_CSCMR1_ESDHC4_CLK_SEL (0x1 << 18) 214#define MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_OFFSET (16) 215#define MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_MASK (0x3 << 16) 216#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET (14) 217#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_MASK (0x3 << 14) 218#define MXC_CCM_CSCMR1_SSI2_CLK_SEL_OFFSET (12) 219#define MXC_CCM_CSCMR1_SSI2_CLK_SEL_MASK (0x3 << 12) 220#define MXC_CCM_CSCMR1_SSI3_CLK_SEL (0x1 << 11) 221#define MXC_CCM_CSCMR1_VPU_RCLK_SEL (0x1 << 10) 222#define MXC_CCM_CSCMR1_SSI_APM_CLK_SEL_OFFSET (8) 223#define MXC_CCM_CSCMR1_SSI_APM_CLK_SEL_MASK (0x3 << 8) 224#define MXC_CCM_CSCMR1_TVE_CLK_SEL (0x1 << 7) 225#define MXC_CCM_CSCMR1_TVE_EXT_CLK_SEL (0x1 << 6) 226#define MXC_CCM_CSCMR1_CSPI_CLK_SEL_OFFSET (4) 227#define MXC_CCM_CSCMR1_CSPI_CLK_SEL_MASK (0x3 << 4) 228#define MXC_CCM_CSCMR1_SPDIF_CLK_SEL_OFFSET (2) 229#define MXC_CCM_CSCMR1_SPDIF_CLK_SEL_MASK (0x3 << 2) 230#define MXC_CCM_CSCMR1_SSI_EXT2_COM_CLK_SEL (0x1 << 1) 231#define MXC_CCM_CSCMR1_SSI_EXT1_COM_CLK_SEL (0x1) 232 233/* Define the bits in register CSCMR2 */ 234#define MXC_CCM_CSCMR2_DI_CLK_SEL_OFFSET(n) (26+n*3) 235#define MXC_CCM_CSCMR2_DI_CLK_SEL_MASK(n) (0x7 << (26+n*3)) 236#define MXC_CCM_CSCMR2_CSI_MCLK2_CLK_SEL_OFFSET (24) 237#define MXC_CCM_CSCMR2_CSI_MCLK2_CLK_SEL_MASK (0x3 << 24) 238#define MXC_CCM_CSCMR2_CSI_MCLK1_CLK_SEL_OFFSET (22) 239#define MXC_CCM_CSCMR2_CSI_MCLK1_CLK_SEL_MASK (0x3 << 22) 240#define MXC_CCM_CSCMR2_ESC_CLK_SEL_OFFSET (20) 241#define MXC_CCM_CSCMR2_ESC_CLK_SEL_MASK (0x3 << 20) 242#define MXC_CCM_CSCMR2_HSC2_CLK_SEL_OFFSET (18) 243#define MXC_CCM_CSCMR2_HSC2_CLK_SEL_MASK (0x3 << 18) 244#define MXC_CCM_CSCMR2_HSC1_CLK_SEL_OFFSET (16) 245#define MXC_CCM_CSCMR2_HSC1_CLK_SEL_MASK (0x3 << 16) 246#define MXC_CCM_CSCMR2_HSI2C_CLK_SEL_OFFSET (14) 247#define MXC_CCM_CSCMR2_HSI2C_CLK_SEL_MASK (0x3 << 14) 248#define MXC_CCM_CSCMR2_FIRI_CLK_SEL_OFFSET (12) 249#define MXC_CCM_CSCMR2_FIRI_CLK_SEL_MASK (0x3 << 12) 250#define MXC_CCM_CSCMR2_SIM_CLK_SEL_OFFSET (10) 251#define MXC_CCM_CSCMR2_SIM_CLK_SEL_MASK (0x3 << 10) 252#define MXC_CCM_CSCMR2_SLIMBUS_COM (0x1 << 9) 253#define MXC_CCM_CSCMR2_SLIMBUS_CLK_SEL_OFFSET (6) 254#define MXC_CCM_CSCMR2_SLIMBUS_CLK_SEL_MASK (0x7 << 6) 255#define MXC_CCM_CSCMR2_SPDIF1_COM (1 << 5) 256#define MXC_CCM_CSCMR2_SPDIF0_COM (1 << 4) 257#define MXC_CCM_CSCMR2_SPDIF1_CLK_SEL_OFFSET (2) 258#define MXC_CCM_CSCMR2_SPDIF1_CLK_SEL_MASK (0x3 << 2) 259#define MXC_CCM_CSCMR2_SPDIF0_CLK_SEL_OFFSET (0) 260#define MXC_CCM_CSCMR2_SPDIF0_CLK_SEL_MASK (0x3) 261 262/* Define the bits in register CSCDR1 */ 263#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_OFFSET (22) 264#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_MASK (0x7 << 22) 265#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_OFFSET (19) 266#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_MASK (0x7 << 19) 267#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_OFFSET (16) 268#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_MASK (0x7 << 16) 269#define MXC_CCM_CSCDR1_PGC_CLK_PODF_OFFSET (14) 270#define MXC_CCM_CSCDR1_PGC_CLK_PODF_MASK (0x3 << 14) 271#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_OFFSET (11) 272#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_MASK (0x7 << 11) 273#define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET (8) 274#define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK (0x7 << 8) 275#define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET (6) 276#define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK (0x3 << 6) 277#define MXC_CCM_CSCDR1_UART_CLK_PRED_OFFSET (3) 278#define MXC_CCM_CSCDR1_UART_CLK_PRED_MASK (0x7 << 3) 279#define MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET (0) 280#define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK (0x7) 281 282/* Define the bits in register CS1CDR and CS2CDR */ 283#define MXC_CCM_CS1CDR_SSI_EXT1_CLK_PRED_OFFSET (22) 284#define MXC_CCM_CS1CDR_SSI_EXT1_CLK_PRED_MASK (0x7 << 22) 285#define MXC_CCM_CS1CDR_SSI_EXT1_CLK_PODF_OFFSET (16) 286#define MXC_CCM_CS1CDR_SSI_EXT1_CLK_PODF_MASK (0x3F << 16) 287#define MXC_CCM_CS1CDR_SSI1_CLK_PRED_OFFSET (6) 288#define MXC_CCM_CS1CDR_SSI1_CLK_PRED_MASK (0x7 << 6) 289#define MXC_CCM_CS1CDR_SSI1_CLK_PODF_OFFSET (0) 290#define MXC_CCM_CS1CDR_SSI1_CLK_PODF_MASK (0x3F) 291 292#define MXC_CCM_CS2CDR_SSI_EXT2_CLK_PRED_OFFSET (22) 293#define MXC_CCM_CS2CDR_SSI_EXT2_CLK_PRED_MASK (0x7 << 22) 294#define MXC_CCM_CS2CDR_SSI_EXT2_CLK_PODF_OFFSET (16) 295#define MXC_CCM_CS2CDR_SSI_EXT2_CLK_PODF_MASK (0x3F << 16) 296#define MXC_CCM_CS2CDR_SSI2_CLK_PRED_OFFSET (6) 297#define MXC_CCM_CS2CDR_SSI2_CLK_PRED_MASK (0x7 << 6) 298#define MXC_CCM_CS2CDR_SSI2_CLK_PODF_OFFSET (0) 299#define MXC_CCM_CS2CDR_SSI2_CLK_PODF_MASK (0x3F) 300 301/* Define the bits in register CDCDR */ 302#define MXC_CCM_CDCDR_TVE_CLK_PRED_OFFSET (28) 303#define MXC_CCM_CDCDR_TVE_CLK_PRED_MASK (0x7 << 28) 304#define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_OFFSET (25) 305#define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_MASK (0x7 << 25) 306#define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_OFFSET (19) 307#define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_MASK (0x3F << 19) 308#define MXC_CCM_CDCDR_SPDIF1_CLK_PRED_OFFSET (16) 309#define MXC_CCM_CDCDR_SPDIF1_CLK_PRED_MASK (0x7 << 16) 310#define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_OFFSET (9) 311#define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_MASK (0x3F << 9) 312#define MXC_CCM_CDCDR_DI_CLK_PRED_OFFSET (6) 313#define MXC_CCM_CDCDR_DI_CLK_PRED_MASK (0x7 << 6) 314#define MXC_CCM_CDCDR_USB_PHY_PRED_OFFSET (3) 315#define MXC_CCM_CDCDR_USB_PHY_PRED_MASK (0x7 << 3) 316#define MXC_CCM_CDCDR_USB_PHY_PODF_OFFSET (0) 317#define MXC_CCM_CDCDR_USB_PHY_PODF_MASK (0x7) 318 319/* Define the bits in register CHSCCDR */ 320#define MXC_CCM_CHSCCDR_ESC_CLK_PRED_OFFSET (12) 321#define MXC_CCM_CHSCCDR_ESC_CLK_PRED_MASK (0x7 << 12) 322#define MXC_CCM_CHSCCDR_ESC_CLK_PODF_OFFSET (6) 323#define MXC_CCM_CHSCCDR_ESC_CLK_PODF_MASK (0x3F << 6) 324#define MXC_CCM_CHSCCDR_HSC2_CLK_PODF_OFFSET (3) 325#define MXC_CCM_CHSCCDR_HSC2_CLK_PODF_MASK (0x7 << 3) 326#define MXC_CCM_CHSCCDR_HSC1_CLK_PODF_OFFSET (0) 327#define MXC_CCM_CHSCCDR_HSC1_CLK_PODF_MASK (0x7) 328 329/* Define the bits in register CSCDR2 */ 330#define MXC_CCM_CSCDR2_CSPI_CLK_PRED_OFFSET (25) 331#define MXC_CCM_CSCDR2_CSPI_CLK_PRED_MASK (0x7 << 25) 332#define MXC_CCM_CSCDR2_CSPI_CLK_PODF_OFFSET (19) 333#define MXC_CCM_CSCDR2_CSPI_CLK_PODF_MASK (0x3F << 19) 334#define MXC_CCM_CSCDR2_SIM_CLK_PRED_OFFSET (16) 335#define MXC_CCM_CSCDR2_SIM_CLK_PRED_MASK (0x7 << 16) 336#define MXC_CCM_CSCDR2_SIM_CLK_PODF_OFFSET (9) 337#define MXC_CCM_CSCDR2_SIM_CLK_PODF_MASK (0x3F << 9) 338#define MXC_CCM_CSCDR2_SLIMBUS_CLK_PRED_OFFSET (6) 339#define MXC_CCM_CSCDR2_SLIMBUS_PRED_MASK (0x7 << 6) 340#define MXC_CCM_CSCDR2_SLIMBUS_PODF_OFFSET (0) 341#define MXC_CCM_CSCDR2_SLIMBUS_PODF_MASK (0x3F) 342 343/* Define the bits in register CSCDR3 */ 344#define MXC_CCM_CSCDR3_HSI2C_CLK_PRED_OFFSET (16) 345#define MXC_CCM_CSCDR3_HSI2C_CLK_PRED_MASK (0x7 << 16) 346#define MXC_CCM_CSCDR3_HSI2C_CLK_PODF_OFFSET (9) 347#define MXC_CCM_CSCDR3_HSI2C_CLK_PODF_MASK (0x3F << 9) 348#define MXC_CCM_CSCDR3_FIRI_CLK_PRED_OFFSET (6) 349#define MXC_CCM_CSCDR3_FIRI_CLK_PRED_MASK (0x7 << 6) 350#define MXC_CCM_CSCDR3_FIRI_CLK_PODF_OFFSET (0) 351#define MXC_CCM_CSCDR3_FIRI_CLK_PODF_MASK (0x3F) 352 353/* Define the bits in register CSCDR4 */ 354#define MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PRED_OFFSET (16) 355#define MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PRED_MASK (0x7 << 16) 356#define MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PODF_OFFSET (9) 357#define MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PODF_MASK (0x3F << 9) 358#define MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PRED_OFFSET (6) 359#define MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PRED_MASK (0x7 << 6) 360#define MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PODF_OFFSET (0) 361#define MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PODF_MASK (0x3F) 362 363/* Define the bits in register CDHIPR */ 364#define MXC_CCM_CDHIPR_ARM_PODF_BUSY (1 << 16) 365#define MXC_CCM_CDHIPR_DDR_HF_CLK_SEL_BUSY (1 << 8) 366#define MXC_CCM_CDHIPR_DDR_PODF_BUSY (1 << 7) 367#define MXC_CCM_CDHIPR_EMI_CLK_SEL_BUSY (1 << 6) 368#define MXC_CCM_CDHIPR_PERIPH_CLK_SEL_BUSY (1 << 5) 369#define MXC_CCM_CDHIPR_NFC_IPG_INT_MEM_PODF_BUSY (1 << 4) 370#define MXC_CCM_CDHIPR_AHB_PODF_BUSY (1 << 3) 371#define MXC_CCM_CDHIPR_EMI_PODF_BUSY (1 << 2) 372#define MXC_CCM_CDHIPR_AXI_B_PODF_BUSY (1 << 1) 373#define MXC_CCM_CDHIPR_AXI_A_PODF_BUSY (1 << 0) 374 375/* Define the bits in register CDCR */ 376#define MXC_CCM_CDCR_ARM_FREQ_SHIFT_DIVIDER (0x1 << 2) 377#define MXC_CCM_CDCR_PERIPH_CLK_DVFS_PODF_OFFSET (0) 378#define MXC_CCM_CDCR_PERIPH_CLK_DVFS_PODF_MASK (0x3) 379 380/* Define the bits in register CLPCR */ 381#define MXC_CCM_CLPCR_BYPASS_HSC_LPM_HS (0x1 << 23) 382#define MXC_CCM_CLPCR_BYPASS_SCC_LPM_HS (0x1 << 22) 383#define MXC_CCM_CLPCR_BYPASS_MAX_LPM_HS (0x1 << 21) 384#define MXC_CCM_CLPCR_BYPASS_SDMA_LPM_HS (0x1 << 20) 385#define MXC_CCM_CLPCR_BYPASS_EMI_LPM_HS (0x1 << 19) 386#define MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS (0x1 << 18) 387#define MXC_CCM_CLPCR_BYPASS_RTIC_LPM_HS (0x1 << 17) 388#define MXC_CCM_CLPCR_BYPASS_RNGC_LPM_HS (0x1 << 16) 389#define MXC_CCM_CLPCR_COSC_PWRDOWN (0x1 << 11) 390#define MXC_CCM_CLPCR_STBY_COUNT_OFFSET (9) 391#define MXC_CCM_CLPCR_STBY_COUNT_MASK (0x3 << 9) 392#define MXC_CCM_CLPCR_VSTBY (0x1 << 8) 393#define MXC_CCM_CLPCR_DIS_REF_OSC (0x1 << 7) 394#define MXC_CCM_CLPCR_SBYOS (0x1 << 6) 395#define MXC_CCM_CLPCR_ARM_CLK_DIS_ON_LPM (0x1 << 5) 396#define MXC_CCM_CLPCR_LPSR_CLK_SEL_OFFSET (3) 397#define MXC_CCM_CLPCR_LPSR_CLK_SEL_MASK (0x3 << 3) 398#define MXC_CCM_CLPCR_LPM_OFFSET (0) 399#define MXC_CCM_CLPCR_LPM_MASK (0x3) 400 401/* Define the bits in register CISR */ 402#define MXC_CCM_CISR_ARM_PODF_LOADED (0x1 << 25) 403#define MXC_CCM_CISR_NFC_IPG_INT_MEM_PODF_LOADED (0x1 << 21) 404#define MXC_CCM_CISR_AHB_PODF_LOADED (0x1 << 20) 405#define MXC_CCM_CISR_EMI_PODF_LOADED (0x1 << 19) 406#define MXC_CCM_CISR_AXI_B_PODF_LOADED (0x1 << 18) 407#define MXC_CCM_CISR_AXI_A_PODF_LOADED (0x1 << 17) 408#define MXC_CCM_CISR_DIVIDER_LOADED (0x1 << 16) 409#define MXC_CCM_CISR_COSC_READY (0x1 << 6) 410#define MXC_CCM_CISR_CKIH2_READY (0x1 << 5) 411#define MXC_CCM_CISR_CKIH_READY (0x1 << 4) 412#define MXC_CCM_CISR_FPM_READY (0x1 << 3) 413#define MXC_CCM_CISR_LRF_PLL3 (0x1 << 2) 414#define MXC_CCM_CISR_LRF_PLL2 (0x1 << 1) 415#define MXC_CCM_CISR_LRF_PLL1 (0x1) 416 417/* Define the bits in register CIMR */ 418#define MXC_CCM_CIMR_MASK_ARM_PODF_LOADED (0x1 << 25) 419#define MXC_CCM_CIMR_MASK_NFC_IPG_INT_MEM_PODF_LOADED (0x1 << 21) 420#define MXC_CCM_CIMR_MASK_EMI_PODF_LOADED (0x1 << 20) 421#define MXC_CCM_CIMR_MASK_AXI_C_PODF_LOADED (0x1 << 19) 422#define MXC_CCM_CIMR_MASK_AXI_B_PODF_LOADED (0x1 << 18) 423#define MXC_CCM_CIMR_MASK_AXI_A_PODF_LOADED (0x1 << 17) 424#define MXC_CCM_CIMR_MASK_DIVIDER_LOADED (0x1 << 16) 425#define MXC_CCM_CIMR_MASK_COSC_READY (0x1 << 5) 426#define MXC_CCM_CIMR_MASK_CKIH_READY (0x1 << 4) 427#define MXC_CCM_CIMR_MASK_FPM_READY (0x1 << 3) 428#define MXC_CCM_CIMR_MASK_LRF_PLL3 (0x1 << 2) 429#define MXC_CCM_CIMR_MASK_LRF_PLL2 (0x1 << 1) 430#define MXC_CCM_CIMR_MASK_LRF_PLL1 (0x1) 431 432/* Define the bits in register CCOSR */ 433#define MXC_CCM_CCOSR_CKO2_EN_OFFSET (0x1 << 24) 434#define MXC_CCM_CCOSR_CKO2_DIV_OFFSET (21) 435#define MXC_CCM_CCOSR_CKO2_DIV_MASK (0x7 << 21) 436#define MXC_CCM_CCOSR_CKO2_SEL_OFFSET (16) 437#define MXC_CCM_CCOSR_CKO2_SEL_MASK (0x1F << 16) 438#define MXC_CCM_CCOSR_CKOL_EN (0x1 << 7) 439#define MXC_CCM_CCOSR_CKOL_DIV_OFFSET (4) 440#define MXC_CCM_CCOSR_CKOL_DIV_MASK (0x7 << 4) 441#define MXC_CCM_CCOSR_CKOL_SEL_OFFSET (0) 442#define MXC_CCM_CCOSR_CKOL_SEL_MASK (0xF) 443 444/* Define the bits in registers CGPR */ 445#define MXC_CCM_CGPR_EFUSE_PROG_SUPPLY_GATE (0x1 << 4) 446#define MXC_CCM_CGPR_FPM_SEL (0x1 << 3) 447#define MXC_CCM_CGPR_VL_L2BIST_CLKDIV_OFFSET (0) 448#define MXC_CCM_CGPR_VL_L2BIST_CLKDIV_MASK (0x7) 449 450/* Define the bits in registers CCGRx */ 451#define MXC_CCM_CCGRx_CG_MASK 0x3 452#define MXC_CCM_CCGRx_MOD_OFF 0x0 453#define MXC_CCM_CCGRx_MOD_ON 0x3 454#define MXC_CCM_CCGRx_MOD_IDLE 0x1 455 456#define MXC_CCM_CCGRx_CG15_MASK (0x3 << 30) 457#define MXC_CCM_CCGRx_CG14_MASK (0x3 << 28) 458#define MXC_CCM_CCGRx_CG13_MASK (0x3 << 26) 459#define MXC_CCM_CCGRx_CG12_MASK (0x3 << 24) 460#define MXC_CCM_CCGRx_CG11_MASK (0x3 << 22) 461#define MXC_CCM_CCGRx_CG10_MASK (0x3 << 20) 462#define MXC_CCM_CCGRx_CG9_MASK (0x3 << 18) 463#define MXC_CCM_CCGRx_CG8_MASK (0x3 << 16) 464#define MXC_CCM_CCGRx_CG5_MASK (0x3 << 10) 465#define MXC_CCM_CCGRx_CG4_MASK (0x3 << 8) 466#define MXC_CCM_CCGRx_CG3_MASK (0x3 << 6) 467#define MXC_CCM_CCGRx_CG2_MASK (0x3 << 4) 468#define MXC_CCM_CCGRx_CG1_MASK (0x3 << 2) 469#define MXC_CCM_CCGRx_CG0_MASK (0x3 << 0) 470 471#define MXC_CCM_CCGRx_CG15_OFFSET 30 472#define MXC_CCM_CCGRx_CG14_OFFSET 28 473#define MXC_CCM_CCGRx_CG13_OFFSET 26 474#define MXC_CCM_CCGRx_CG12_OFFSET 24 475#define MXC_CCM_CCGRx_CG11_OFFSET 22 476#define MXC_CCM_CCGRx_CG10_OFFSET 20 477#define MXC_CCM_CCGRx_CG9_OFFSET 18 478#define MXC_CCM_CCGRx_CG8_OFFSET 16 479#define MXC_CCM_CCGRx_CG7_OFFSET 14 480#define MXC_CCM_CCGRx_CG6_OFFSET 12 481#define MXC_CCM_CCGRx_CG5_OFFSET 10 482#define MXC_CCM_CCGRx_CG4_OFFSET 8 483#define MXC_CCM_CCGRx_CG3_OFFSET 6 484#define MXC_CCM_CCGRx_CG2_OFFSET 4 485#define MXC_CCM_CCGRx_CG1_OFFSET 2 486#define MXC_CCM_CCGRx_CG0_OFFSET 0 487 488#define MXC_DPTC_LP_BASE (MX51_GPC_BASE + 0x80) 489#define MXC_DPTC_GP_BASE (MX51_GPC_BASE + 0x100) 490#define MXC_DVFS_CORE_BASE (MX51_GPC_BASE + 0x180) 491#define MXC_DPTC_PER_BASE (MX51_GPC_BASE + 0x1C0) 492#define MXC_PGC_IPU_BASE (MX51_GPC_BASE + 0x220) 493#define MXC_PGC_VPU_BASE (MX51_GPC_BASE + 0x240) 494#define MXC_PGC_GPU_BASE (MX51_GPC_BASE + 0x260) 495#define MXC_SRPG_NEON_BASE (MX51_GPC_BASE + 0x280) 496#define MXC_SRPG_ARM_BASE (MX51_GPC_BASE + 0x2A0) 497#define MXC_SRPG_EMPGC0_BASE (MX51_GPC_BASE + 0x2C0) 498#define MXC_SRPG_EMPGC1_BASE (MX51_GPC_BASE + 0x2D0) 499#define MXC_SRPG_MEGAMIX_BASE (MX51_GPC_BASE + 0x2E0) 500#define MXC_SRPG_EMI_BASE (MX51_GPC_BASE + 0x300) 501 502/* CORTEXA8 platform */ 503#define MXC_CORTEXA8_PLAT_PVID (MX51_CORTEXA8_BASE + 0x0) 504#define MXC_CORTEXA8_PLAT_GPC (MX51_CORTEXA8_BASE + 0x4) 505#define MXC_CORTEXA8_PLAT_PIC (MX51_CORTEXA8_BASE + 0x8) 506#define MXC_CORTEXA8_PLAT_LPC (MX51_CORTEXA8_BASE + 0xC) 507#define MXC_CORTEXA8_PLAT_NEON_LPC (MX51_CORTEXA8_BASE + 0x10) 508#define MXC_CORTEXA8_PLAT_ICGC (MX51_CORTEXA8_BASE + 0x14) 509#define MXC_CORTEXA8_PLAT_AMC (MX51_CORTEXA8_BASE + 0x18) 510#define MXC_CORTEXA8_PLAT_NMC (MX51_CORTEXA8_BASE + 0x20) 511#define MXC_CORTEXA8_PLAT_NMS (MX51_CORTEXA8_BASE + 0x24) 512 513/* DVFS CORE */ 514#define MXC_DVFSTHRS (MXC_DVFS_CORE_BASE + 0x00) 515#define MXC_DVFSCOUN (MXC_DVFS_CORE_BASE + 0x04) 516#define MXC_DVFSSIG1 (MXC_DVFS_CORE_BASE + 0x08) 517#define MXC_DVFSSIG0 (MXC_DVFS_CORE_BASE + 0x0C) 518#define MXC_DVFSGPC0 (MXC_DVFS_CORE_BASE + 0x10) 519#define MXC_DVFSGPC1 (MXC_DVFS_CORE_BASE + 0x14) 520#define MXC_DVFSGPBT (MXC_DVFS_CORE_BASE + 0x18) 521#define MXC_DVFSEMAC (MXC_DVFS_CORE_BASE + 0x1C) 522#define MXC_DVFSCNTR (MXC_DVFS_CORE_BASE + 0x20) 523#define MXC_DVFSLTR0_0 (MXC_DVFS_CORE_BASE + 0x24) 524#define MXC_DVFSLTR0_1 (MXC_DVFS_CORE_BASE + 0x28) 525#define MXC_DVFSLTR1_0 (MXC_DVFS_CORE_BASE + 0x2C) 526#define MXC_DVFSLTR1_1 (MXC_DVFS_CORE_BASE + 0x30) 527#define MXC_DVFSPT0 (MXC_DVFS_CORE_BASE + 0x34) 528#define MXC_DVFSPT1 (MXC_DVFS_CORE_BASE + 0x38) 529#define MXC_DVFSPT2 (MXC_DVFS_CORE_BASE + 0x3C) 530#define MXC_DVFSPT3 (MXC_DVFS_CORE_BASE + 0x40) 531 532/* GPC */ 533#define MXC_GPC_CNTR (MX51_GPC_BASE + 0x0) 534#define MXC_GPC_PGR (MX51_GPC_BASE + 0x4) 535#define MXC_GPC_VCR (MX51_GPC_BASE + 0x8) 536#define MXC_GPC_ALL_PU (MX51_GPC_BASE + 0xC) 537#define MXC_GPC_NEON (MX51_GPC_BASE + 0x10) 538#define MXC_GPC_PGR_ARMPG_OFFSET 8 539#define MXC_GPC_PGR_ARMPG_MASK (3 << 8) 540 541/* PGC */ 542#define MXC_PGC_IPU_PGCR (MXC_PGC_IPU_BASE + 0x0) 543#define MXC_PGC_IPU_PGSR (MXC_PGC_IPU_BASE + 0xC) 544#define MXC_PGC_VPU_PGCR (MXC_PGC_VPU_BASE + 0x0) 545#define MXC_PGC_VPU_PGSR (MXC_PGC_VPU_BASE + 0xC) 546#define MXC_PGC_GPU_PGCR (MXC_PGC_GPU_BASE + 0x0) 547#define MXC_PGC_GPU_PGSR (MXC_PGC_GPU_BASE + 0xC) 548 549#define MXC_PGCR_PCR 1 550#define MXC_SRPGCR_PCR 1 551#define MXC_EMPGCR_PCR 1 552#define MXC_PGSR_PSR 1 553 554 555#define MXC_CORTEXA8_PLAT_LPC_DSM (1 << 0) 556#define MXC_CORTEXA8_PLAT_LPC_DBG_DSM (1 << 1) 557 558/* SRPG */ 559#define MXC_SRPG_NEON_SRPGCR (MXC_SRPG_NEON_BASE + 0x0) 560#define MXC_SRPG_NEON_PUPSCR (MXC_SRPG_NEON_BASE + 0x4) 561#define MXC_SRPG_NEON_PDNSCR (MXC_SRPG_NEON_BASE + 0x8) 562 563#define MXC_SRPG_ARM_SRPGCR (MXC_SRPG_ARM_BASE + 0x0) 564#define MXC_SRPG_ARM_PUPSCR (MXC_SRPG_ARM_BASE + 0x4) 565#define MXC_SRPG_ARM_PDNSCR (MXC_SRPG_ARM_BASE + 0x8) 566 567#define MXC_SRPG_EMPGC0_SRPGCR (MXC_SRPG_EMPGC0_BASE + 0x0) 568#define MXC_SRPG_EMPGC0_PUPSCR (MXC_SRPG_EMPGC0_BASE + 0x4) 569#define MXC_SRPG_EMPGC0_PDNSCR (MXC_SRPG_EMPGC0_BASE + 0x8) 570 571#define MXC_SRPG_EMPGC1_SRPGCR (MXC_SRPG_EMPGC1_BASE + 0x0) 572#define MXC_SRPG_EMPGC1_PUPSCR (MXC_SRPG_EMPGC1_BASE + 0x4) 573#define MXC_SRPG_EMPGC1_PDNSCR (MXC_SRPG_EMPGC1_BASE + 0x8) 574 575#define MXC_SRPG_MEGAMIX_SRPGCR (MXC_SRPG_MEGAMIX_BASE + 0x0) 576#define MXC_SRPG_MEGAMIX_PUPSCR (MXC_SRPG_MEGAMIX_BASE + 0x4) 577#define MXC_SRPG_MEGAMIX_PDNSCR (MXC_SRPG_MEGAMIX_BASE + 0x8) 578 579#define MXC_SRPGC_EMI_SRPGCR (MXC_SRPGC_EMI_BASE + 0x0) 580#define MXC_SRPGC_EMI_PUPSCR (MXC_SRPGC_EMI_BASE + 0x4) 581#define MXC_SRPGC_EMI_PDNSCR (MXC_SRPGC_EMI_BASE + 0x8) 582 583#endif /* __ARCH_ARM_MACH_MX51_CRM_REGS_H__ */ 584