1/* 2 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. 3 * Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de> 4 * 5 * This program is free software; you can redistribute it and/or 6 * modify it under the terms of the GNU General Public License 7 * as published by the Free Software Foundation; either version 2 8 * of the License, or (at your option) any later version. 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, write to the Free Software 16 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, 17 * MA 02110-1301, USA. 18 */ 19 20#ifndef __ARCH_ARM_MACH_MX3_CRM_REGS_H__ 21#define __ARCH_ARM_MACH_MX3_CRM_REGS_H__ 22 23#define CKIH_CLK_FREQ 26000000 24#define CKIH_CLK_FREQ_27MHZ 27000000 25#define CKIL_CLK_FREQ 32768 26 27#define MXC_CCM_BASE MX31_IO_ADDRESS(MX31_CCM_BASE_ADDR) 28 29/* Register addresses */ 30#define MXC_CCM_CCMR (MXC_CCM_BASE + 0x00) 31#define MXC_CCM_PDR0 (MXC_CCM_BASE + 0x04) 32#define MXC_CCM_PDR1 (MXC_CCM_BASE + 0x08) 33#define MXC_CCM_RCSR (MXC_CCM_BASE + 0x0C) 34#define MXC_CCM_MPCTL (MXC_CCM_BASE + 0x10) 35#define MXC_CCM_UPCTL (MXC_CCM_BASE + 0x14) 36#define MXC_CCM_SRPCTL (MXC_CCM_BASE + 0x18) 37#define MXC_CCM_COSR (MXC_CCM_BASE + 0x1C) 38#define MXC_CCM_CGR0 (MXC_CCM_BASE + 0x20) 39#define MXC_CCM_CGR1 (MXC_CCM_BASE + 0x24) 40#define MXC_CCM_CGR2 (MXC_CCM_BASE + 0x28) 41#define MXC_CCM_WIMR (MXC_CCM_BASE + 0x2C) 42#define MXC_CCM_LDC (MXC_CCM_BASE + 0x30) 43#define MXC_CCM_DCVR0 (MXC_CCM_BASE + 0x34) 44#define MXC_CCM_DCVR1 (MXC_CCM_BASE + 0x38) 45#define MXC_CCM_DCVR2 (MXC_CCM_BASE + 0x3C) 46#define MXC_CCM_DCVR3 (MXC_CCM_BASE + 0x40) 47#define MXC_CCM_LTR0 (MXC_CCM_BASE + 0x44) 48#define MXC_CCM_LTR1 (MXC_CCM_BASE + 0x48) 49#define MXC_CCM_LTR2 (MXC_CCM_BASE + 0x4C) 50#define MXC_CCM_LTR3 (MXC_CCM_BASE + 0x50) 51#define MXC_CCM_LTBR0 (MXC_CCM_BASE + 0x54) 52#define MXC_CCM_LTBR1 (MXC_CCM_BASE + 0x58) 53#define MXC_CCM_PMCR0 (MXC_CCM_BASE + 0x5C) 54#define MXC_CCM_PMCR1 (MXC_CCM_BASE + 0x60) 55#define MXC_CCM_PDR2 (MXC_CCM_BASE + 0x64) 56 57/* Register bit definitions */ 58#define MXC_CCM_CCMR_WBEN (1 << 27) 59#define MXC_CCM_CCMR_CSCS (1 << 25) 60#define MXC_CCM_CCMR_PERCS (1 << 24) 61#define MXC_CCM_CCMR_SSI1S_OFFSET 18 62#define MXC_CCM_CCMR_SSI1S_MASK (0x3 << 18) 63#define MXC_CCM_CCMR_SSI2S_OFFSET 21 64#define MXC_CCM_CCMR_SSI2S_MASK (0x3 << 21) 65#define MXC_CCM_CCMR_LPM_OFFSET 14 66#define MXC_CCM_CCMR_LPM_MASK (0x3 << 14) 67#define MXC_CCM_CCMR_FIRS_OFFSET 11 68#define MXC_CCM_CCMR_FIRS_MASK (0x3 << 11) 69#define MXC_CCM_CCMR_UPE (1 << 9) 70#define MXC_CCM_CCMR_SPE (1 << 8) 71#define MXC_CCM_CCMR_MDS (1 << 7) 72#define MXC_CCM_CCMR_SBYCS (1 << 4) 73#define MXC_CCM_CCMR_MPE (1 << 3) 74#define MXC_CCM_CCMR_PRCS_OFFSET 1 75#define MXC_CCM_CCMR_PRCS_MASK (0x3 << 1) 76 77#define MXC_CCM_PDR0_CSI_PODF_OFFSET 26 78#define MXC_CCM_PDR0_CSI_PODF_MASK (0x3F << 26) 79#define MXC_CCM_PDR0_CSI_PRDF_OFFSET 23 80#define MXC_CCM_PDR0_CSI_PRDF_MASK (0x7 << 23) 81#define MXC_CCM_PDR0_PER_PODF_OFFSET 16 82#define MXC_CCM_PDR0_PER_PODF_MASK (0x1F << 16) 83#define MXC_CCM_PDR0_HSP_PODF_OFFSET 11 84#define MXC_CCM_PDR0_HSP_PODF_MASK (0x7 << 11) 85#define MXC_CCM_PDR0_NFC_PODF_OFFSET 8 86#define MXC_CCM_PDR0_NFC_PODF_MASK (0x7 << 8) 87#define MXC_CCM_PDR0_IPG_PODF_OFFSET 6 88#define MXC_CCM_PDR0_IPG_PODF_MASK (0x3 << 6) 89#define MXC_CCM_PDR0_MAX_PODF_OFFSET 3 90#define MXC_CCM_PDR0_MAX_PODF_MASK (0x7 << 3) 91#define MXC_CCM_PDR0_MCU_PODF_OFFSET 0 92#define MXC_CCM_PDR0_MCU_PODF_MASK 0x7 93 94#define MXC_CCM_PDR1_USB_PRDF_OFFSET 30 95#define MXC_CCM_PDR1_USB_PRDF_MASK (0x3 << 30) 96#define MXC_CCM_PDR1_USB_PODF_OFFSET 27 97#define MXC_CCM_PDR1_USB_PODF_MASK (0x7 << 27) 98#define MXC_CCM_PDR1_FIRI_PRE_PODF_OFFSET 24 99#define MXC_CCM_PDR1_FIRI_PRE_PODF_MASK (0x7 << 24) 100#define MXC_CCM_PDR1_FIRI_PODF_OFFSET 18 101#define MXC_CCM_PDR1_FIRI_PODF_MASK (0x3F << 18) 102#define MXC_CCM_PDR1_SSI2_PRE_PODF_OFFSET 15 103#define MXC_CCM_PDR1_SSI2_PRE_PODF_MASK (0x7 << 15) 104#define MXC_CCM_PDR1_SSI2_PODF_OFFSET 9 105#define MXC_CCM_PDR1_SSI2_PODF_MASK (0x3F << 9) 106#define MXC_CCM_PDR1_SSI1_PRE_PODF_OFFSET 6 107#define MXC_CCM_PDR1_SSI1_PRE_PODF_MASK (0x7 << 6) 108#define MXC_CCM_PDR1_SSI1_PODF_OFFSET 0 109#define MXC_CCM_PDR1_SSI1_PODF_MASK 0x3F 110 111/* Bit definitions for RCSR */ 112#define MXC_CCM_RCSR_NF16B 0x80000000 113 114/* 115 * LTR0 register offsets 116 */ 117#define MXC_CCM_LTR0_DIV3CK_OFFSET 1 118#define MXC_CCM_LTR0_DIV3CK_MASK (0x3 << 1) 119#define MXC_CCM_LTR0_DNTHR_OFFSET 16 120#define MXC_CCM_LTR0_DNTHR_MASK (0x3F << 16) 121#define MXC_CCM_LTR0_UPTHR_OFFSET 22 122#define MXC_CCM_LTR0_UPTHR_MASK (0x3F << 22) 123 124/* 125 * LTR1 register offsets 126 */ 127#define MXC_CCM_LTR1_PNCTHR_OFFSET 0 128#define MXC_CCM_LTR1_PNCTHR_MASK 0x3F 129#define MXC_CCM_LTR1_UPCNT_OFFSET 6 130#define MXC_CCM_LTR1_UPCNT_MASK (0xFF << 6) 131#define MXC_CCM_LTR1_DNCNT_OFFSET 14 132#define MXC_CCM_LTR1_DNCNT_MASK (0xFF << 14) 133#define MXC_CCM_LTR1_LTBRSR_MASK 0x400000 134#define MXC_CCM_LTR1_LTBRSR_OFFSET 22 135#define MXC_CCM_LTR1_LTBRSR 0x400000 136#define MXC_CCM_LTR1_LTBRSH 0x800000 137 138/* 139 * LTR2 bit definitions. x ranges from 0 for WSW9 to 6 for WSW15 140 */ 141#define MXC_CCM_LTR2_WSW_OFFSET(x) (11 + (x) * 3) 142#define MXC_CCM_LTR2_WSW_MASK(x) (0x7 << \ 143 MXC_CCM_LTR2_WSW_OFFSET((x))) 144#define MXC_CCM_LTR2_EMAC_OFFSET 0 145#define MXC_CCM_LTR2_EMAC_MASK 0x1FF 146 147/* 148 * LTR3 bit definitions. x ranges from 0 for WSW0 to 8 for WSW8 149 */ 150#define MXC_CCM_LTR3_WSW_OFFSET(x) (5 + (x) * 3) 151#define MXC_CCM_LTR3_WSW_MASK(x) (0x7 << \ 152 MXC_CCM_LTR3_WSW_OFFSET((x))) 153 154#define MXC_CCM_PMCR0_DFSUP1 0x80000000 155#define MXC_CCM_PMCR0_DFSUP1_SPLL (0 << 31) 156#define MXC_CCM_PMCR0_DFSUP1_MPLL (1 << 31) 157#define MXC_CCM_PMCR0_DFSUP0 0x40000000 158#define MXC_CCM_PMCR0_DFSUP0_PLL (0 << 30) 159#define MXC_CCM_PMCR0_DFSUP0_PDR (1 << 30) 160#define MXC_CCM_PMCR0_DFSUP_MASK (0x3 << 30) 161 162#define DVSUP_TURBO 0 163#define DVSUP_HIGH 1 164#define DVSUP_MEDIUM 2 165#define DVSUP_LOW 3 166#define MXC_CCM_PMCR0_DVSUP_TURBO (DVSUP_TURBO << 28) 167#define MXC_CCM_PMCR0_DVSUP_HIGH (DVSUP_HIGH << 28) 168#define MXC_CCM_PMCR0_DVSUP_MEDIUM (DVSUP_MEDIUM << 28) 169#define MXC_CCM_PMCR0_DVSUP_LOW (DVSUP_LOW << 28) 170#define MXC_CCM_PMCR0_DVSUP_OFFSET 28 171#define MXC_CCM_PMCR0_DVSUP_MASK (0x3 << 28) 172#define MXC_CCM_PMCR0_UDSC 0x08000000 173#define MXC_CCM_PMCR0_UDSC_MASK (1 << 27) 174#define MXC_CCM_PMCR0_UDSC_UP (1 << 27) 175#define MXC_CCM_PMCR0_UDSC_DOWN (0 << 27) 176 177#define MXC_CCM_PMCR0_VSCNT_1 (0x0 << 24) 178#define MXC_CCM_PMCR0_VSCNT_2 (0x1 << 24) 179#define MXC_CCM_PMCR0_VSCNT_3 (0x2 << 24) 180#define MXC_CCM_PMCR0_VSCNT_4 (0x3 << 24) 181#define MXC_CCM_PMCR0_VSCNT_5 (0x4 << 24) 182#define MXC_CCM_PMCR0_VSCNT_6 (0x5 << 24) 183#define MXC_CCM_PMCR0_VSCNT_7 (0x6 << 24) 184#define MXC_CCM_PMCR0_VSCNT_8 (0x7 << 24) 185#define MXC_CCM_PMCR0_VSCNT_OFFSET 24 186#define MXC_CCM_PMCR0_VSCNT_MASK (0x7 << 24) 187#define MXC_CCM_PMCR0_DVFEV 0x00800000 188#define MXC_CCM_PMCR0_DVFIS 0x00400000 189#define MXC_CCM_PMCR0_LBMI 0x00200000 190#define MXC_CCM_PMCR0_LBFL 0x00100000 191#define MXC_CCM_PMCR0_LBCF_4 (0x0 << 18) 192#define MXC_CCM_PMCR0_LBCF_8 (0x1 << 18) 193#define MXC_CCM_PMCR0_LBCF_12 (0x2 << 18) 194#define MXC_CCM_PMCR0_LBCF_16 (0x3 << 18) 195#define MXC_CCM_PMCR0_LBCF_OFFSET 18 196#define MXC_CCM_PMCR0_LBCF_MASK (0x3 << 18) 197#define MXC_CCM_PMCR0_PTVIS 0x00020000 198#define MXC_CCM_PMCR0_UPDTEN 0x00010000 199#define MXC_CCM_PMCR0_UPDTEN_MASK (0x1 << 16) 200#define MXC_CCM_PMCR0_FSVAIM 0x00008000 201#define MXC_CCM_PMCR0_FSVAI_OFFSET 13 202#define MXC_CCM_PMCR0_FSVAI_MASK (0x3 << 13) 203#define MXC_CCM_PMCR0_DPVCR 0x00001000 204#define MXC_CCM_PMCR0_DPVV 0x00000800 205#define MXC_CCM_PMCR0_WFIM 0x00000400 206#define MXC_CCM_PMCR0_DRCE3 0x00000200 207#define MXC_CCM_PMCR0_DRCE2 0x00000100 208#define MXC_CCM_PMCR0_DRCE1 0x00000080 209#define MXC_CCM_PMCR0_DRCE0 0x00000040 210#define MXC_CCM_PMCR0_DCR 0x00000020 211#define MXC_CCM_PMCR0_DVFEN 0x00000010 212#define MXC_CCM_PMCR0_PTVAIM 0x00000008 213#define MXC_CCM_PMCR0_PTVAI_OFFSET 1 214#define MXC_CCM_PMCR0_PTVAI_MASK (0x3 << 1) 215#define MXC_CCM_PMCR0_DPTEN 0x00000001 216 217#define MXC_CCM_PMCR1_DVGP_OFFSET 0 218#define MXC_CCM_PMCR1_DVGP_MASK (0xF) 219 220#define MXC_CCM_PMCR1_PLLRDIS (0x1 << 7) 221#define MXC_CCM_PMCR1_EMIRQ_EN (0x1 << 8) 222 223#define MXC_CCM_DCVR_ULV_MASK (0x3FF << 22) 224#define MXC_CCM_DCVR_ULV_OFFSET 22 225#define MXC_CCM_DCVR_LLV_MASK (0x3FF << 12) 226#define MXC_CCM_DCVR_LLV_OFFSET 12 227#define MXC_CCM_DCVR_ELV_MASK (0x3FF << 2) 228#define MXC_CCM_DCVR_ELV_OFFSET 2 229 230#define MXC_CCM_PDR2_MST2_PDF_MASK (0x3F << 7) 231#define MXC_CCM_PDR2_MST2_PDF_OFFSET 7 232#define MXC_CCM_PDR2_MST1_PDF_MASK 0x3F 233#define MXC_CCM_PDR2_MST1_PDF_OFFSET 0 234 235#define MXC_CCM_COSR_CLKOSEL_MASK 0x0F 236#define MXC_CCM_COSR_CLKOSEL_OFFSET 0 237#define MXC_CCM_COSR_CLKOUTDIV_MASK (0x07 << 6) 238#define MXC_CCM_COSR_CLKOUTDIV_OFFSET 6 239#define MXC_CCM_COSR_CLKOEN (1 << 9) 240 241/* 242 * PMCR0 register offsets 243 */ 244#define MXC_CCM_PMCR0_LBFL_OFFSET 20 245#define MXC_CCM_PMCR0_DFSUP0_OFFSET 30 246#define MXC_CCM_PMCR0_DFSUP1_OFFSET 31 247 248#endif /* __ARCH_ARM_MACH_MX3_CRM_REGS_H__ */ 249