1/* 2 * arch/arm/mach-mv78xx0/include/mach/mv78xx0.h 3 * 4 * Generic definitions for Marvell MV78xx0 SoC flavors: 5 * MV781x0 and MV782x0. 6 * 7 * This file is licensed under the terms of the GNU General Public 8 * License version 2. This program is licensed "as is" without any 9 * warranty of any kind, whether express or implied. 10 */ 11 12#ifndef __ASM_ARCH_MV78XX0_H 13#define __ASM_ARCH_MV78XX0_H 14 15/* 16 * Marvell MV78xx0 address maps. 17 * 18 * phys 19 * c0000000 PCIe Memory space 20 * f0800000 PCIe #0 I/O space 21 * f0900000 PCIe #1 I/O space 22 * f0a00000 PCIe #2 I/O space 23 * f0b00000 PCIe #3 I/O space 24 * f0c00000 PCIe #4 I/O space 25 * f0d00000 PCIe #5 I/O space 26 * f0e00000 PCIe #6 I/O space 27 * f0f00000 PCIe #7 I/O space 28 * f1000000 on-chip peripheral registers 29 * 30 * virt phys size 31 * fe400000 f102x000 16K core-specific peripheral registers 32 * fe700000 f0800000 1M PCIe #0 I/O space 33 * fe800000 f0900000 1M PCIe #1 I/O space 34 * fe900000 f0a00000 1M PCIe #2 I/O space 35 * fea00000 f0b00000 1M PCIe #3 I/O space 36 * feb00000 f0c00000 1M PCIe #4 I/O space 37 * fec00000 f0d00000 1M PCIe #5 I/O space 38 * fed00000 f0e00000 1M PCIe #6 I/O space 39 * fee00000 f0f00000 1M PCIe #7 I/O space 40 * fef00000 f1000000 1M on-chip peripheral registers 41 */ 42#define MV78XX0_CORE0_REGS_PHYS_BASE 0xf1020000 43#define MV78XX0_CORE1_REGS_PHYS_BASE 0xf1024000 44#define MV78XX0_CORE_REGS_VIRT_BASE 0xfe400000 45#define MV78XX0_CORE_REGS_SIZE SZ_16K 46 47#define MV78XX0_PCIE_IO_PHYS_BASE(i) (0xf0800000 + ((i) << 20)) 48#define MV78XX0_PCIE_IO_VIRT_BASE(i) (0xfe700000 + ((i) << 20)) 49#define MV78XX0_PCIE_IO_SIZE SZ_1M 50 51#define MV78XX0_REGS_PHYS_BASE 0xf1000000 52#define MV78XX0_REGS_VIRT_BASE 0xfef00000 53#define MV78XX0_REGS_SIZE SZ_1M 54 55#define MV78XX0_PCIE_MEM_PHYS_BASE 0xc0000000 56#define MV78XX0_PCIE_MEM_SIZE 0x30000000 57 58/* 59 * Core-specific peripheral registers. 60 */ 61#define BRIDGE_VIRT_BASE (MV78XX0_CORE_REGS_VIRT_BASE) 62 63/* 64 * Register Map 65 */ 66#define DDR_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x00000) 67#define DDR_WINDOW_CPU0_BASE (DDR_VIRT_BASE | 0x1500) 68#define DDR_WINDOW_CPU1_BASE (DDR_VIRT_BASE | 0x1700) 69 70#define DEV_BUS_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0x10000) 71#define DEV_BUS_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x10000) 72#define SAMPLE_AT_RESET_LOW (DEV_BUS_VIRT_BASE | 0x0030) 73#define SAMPLE_AT_RESET_HIGH (DEV_BUS_VIRT_BASE | 0x0034) 74#define I2C_0_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x1000) 75#define I2C_1_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x1100) 76#define UART0_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x2000) 77#define UART0_VIRT_BASE (DEV_BUS_VIRT_BASE | 0x2000) 78#define UART1_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x2100) 79#define UART1_VIRT_BASE (DEV_BUS_VIRT_BASE | 0x2100) 80#define UART2_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x2200) 81#define UART2_VIRT_BASE (DEV_BUS_VIRT_BASE | 0x2200) 82#define UART3_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x2300) 83#define UART3_VIRT_BASE (DEV_BUS_VIRT_BASE | 0x2300) 84 85#define GE10_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0x30000) 86#define GE11_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0x34000) 87 88#define PCIE00_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x40000) 89#define PCIE01_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x44000) 90#define PCIE02_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x48000) 91#define PCIE03_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x4c000) 92 93#define USB0_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0x50000) 94#define USB1_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0x51000) 95#define USB2_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0x52000) 96 97#define GE00_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0x70000) 98#define GE01_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0x74000) 99 100#define PCIE10_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x80000) 101#define PCIE11_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x84000) 102#define PCIE12_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x88000) 103#define PCIE13_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x8c000) 104 105#define SATA_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0xa0000) 106 107/* 108 * Supported devices and revisions. 109 */ 110#define MV78X00_Z0_DEV_ID 0x6381 111#define MV78X00_REV_Z0 1 112 113#define MV78100_DEV_ID 0x7810 114#define MV78100_REV_A0 1 115#define MV78100_REV_A1 2 116 117#define MV78200_DEV_ID 0x7820 118#define MV78200_REV_A0 1 119 120#endif 121