1/* 2 * linux/arch/arm/mach-mmp/pxa910.c 3 * 4 * Code specific to PXA910 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 */ 10 11#include <linux/module.h> 12#include <linux/kernel.h> 13#include <linux/init.h> 14#include <linux/list.h> 15#include <linux/io.h> 16 17#include <asm/mach/time.h> 18#include <mach/addr-map.h> 19#include <mach/regs-apbc.h> 20#include <mach/regs-apmu.h> 21#include <mach/cputype.h> 22#include <mach/irqs.h> 23#include <mach/gpio.h> 24#include <mach/dma.h> 25#include <mach/mfp.h> 26#include <mach/devices.h> 27 28#include "common.h" 29#include "clock.h" 30 31#define MFPR_VIRT_BASE (APB_VIRT_BASE + 0x1e000) 32 33static struct mfp_addr_map pxa910_mfp_addr_map[] __initdata = 34{ 35 MFP_ADDR_X(GPIO0, GPIO54, 0xdc), 36 MFP_ADDR_X(GPIO67, GPIO98, 0x1b8), 37 MFP_ADDR_X(GPIO100, GPIO109, 0x238), 38 39 MFP_ADDR(GPIO123, 0xcc), 40 MFP_ADDR(GPIO124, 0xd0), 41 42 MFP_ADDR(DF_IO0, 0x40), 43 MFP_ADDR(DF_IO1, 0x3c), 44 MFP_ADDR(DF_IO2, 0x38), 45 MFP_ADDR(DF_IO3, 0x34), 46 MFP_ADDR(DF_IO4, 0x30), 47 MFP_ADDR(DF_IO5, 0x2c), 48 MFP_ADDR(DF_IO6, 0x28), 49 MFP_ADDR(DF_IO7, 0x24), 50 MFP_ADDR(DF_IO8, 0x20), 51 MFP_ADDR(DF_IO9, 0x1c), 52 MFP_ADDR(DF_IO10, 0x18), 53 MFP_ADDR(DF_IO11, 0x14), 54 MFP_ADDR(DF_IO12, 0x10), 55 MFP_ADDR(DF_IO13, 0xc), 56 MFP_ADDR(DF_IO14, 0x8), 57 MFP_ADDR(DF_IO15, 0x4), 58 59 MFP_ADDR(DF_nCS0_SM_nCS2, 0x44), 60 MFP_ADDR(DF_nCS1_SM_nCS3, 0x48), 61 MFP_ADDR(SM_nCS0, 0x4c), 62 MFP_ADDR(SM_nCS1, 0x50), 63 MFP_ADDR(DF_WEn, 0x54), 64 MFP_ADDR(DF_REn, 0x58), 65 MFP_ADDR(DF_CLE_SM_OEn, 0x5c), 66 MFP_ADDR(DF_ALE_SM_WEn, 0x60), 67 MFP_ADDR(SM_SCLK, 0x64), 68 MFP_ADDR(DF_RDY0, 0x68), 69 MFP_ADDR(SM_BE0, 0x6c), 70 MFP_ADDR(SM_BE1, 0x70), 71 MFP_ADDR(SM_ADV, 0x74), 72 MFP_ADDR(DF_RDY1, 0x78), 73 MFP_ADDR(SM_ADVMUX, 0x7c), 74 MFP_ADDR(SM_RDY, 0x80), 75 76 MFP_ADDR_X(MMC1_DAT7, MMC1_WP, 0x84), 77 78 MFP_ADDR_END, 79}; 80 81#define APMASK(i) (GPIO_REGS_VIRT + BANK_OFF(i) + 0x09c) 82 83static void __init pxa910_init_gpio(void) 84{ 85 int i; 86 87 /* enable GPIO clock */ 88 __raw_writel(APBC_APBCLK | APBC_FNCLK, APBC_PXA910_GPIO); 89 90 /* unmask GPIO edge detection for all 4 banks - APMASKx */ 91 for (i = 0; i < 4; i++) 92 __raw_writel(0xffffffff, APMASK(i)); 93 94 pxa_init_gpio(IRQ_PXA910_AP_GPIO, 0, 127, NULL); 95} 96 97void __init pxa910_init_irq(void) 98{ 99 icu_init_irq(); 100 pxa910_init_gpio(); 101} 102 103/* APB peripheral clocks */ 104static APBC_CLK(uart1, PXA910_UART0, 1, 14745600); 105static APBC_CLK(uart2, PXA910_UART1, 1, 14745600); 106static APBC_CLK(twsi0, PXA168_TWSI0, 1, 33000000); 107static APBC_CLK(twsi1, PXA168_TWSI1, 1, 33000000); 108static APBC_CLK(pwm1, PXA910_PWM1, 1, 13000000); 109static APBC_CLK(pwm2, PXA910_PWM2, 1, 13000000); 110static APBC_CLK(pwm3, PXA910_PWM3, 1, 13000000); 111static APBC_CLK(pwm4, PXA910_PWM4, 1, 13000000); 112 113static APMU_CLK(nand, NAND, 0x01db, 208000000); 114 115/* device and clock bindings */ 116static struct clk_lookup pxa910_clkregs[] = { 117 INIT_CLKREG(&clk_uart1, "pxa2xx-uart.0", NULL), 118 INIT_CLKREG(&clk_uart2, "pxa2xx-uart.1", NULL), 119 INIT_CLKREG(&clk_twsi0, "pxa2xx-i2c.0", NULL), 120 INIT_CLKREG(&clk_twsi1, "pxa2xx-i2c.1", NULL), 121 INIT_CLKREG(&clk_pwm1, "pxa910-pwm.0", NULL), 122 INIT_CLKREG(&clk_pwm2, "pxa910-pwm.1", NULL), 123 INIT_CLKREG(&clk_pwm3, "pxa910-pwm.2", NULL), 124 INIT_CLKREG(&clk_pwm4, "pxa910-pwm.3", NULL), 125 INIT_CLKREG(&clk_nand, "pxa3xx-nand", NULL), 126}; 127 128static int __init pxa910_init(void) 129{ 130 if (cpu_is_pxa910()) { 131 mfp_init_base(MFPR_VIRT_BASE); 132 mfp_init_addr(pxa910_mfp_addr_map); 133 pxa_init_dma(IRQ_PXA910_DMA_INT0, 32); 134 clkdev_add_table(ARRAY_AND_SIZE(pxa910_clkregs)); 135 } 136 137 return 0; 138} 139postcore_initcall(pxa910_init); 140 141/* system timer - clock enabled, 3.25MHz */ 142#define TIMER_CLK_RST (APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(3)) 143 144static void __init pxa910_timer_init(void) 145{ 146 /* reset and configure */ 147 __raw_writel(APBC_APBCLK | APBC_RST, APBC_PXA910_TIMERS); 148 __raw_writel(TIMER_CLK_RST, APBC_PXA910_TIMERS); 149 150 timer_init(IRQ_PXA910_AP1_TIMER1); 151} 152 153struct sys_timer pxa910_timer = { 154 .init = pxa910_timer_init, 155}; 156 157/* on-chip devices */ 158 159/* NOTE: there are totally 3 UARTs on PXA910: 160 * 161 * UART1 - Slow UART (can be used both by AP and CP) 162 * UART2/3 - Fast UART 163 * 164 * To be backward compatible with the legacy FFUART/BTUART/STUART sequence, 165 * they are re-ordered as: 166 * 167 * pxa910_device_uart1 - UART2 as FFUART 168 * pxa910_device_uart2 - UART3 as BTUART 169 * 170 * UART1 is not used by AP for the moment. 171 */ 172PXA910_DEVICE(uart1, "pxa2xx-uart", 0, UART2, 0xd4017000, 0x30, 21, 22); 173PXA910_DEVICE(uart2, "pxa2xx-uart", 1, UART3, 0xd4018000, 0x30, 23, 24); 174PXA910_DEVICE(twsi0, "pxa2xx-i2c", 0, TWSI0, 0xd4011000, 0x28); 175PXA910_DEVICE(twsi1, "pxa2xx-i2c", 1, TWSI1, 0xd4025000, 0x28); 176PXA910_DEVICE(pwm1, "pxa910-pwm", 0, NONE, 0xd401a000, 0x10); 177PXA910_DEVICE(pwm2, "pxa910-pwm", 1, NONE, 0xd401a400, 0x10); 178PXA910_DEVICE(pwm3, "pxa910-pwm", 2, NONE, 0xd401a800, 0x10); 179PXA910_DEVICE(pwm4, "pxa910-pwm", 3, NONE, 0xd401ac00, 0x10); 180PXA910_DEVICE(nand, "pxa3xx-nand", -1, NAND, 0xd4283000, 0x80, 97, 99); 181