1/* 2 * arch/arm/mach-kirkwood/pcie.c 3 * 4 * PCIe functions for Marvell Kirkwood SoCs 5 * 6 * This file is licensed under the terms of the GNU General Public 7 * License version 2. This program is licensed "as is" without any 8 * warranty of any kind, whether express or implied. 9 */ 10 11#include <linux/kernel.h> 12#include <linux/pci.h> 13#include <linux/slab.h> 14#include <linux/mbus.h> 15#include <asm/irq.h> 16#include <asm/mach/pci.h> 17#include <plat/pcie.h> 18#include <mach/bridge-regs.h> 19#include "common.h" 20 21void __init kirkwood_pcie_id(u32 *dev, u32 *rev) 22{ 23 *dev = orion_pcie_dev_id((void __iomem *)PCIE_VIRT_BASE); 24 *rev = orion_pcie_rev((void __iomem *)PCIE_VIRT_BASE); 25} 26 27struct pcie_port { 28 u8 root_bus_nr; 29 void __iomem *base; 30 spinlock_t conf_lock; 31 int irq; 32 struct resource res[2]; 33}; 34 35static int pcie_port_map[2]; 36static int num_pcie_ports; 37 38static inline struct pcie_port *bus_to_port(struct pci_bus *bus) 39{ 40 struct pci_sys_data *sys = bus->sysdata; 41 return sys->private_data; 42} 43 44static int pcie_valid_config(struct pcie_port *pp, int bus, int dev) 45{ 46 /* 47 * Don't go out when trying to access -- 48 * 1. nonexisting device on local bus 49 * 2. where there's no device connected (no link) 50 */ 51 if (bus == pp->root_bus_nr && dev == 0) 52 return 1; 53 54 if (!orion_pcie_link_up(pp->base)) 55 return 0; 56 57 if (bus == pp->root_bus_nr && dev != 1) 58 return 0; 59 60 return 1; 61} 62 63 64/* 65 * PCIe config cycles are done by programming the PCIE_CONF_ADDR register 66 * and then reading the PCIE_CONF_DATA register. Need to make sure these 67 * transactions are atomic. 68 */ 69 70static int pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where, 71 int size, u32 *val) 72{ 73 struct pcie_port *pp = bus_to_port(bus); 74 unsigned long flags; 75 int ret; 76 77 if (pcie_valid_config(pp, bus->number, PCI_SLOT(devfn)) == 0) { 78 *val = 0xffffffff; 79 return PCIBIOS_DEVICE_NOT_FOUND; 80 } 81 82 spin_lock_irqsave(&pp->conf_lock, flags); 83 ret = orion_pcie_rd_conf(pp->base, bus, devfn, where, size, val); 84 spin_unlock_irqrestore(&pp->conf_lock, flags); 85 86 return ret; 87} 88 89static int pcie_wr_conf(struct pci_bus *bus, u32 devfn, 90 int where, int size, u32 val) 91{ 92 struct pcie_port *pp = bus_to_port(bus); 93 unsigned long flags; 94 int ret; 95 96 if (pcie_valid_config(pp, bus->number, PCI_SLOT(devfn)) == 0) 97 return PCIBIOS_DEVICE_NOT_FOUND; 98 99 spin_lock_irqsave(&pp->conf_lock, flags); 100 ret = orion_pcie_wr_conf(pp->base, bus, devfn, where, size, val); 101 spin_unlock_irqrestore(&pp->conf_lock, flags); 102 103 return ret; 104} 105 106static struct pci_ops pcie_ops = { 107 .read = pcie_rd_conf, 108 .write = pcie_wr_conf, 109}; 110 111static void __init pcie0_ioresources_init(struct pcie_port *pp) 112{ 113 pp->base = (void __iomem *)PCIE_VIRT_BASE; 114 pp->irq = IRQ_KIRKWOOD_PCIE; 115 116 /* 117 * IORESOURCE_IO 118 */ 119 pp->res[0].name = "PCIe 0 I/O Space"; 120 pp->res[0].start = KIRKWOOD_PCIE_IO_BUS_BASE; 121 pp->res[0].end = pp->res[0].start + KIRKWOOD_PCIE_IO_SIZE - 1; 122 pp->res[0].flags = IORESOURCE_IO; 123 124 /* 125 * IORESOURCE_MEM 126 */ 127 pp->res[1].name = "PCIe 0 MEM"; 128 pp->res[1].start = KIRKWOOD_PCIE_MEM_PHYS_BASE; 129 pp->res[1].end = pp->res[1].start + KIRKWOOD_PCIE_MEM_SIZE - 1; 130 pp->res[1].flags = IORESOURCE_MEM; 131} 132 133static void __init pcie1_ioresources_init(struct pcie_port *pp) 134{ 135 pp->base = (void __iomem *)PCIE1_VIRT_BASE; 136 pp->irq = IRQ_KIRKWOOD_PCIE1; 137 138 /* 139 * IORESOURCE_IO 140 */ 141 pp->res[0].name = "PCIe 1 I/O Space"; 142 pp->res[0].start = KIRKWOOD_PCIE1_IO_BUS_BASE; 143 pp->res[0].end = pp->res[0].start + KIRKWOOD_PCIE1_IO_SIZE - 1; 144 pp->res[0].flags = IORESOURCE_IO; 145 146 /* 147 * IORESOURCE_MEM 148 */ 149 pp->res[1].name = "PCIe 1 MEM"; 150 pp->res[1].start = KIRKWOOD_PCIE1_MEM_PHYS_BASE; 151 pp->res[1].end = pp->res[1].start + KIRKWOOD_PCIE1_MEM_SIZE - 1; 152 pp->res[1].flags = IORESOURCE_MEM; 153} 154 155static int __init kirkwood_pcie_setup(int nr, struct pci_sys_data *sys) 156{ 157 extern unsigned int kirkwood_clk_ctrl; 158 struct pcie_port *pp; 159 int index; 160 161 if (nr >= num_pcie_ports) 162 return 0; 163 164 index = pcie_port_map[nr]; 165 printk(KERN_INFO "PCI: bus%d uses PCIe port %d\n", sys->busnr, index); 166 167 pp = kzalloc(sizeof(*pp), GFP_KERNEL); 168 if (!pp) 169 panic("PCIe: failed to allocate pcie_port data"); 170 sys->private_data = pp; 171 pp->root_bus_nr = sys->busnr; 172 spin_lock_init(&pp->conf_lock); 173 174 switch (index) { 175 case 0: 176 kirkwood_clk_ctrl |= CGC_PEX0; 177 pcie0_ioresources_init(pp); 178 break; 179 case 1: 180 kirkwood_clk_ctrl |= CGC_PEX1; 181 pcie1_ioresources_init(pp); 182 break; 183 default: 184 panic("PCIe setup: invalid controller %d", index); 185 } 186 187 if (request_resource(&ioport_resource, &pp->res[0])) 188 panic("Request PCIe%d IO resource failed\n", index); 189 if (request_resource(&iomem_resource, &pp->res[1])) 190 panic("Request PCIe%d Memory resource failed\n", index); 191 192 sys->resource[0] = &pp->res[0]; 193 sys->resource[1] = &pp->res[1]; 194 sys->resource[2] = NULL; 195 sys->io_offset = 0; 196 197 /* 198 * Generic PCIe unit setup. 199 */ 200 orion_pcie_set_local_bus_nr(pp->base, sys->busnr); 201 202 orion_pcie_setup(pp->base, &kirkwood_mbus_dram_info); 203 204 return 1; 205} 206 207static void __devinit rc_pci_fixup(struct pci_dev *dev) 208{ 209 /* 210 * Prevent enumeration of root complex. 211 */ 212 if (dev->bus->parent == NULL && dev->devfn == 0) { 213 int i; 214 215 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { 216 dev->resource[i].start = 0; 217 dev->resource[i].end = 0; 218 dev->resource[i].flags = 0; 219 } 220 } 221} 222DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL, PCI_ANY_ID, rc_pci_fixup); 223 224static struct pci_bus __init * 225kirkwood_pcie_scan_bus(int nr, struct pci_sys_data *sys) 226{ 227 struct pci_bus *bus; 228 229 if (nr < num_pcie_ports) { 230 bus = pci_scan_bus(sys->busnr, &pcie_ops, sys); 231 } else { 232 bus = NULL; 233 BUG(); 234 } 235 236 return bus; 237} 238 239static int __init kirkwood_pcie_map_irq(struct pci_dev *dev, u8 slot, u8 pin) 240{ 241 struct pcie_port *pp = bus_to_port(dev->bus); 242 243 return pp->irq; 244} 245 246static struct hw_pci kirkwood_pci __initdata = { 247 .swizzle = pci_std_swizzle, 248 .setup = kirkwood_pcie_setup, 249 .scan = kirkwood_pcie_scan_bus, 250 .map_irq = kirkwood_pcie_map_irq, 251}; 252 253static void __init add_pcie_port(int index, unsigned long base) 254{ 255 printk(KERN_INFO "Kirkwood PCIe port %d: ", index); 256 257 if (orion_pcie_link_up((void __iomem *)base)) { 258 printk(KERN_INFO "link up\n"); 259 pcie_port_map[num_pcie_ports++] = index; 260 } else 261 printk(KERN_INFO "link down, ignoring\n"); 262} 263 264void __init kirkwood_pcie_init(unsigned int portmask) 265{ 266 if (portmask & KW_PCIE0) 267 add_pcie_port(0, PCIE_VIRT_BASE); 268 269 if (portmask & KW_PCIE1) 270 add_pcie_port(1, PCIE1_VIRT_BASE); 271 272 kirkwood_pci.nr_controllers = num_pcie_ports; 273 pci_common_init(&kirkwood_pci); 274} 275