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  • only in /netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/arm/mach-footbridge/include/mach/
1/*
2 *  arch/arm/mach-footbridge/include/mach/memory.h
3 *
4 *  Copyright (C) 1996-1999 Russell King.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 *  Changelog:
11 *   20-Oct-1996 RMK	Created
12 *   31-Dec-1997 RMK	Fixed definitions to reduce warnings.
13 *   17-May-1998 DAG	Added __virt_to_bus and __bus_to_virt functions.
14 *   21-Nov-1998 RMK	Changed __virt_to_bus and __bus_to_virt to macros.
15 *   21-Mar-1999 RMK	Added PAGE_OFFSET for co285 architecture.
16 *			Renamed to memory.h
17 *			Moved PAGE_OFFSET and TASK_SIZE here
18 */
19#ifndef __ASM_ARCH_MEMORY_H
20#define __ASM_ARCH_MEMORY_H
21
22
23#if defined(CONFIG_FOOTBRIDGE_ADDIN)
24/*
25 * If we may be using add-in footbridge mode, then we must
26 * use the out-of-line translation that makes use of the
27 * PCI BAR
28 */
29#ifndef __ASSEMBLY__
30extern unsigned long __virt_to_bus(unsigned long);
31extern unsigned long __bus_to_virt(unsigned long);
32extern unsigned long __pfn_to_bus(unsigned long);
33extern unsigned long __bus_to_pfn(unsigned long);
34#endif
35#define __virt_to_bus	__virt_to_bus
36#define __bus_to_virt	__bus_to_virt
37
38#elif defined(CONFIG_FOOTBRIDGE_HOST)
39
40/*
41 * The footbridge is programmed to expose the system RAM at 0xe0000000.
42 * The requirement is that the RAM isn't placed at bus address 0, which
43 * would clash with VGA cards.
44 */
45#define BUS_OFFSET		0xe0000000
46#define __virt_to_bus(x)	((x) + (BUS_OFFSET - PAGE_OFFSET))
47#define __bus_to_virt(x)	((x) - (BUS_OFFSET - PAGE_OFFSET))
48#define __pfn_to_bus(x)		(__pfn_to_phys(x) + (BUS_OFFSET - PHYS_OFFSET))
49#define __bus_to_pfn(x)		__phys_to_pfn((x) - (BUS_OFFSET - PHYS_OFFSET))
50
51#else
52
53#error "Undefined footbridge mode"
54
55#endif
56
57/*
58 * Cache flushing area.
59 */
60#define FLUSH_BASE		0xf9000000
61
62/*
63 * Physical DRAM offset.
64 */
65#define PHYS_OFFSET		UL(0x00000000)
66
67#define FLUSH_BASE_PHYS		0x50000000
68
69#endif
70