1/* 2 * arch/arm/mach-dove/irq.c 3 * 4 * Dove IRQ handling. 5 * 6 * This file is licensed under the terms of the GNU General Public 7 * License version 2. This program is licensed "as is" without any 8 * warranty of any kind, whether express or implied. 9 */ 10 11#include <linux/kernel.h> 12#include <linux/init.h> 13#include <linux/irq.h> 14#include <linux/gpio.h> 15#include <linux/io.h> 16#include <asm/mach/arch.h> 17#include <plat/irq.h> 18#include <asm/mach/irq.h> 19#include <mach/pm.h> 20#include <mach/bridge-regs.h> 21#include "common.h" 22 23static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc) 24{ 25 int irqoff; 26 BUG_ON(irq < IRQ_DOVE_GPIO_0_7 || irq > IRQ_DOVE_HIGH_GPIO); 27 28 irqoff = irq <= IRQ_DOVE_GPIO_16_23 ? irq - IRQ_DOVE_GPIO_0_7 : 29 3 + irq - IRQ_DOVE_GPIO_24_31; 30 31 orion_gpio_irq_handler(irqoff << 3); 32 if (irq == IRQ_DOVE_HIGH_GPIO) { 33 orion_gpio_irq_handler(40); 34 orion_gpio_irq_handler(48); 35 orion_gpio_irq_handler(56); 36 } 37} 38 39static void pmu_irq_mask(unsigned int irq) 40{ 41 int pin = irq_to_pmu(irq); 42 u32 u; 43 44 u = readl(PMU_INTERRUPT_MASK); 45 u &= ~(1 << (pin & 31)); 46 writel(u, PMU_INTERRUPT_MASK); 47} 48 49static void pmu_irq_unmask(unsigned int irq) 50{ 51 int pin = irq_to_pmu(irq); 52 u32 u; 53 54 u = readl(PMU_INTERRUPT_MASK); 55 u |= 1 << (pin & 31); 56 writel(u, PMU_INTERRUPT_MASK); 57} 58 59static void pmu_irq_ack(unsigned int irq) 60{ 61 int pin = irq_to_pmu(irq); 62 u32 u; 63 64 u = ~(1 << (pin & 31)); 65 writel(u, PMU_INTERRUPT_CAUSE); 66} 67 68static struct irq_chip pmu_irq_chip = { 69 .name = "pmu_irq", 70 .mask = pmu_irq_mask, 71 .unmask = pmu_irq_unmask, 72 .ack = pmu_irq_ack, 73}; 74 75static void pmu_irq_handler(unsigned int irq, struct irq_desc *desc) 76{ 77 unsigned long cause = readl(PMU_INTERRUPT_CAUSE); 78 79 cause &= readl(PMU_INTERRUPT_MASK); 80 if (cause == 0) { 81 do_bad_IRQ(irq, desc); 82 return; 83 } 84 85 for (irq = 0; irq < NR_PMU_IRQS; irq++) { 86 if (!(cause & (1 << irq))) 87 continue; 88 irq = pmu_to_irq(irq); 89 desc = irq_desc + irq; 90 desc_handle_irq(irq, desc); 91 } 92} 93 94void __init dove_init_irq(void) 95{ 96 int i; 97 98 orion_irq_init(0, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF)); 99 orion_irq_init(32, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF)); 100 101 /* 102 * Mask and clear GPIO IRQ interrupts. 103 */ 104 writel(0, GPIO_LEVEL_MASK(0)); 105 writel(0, GPIO_EDGE_MASK(0)); 106 writel(0, GPIO_EDGE_CAUSE(0)); 107 108 /* 109 * Mask and clear PMU interrupts 110 */ 111 writel(0, PMU_INTERRUPT_MASK); 112 writel(0, PMU_INTERRUPT_CAUSE); 113 114 for (i = IRQ_DOVE_GPIO_START; i < IRQ_DOVE_PMU_START; i++) { 115 set_irq_chip(i, &orion_gpio_irq_chip); 116 set_irq_handler(i, handle_level_irq); 117 irq_desc[i].status |= IRQ_LEVEL; 118 set_irq_flags(i, IRQF_VALID); 119 } 120 set_irq_chained_handler(IRQ_DOVE_GPIO_0_7, gpio_irq_handler); 121 set_irq_chained_handler(IRQ_DOVE_GPIO_8_15, gpio_irq_handler); 122 set_irq_chained_handler(IRQ_DOVE_GPIO_16_23, gpio_irq_handler); 123 set_irq_chained_handler(IRQ_DOVE_GPIO_24_31, gpio_irq_handler); 124 set_irq_chained_handler(IRQ_DOVE_HIGH_GPIO, gpio_irq_handler); 125 126 for (i = IRQ_DOVE_PMU_START; i < NR_IRQS; i++) { 127 set_irq_chip(i, &pmu_irq_chip); 128 set_irq_handler(i, handle_level_irq); 129 irq_desc[i].status |= IRQ_LEVEL; 130 set_irq_flags(i, IRQF_VALID); 131 } 132 set_irq_chained_handler(IRQ_DOVE_PMU, pmu_irq_handler); 133} 134