1/* 2 * TI DaVinci DM644x chip specific setup 3 * 4 * Author: Kevin Hilman, Deep Root Systems, LLC 5 * 6 * 2007 (c) Deep Root Systems, LLC. This file is licensed under 7 * the terms of the GNU General Public License version 2. This program 8 * is licensed "as is" without any warranty of any kind, whether express 9 * or implied. 10 */ 11#include <linux/init.h> 12#include <linux/clk.h> 13#include <linux/serial_8250.h> 14#include <linux/platform_device.h> 15#include <linux/gpio.h> 16 17#include <asm/mach/map.h> 18 19#include <mach/dm646x.h> 20#include <mach/cputype.h> 21#include <mach/edma.h> 22#include <mach/irqs.h> 23#include <mach/psc.h> 24#include <mach/mux.h> 25#include <mach/time.h> 26#include <mach/serial.h> 27#include <mach/common.h> 28#include <mach/asp.h> 29 30#include "clock.h" 31#include "mux.h" 32 33#define DAVINCI_VPIF_BASE (0x01C12000) 34#define VDD3P3V_PWDN_OFFSET (0x48) 35#define VSCLKDIS_OFFSET (0x6C) 36 37#define VDD3P3V_VID_MASK (BIT_MASK(3) | BIT_MASK(2) | BIT_MASK(1) |\ 38 BIT_MASK(0)) 39#define VSCLKDIS_MASK (BIT_MASK(11) | BIT_MASK(10) | BIT_MASK(9) |\ 40 BIT_MASK(8)) 41 42/* 43 * Device specific clocks 44 */ 45#define DM646X_AUX_FREQ 24000000 46 47static struct pll_data pll1_data = { 48 .num = 1, 49 .phys_base = DAVINCI_PLL1_BASE, 50}; 51 52static struct pll_data pll2_data = { 53 .num = 2, 54 .phys_base = DAVINCI_PLL2_BASE, 55}; 56 57static struct clk ref_clk = { 58 .name = "ref_clk", 59}; 60 61static struct clk aux_clkin = { 62 .name = "aux_clkin", 63 .rate = DM646X_AUX_FREQ, 64}; 65 66static struct clk pll1_clk = { 67 .name = "pll1", 68 .parent = &ref_clk, 69 .pll_data = &pll1_data, 70 .flags = CLK_PLL, 71}; 72 73static struct clk pll1_sysclk1 = { 74 .name = "pll1_sysclk1", 75 .parent = &pll1_clk, 76 .flags = CLK_PLL, 77 .div_reg = PLLDIV1, 78}; 79 80static struct clk pll1_sysclk2 = { 81 .name = "pll1_sysclk2", 82 .parent = &pll1_clk, 83 .flags = CLK_PLL, 84 .div_reg = PLLDIV2, 85}; 86 87static struct clk pll1_sysclk3 = { 88 .name = "pll1_sysclk3", 89 .parent = &pll1_clk, 90 .flags = CLK_PLL, 91 .div_reg = PLLDIV3, 92}; 93 94static struct clk pll1_sysclk4 = { 95 .name = "pll1_sysclk4", 96 .parent = &pll1_clk, 97 .flags = CLK_PLL, 98 .div_reg = PLLDIV4, 99}; 100 101static struct clk pll1_sysclk5 = { 102 .name = "pll1_sysclk5", 103 .parent = &pll1_clk, 104 .flags = CLK_PLL, 105 .div_reg = PLLDIV5, 106}; 107 108static struct clk pll1_sysclk6 = { 109 .name = "pll1_sysclk6", 110 .parent = &pll1_clk, 111 .flags = CLK_PLL, 112 .div_reg = PLLDIV6, 113}; 114 115static struct clk pll1_sysclk8 = { 116 .name = "pll1_sysclk8", 117 .parent = &pll1_clk, 118 .flags = CLK_PLL, 119 .div_reg = PLLDIV8, 120}; 121 122static struct clk pll1_sysclk9 = { 123 .name = "pll1_sysclk9", 124 .parent = &pll1_clk, 125 .flags = CLK_PLL, 126 .div_reg = PLLDIV9, 127}; 128 129static struct clk pll1_sysclkbp = { 130 .name = "pll1_sysclkbp", 131 .parent = &pll1_clk, 132 .flags = CLK_PLL | PRE_PLL, 133 .div_reg = BPDIV, 134}; 135 136static struct clk pll1_aux_clk = { 137 .name = "pll1_aux_clk", 138 .parent = &pll1_clk, 139 .flags = CLK_PLL | PRE_PLL, 140}; 141 142static struct clk pll2_clk = { 143 .name = "pll2_clk", 144 .parent = &ref_clk, 145 .pll_data = &pll2_data, 146 .flags = CLK_PLL, 147}; 148 149static struct clk pll2_sysclk1 = { 150 .name = "pll2_sysclk1", 151 .parent = &pll2_clk, 152 .flags = CLK_PLL, 153 .div_reg = PLLDIV1, 154}; 155 156static struct clk dsp_clk = { 157 .name = "dsp", 158 .parent = &pll1_sysclk1, 159 .lpsc = DM646X_LPSC_C64X_CPU, 160 .flags = PSC_DSP, 161 .usecount = 1, /* REVISIT how to disable? */ 162}; 163 164static struct clk arm_clk = { 165 .name = "arm", 166 .parent = &pll1_sysclk2, 167 .lpsc = DM646X_LPSC_ARM, 168 .flags = ALWAYS_ENABLED, 169}; 170 171static struct clk edma_cc_clk = { 172 .name = "edma_cc", 173 .parent = &pll1_sysclk2, 174 .lpsc = DM646X_LPSC_TPCC, 175 .flags = ALWAYS_ENABLED, 176}; 177 178static struct clk edma_tc0_clk = { 179 .name = "edma_tc0", 180 .parent = &pll1_sysclk2, 181 .lpsc = DM646X_LPSC_TPTC0, 182 .flags = ALWAYS_ENABLED, 183}; 184 185static struct clk edma_tc1_clk = { 186 .name = "edma_tc1", 187 .parent = &pll1_sysclk2, 188 .lpsc = DM646X_LPSC_TPTC1, 189 .flags = ALWAYS_ENABLED, 190}; 191 192static struct clk edma_tc2_clk = { 193 .name = "edma_tc2", 194 .parent = &pll1_sysclk2, 195 .lpsc = DM646X_LPSC_TPTC2, 196 .flags = ALWAYS_ENABLED, 197}; 198 199static struct clk edma_tc3_clk = { 200 .name = "edma_tc3", 201 .parent = &pll1_sysclk2, 202 .lpsc = DM646X_LPSC_TPTC3, 203 .flags = ALWAYS_ENABLED, 204}; 205 206static struct clk uart0_clk = { 207 .name = "uart0", 208 .parent = &aux_clkin, 209 .lpsc = DM646X_LPSC_UART0, 210}; 211 212static struct clk uart1_clk = { 213 .name = "uart1", 214 .parent = &aux_clkin, 215 .lpsc = DM646X_LPSC_UART1, 216}; 217 218static struct clk uart2_clk = { 219 .name = "uart2", 220 .parent = &aux_clkin, 221 .lpsc = DM646X_LPSC_UART2, 222}; 223 224static struct clk i2c_clk = { 225 .name = "I2CCLK", 226 .parent = &pll1_sysclk3, 227 .lpsc = DM646X_LPSC_I2C, 228}; 229 230static struct clk gpio_clk = { 231 .name = "gpio", 232 .parent = &pll1_sysclk3, 233 .lpsc = DM646X_LPSC_GPIO, 234}; 235 236static struct clk mcasp0_clk = { 237 .name = "mcasp0", 238 .parent = &pll1_sysclk3, 239 .lpsc = DM646X_LPSC_McASP0, 240}; 241 242static struct clk mcasp1_clk = { 243 .name = "mcasp1", 244 .parent = &pll1_sysclk3, 245 .lpsc = DM646X_LPSC_McASP1, 246}; 247 248static struct clk aemif_clk = { 249 .name = "aemif", 250 .parent = &pll1_sysclk3, 251 .lpsc = DM646X_LPSC_AEMIF, 252 .flags = ALWAYS_ENABLED, 253}; 254 255static struct clk emac_clk = { 256 .name = "emac", 257 .parent = &pll1_sysclk3, 258 .lpsc = DM646X_LPSC_EMAC, 259}; 260 261static struct clk pwm0_clk = { 262 .name = "pwm0", 263 .parent = &pll1_sysclk3, 264 .lpsc = DM646X_LPSC_PWM0, 265 .usecount = 1, /* REVIST: disabling hangs system */ 266}; 267 268static struct clk pwm1_clk = { 269 .name = "pwm1", 270 .parent = &pll1_sysclk3, 271 .lpsc = DM646X_LPSC_PWM1, 272 .usecount = 1, /* REVIST: disabling hangs system */ 273}; 274 275static struct clk timer0_clk = { 276 .name = "timer0", 277 .parent = &pll1_sysclk3, 278 .lpsc = DM646X_LPSC_TIMER0, 279}; 280 281static struct clk timer1_clk = { 282 .name = "timer1", 283 .parent = &pll1_sysclk3, 284 .lpsc = DM646X_LPSC_TIMER1, 285}; 286 287static struct clk timer2_clk = { 288 .name = "timer2", 289 .parent = &pll1_sysclk3, 290 .flags = ALWAYS_ENABLED, /* no LPSC, always enabled; c.f. spruep9a */ 291}; 292 293 294static struct clk ide_clk = { 295 .name = "ide", 296 .parent = &pll1_sysclk4, 297 .lpsc = DAVINCI_LPSC_ATA, 298}; 299 300static struct clk vpif0_clk = { 301 .name = "vpif0", 302 .parent = &ref_clk, 303 .lpsc = DM646X_LPSC_VPSSMSTR, 304 .flags = ALWAYS_ENABLED, 305}; 306 307static struct clk vpif1_clk = { 308 .name = "vpif1", 309 .parent = &ref_clk, 310 .lpsc = DM646X_LPSC_VPSSSLV, 311 .flags = ALWAYS_ENABLED, 312}; 313 314static struct clk_lookup dm646x_clks[] = { 315 CLK(NULL, "ref", &ref_clk), 316 CLK(NULL, "aux", &aux_clkin), 317 CLK(NULL, "pll1", &pll1_clk), 318 CLK(NULL, "pll1_sysclk", &pll1_sysclk1), 319 CLK(NULL, "pll1_sysclk", &pll1_sysclk2), 320 CLK(NULL, "pll1_sysclk", &pll1_sysclk3), 321 CLK(NULL, "pll1_sysclk", &pll1_sysclk4), 322 CLK(NULL, "pll1_sysclk", &pll1_sysclk5), 323 CLK(NULL, "pll1_sysclk", &pll1_sysclk6), 324 CLK(NULL, "pll1_sysclk", &pll1_sysclk8), 325 CLK(NULL, "pll1_sysclk", &pll1_sysclk9), 326 CLK(NULL, "pll1_sysclk", &pll1_sysclkbp), 327 CLK(NULL, "pll1_aux", &pll1_aux_clk), 328 CLK(NULL, "pll2", &pll2_clk), 329 CLK(NULL, "pll2_sysclk1", &pll2_sysclk1), 330 CLK(NULL, "dsp", &dsp_clk), 331 CLK(NULL, "arm", &arm_clk), 332 CLK(NULL, "edma_cc", &edma_cc_clk), 333 CLK(NULL, "edma_tc0", &edma_tc0_clk), 334 CLK(NULL, "edma_tc1", &edma_tc1_clk), 335 CLK(NULL, "edma_tc2", &edma_tc2_clk), 336 CLK(NULL, "edma_tc3", &edma_tc3_clk), 337 CLK(NULL, "uart0", &uart0_clk), 338 CLK(NULL, "uart1", &uart1_clk), 339 CLK(NULL, "uart2", &uart2_clk), 340 CLK("i2c_davinci.1", NULL, &i2c_clk), 341 CLK(NULL, "gpio", &gpio_clk), 342 CLK("davinci-mcasp.0", NULL, &mcasp0_clk), 343 CLK("davinci-mcasp.1", NULL, &mcasp1_clk), 344 CLK(NULL, "aemif", &aemif_clk), 345 CLK("davinci_emac.1", NULL, &emac_clk), 346 CLK(NULL, "pwm0", &pwm0_clk), 347 CLK(NULL, "pwm1", &pwm1_clk), 348 CLK(NULL, "timer0", &timer0_clk), 349 CLK(NULL, "timer1", &timer1_clk), 350 CLK("watchdog", NULL, &timer2_clk), 351 CLK("palm_bk3710", NULL, &ide_clk), 352 CLK(NULL, "vpif0", &vpif0_clk), 353 CLK(NULL, "vpif1", &vpif1_clk), 354 CLK(NULL, NULL, NULL), 355}; 356 357static struct emac_platform_data dm646x_emac_pdata = { 358 .ctrl_reg_offset = DM646X_EMAC_CNTRL_OFFSET, 359 .ctrl_mod_reg_offset = DM646X_EMAC_CNTRL_MOD_OFFSET, 360 .ctrl_ram_offset = DM646X_EMAC_CNTRL_RAM_OFFSET, 361 .mdio_reg_offset = DM646X_EMAC_MDIO_OFFSET, 362 .ctrl_ram_size = DM646X_EMAC_CNTRL_RAM_SIZE, 363 .version = EMAC_VERSION_2, 364}; 365 366static struct resource dm646x_emac_resources[] = { 367 { 368 .start = DM646X_EMAC_BASE, 369 .end = DM646X_EMAC_BASE + 0x47ff, 370 .flags = IORESOURCE_MEM, 371 }, 372 { 373 .start = IRQ_DM646X_EMACRXTHINT, 374 .end = IRQ_DM646X_EMACRXTHINT, 375 .flags = IORESOURCE_IRQ, 376 }, 377 { 378 .start = IRQ_DM646X_EMACRXINT, 379 .end = IRQ_DM646X_EMACRXINT, 380 .flags = IORESOURCE_IRQ, 381 }, 382 { 383 .start = IRQ_DM646X_EMACTXINT, 384 .end = IRQ_DM646X_EMACTXINT, 385 .flags = IORESOURCE_IRQ, 386 }, 387 { 388 .start = IRQ_DM646X_EMACMISCINT, 389 .end = IRQ_DM646X_EMACMISCINT, 390 .flags = IORESOURCE_IRQ, 391 }, 392}; 393 394static struct platform_device dm646x_emac_device = { 395 .name = "davinci_emac", 396 .id = 1, 397 .dev = { 398 .platform_data = &dm646x_emac_pdata, 399 }, 400 .num_resources = ARRAY_SIZE(dm646x_emac_resources), 401 .resource = dm646x_emac_resources, 402}; 403 404/* 405 * Device specific mux setup 406 * 407 * soc description mux mode mode mux dbg 408 * reg offset mask mode 409 */ 410static const struct mux_config dm646x_pins[] = { 411#ifdef CONFIG_DAVINCI_MUX 412MUX_CFG(DM646X, ATAEN, 0, 0, 5, 1, true) 413 414MUX_CFG(DM646X, AUDCK1, 0, 29, 1, 0, false) 415 416MUX_CFG(DM646X, AUDCK0, 0, 28, 1, 0, false) 417 418MUX_CFG(DM646X, CRGMUX, 0, 24, 7, 5, true) 419 420MUX_CFG(DM646X, STSOMUX_DISABLE, 0, 22, 3, 0, true) 421 422MUX_CFG(DM646X, STSIMUX_DISABLE, 0, 20, 3, 0, true) 423 424MUX_CFG(DM646X, PTSOMUX_DISABLE, 0, 18, 3, 0, true) 425 426MUX_CFG(DM646X, PTSIMUX_DISABLE, 0, 16, 3, 0, true) 427 428MUX_CFG(DM646X, STSOMUX, 0, 22, 3, 2, true) 429 430MUX_CFG(DM646X, STSIMUX, 0, 20, 3, 2, true) 431 432MUX_CFG(DM646X, PTSOMUX_PARALLEL, 0, 18, 3, 2, true) 433 434MUX_CFG(DM646X, PTSIMUX_PARALLEL, 0, 16, 3, 2, true) 435 436MUX_CFG(DM646X, PTSOMUX_SERIAL, 0, 18, 3, 3, true) 437 438MUX_CFG(DM646X, PTSIMUX_SERIAL, 0, 16, 3, 3, true) 439#endif 440}; 441 442static u8 dm646x_default_priorities[DAVINCI_N_AINTC_IRQ] = { 443 [IRQ_DM646X_VP_VERTINT0] = 7, 444 [IRQ_DM646X_VP_VERTINT1] = 7, 445 [IRQ_DM646X_VP_VERTINT2] = 7, 446 [IRQ_DM646X_VP_VERTINT3] = 7, 447 [IRQ_DM646X_VP_ERRINT] = 7, 448 [IRQ_DM646X_RESERVED_1] = 7, 449 [IRQ_DM646X_RESERVED_2] = 7, 450 [IRQ_DM646X_WDINT] = 7, 451 [IRQ_DM646X_CRGENINT0] = 7, 452 [IRQ_DM646X_CRGENINT1] = 7, 453 [IRQ_DM646X_TSIFINT0] = 7, 454 [IRQ_DM646X_TSIFINT1] = 7, 455 [IRQ_DM646X_VDCEINT] = 7, 456 [IRQ_DM646X_USBINT] = 7, 457 [IRQ_DM646X_USBDMAINT] = 7, 458 [IRQ_DM646X_PCIINT] = 7, 459 [IRQ_CCINT0] = 7, /* dma */ 460 [IRQ_CCERRINT] = 7, /* dma */ 461 [IRQ_TCERRINT0] = 7, /* dma */ 462 [IRQ_TCERRINT] = 7, /* dma */ 463 [IRQ_DM646X_TCERRINT2] = 7, 464 [IRQ_DM646X_TCERRINT3] = 7, 465 [IRQ_DM646X_IDE] = 7, 466 [IRQ_DM646X_HPIINT] = 7, 467 [IRQ_DM646X_EMACRXTHINT] = 7, 468 [IRQ_DM646X_EMACRXINT] = 7, 469 [IRQ_DM646X_EMACTXINT] = 7, 470 [IRQ_DM646X_EMACMISCINT] = 7, 471 [IRQ_DM646X_MCASP0TXINT] = 7, 472 [IRQ_DM646X_MCASP0RXINT] = 7, 473 [IRQ_AEMIFINT] = 7, 474 [IRQ_DM646X_RESERVED_3] = 7, 475 [IRQ_DM646X_MCASP1TXINT] = 7, /* clockevent */ 476 [IRQ_TINT0_TINT34] = 7, /* clocksource */ 477 [IRQ_TINT1_TINT12] = 7, /* DSP timer */ 478 [IRQ_TINT1_TINT34] = 7, /* system tick */ 479 [IRQ_PWMINT0] = 7, 480 [IRQ_PWMINT1] = 7, 481 [IRQ_DM646X_VLQINT] = 7, 482 [IRQ_I2C] = 7, 483 [IRQ_UARTINT0] = 7, 484 [IRQ_UARTINT1] = 7, 485 [IRQ_DM646X_UARTINT2] = 7, 486 [IRQ_DM646X_SPINT0] = 7, 487 [IRQ_DM646X_SPINT1] = 7, 488 [IRQ_DM646X_DSP2ARMINT] = 7, 489 [IRQ_DM646X_RESERVED_4] = 7, 490 [IRQ_DM646X_PSCINT] = 7, 491 [IRQ_DM646X_GPIO0] = 7, 492 [IRQ_DM646X_GPIO1] = 7, 493 [IRQ_DM646X_GPIO2] = 7, 494 [IRQ_DM646X_GPIO3] = 7, 495 [IRQ_DM646X_GPIO4] = 7, 496 [IRQ_DM646X_GPIO5] = 7, 497 [IRQ_DM646X_GPIO6] = 7, 498 [IRQ_DM646X_GPIO7] = 7, 499 [IRQ_DM646X_GPIOBNK0] = 7, 500 [IRQ_DM646X_GPIOBNK1] = 7, 501 [IRQ_DM646X_GPIOBNK2] = 7, 502 [IRQ_DM646X_DDRINT] = 7, 503 [IRQ_DM646X_AEMIFINT] = 7, 504 [IRQ_COMMTX] = 7, 505 [IRQ_COMMRX] = 7, 506 [IRQ_EMUINT] = 7, 507}; 508 509/*----------------------------------------------------------------------*/ 510 511/* Four Transfer Controllers on DM646x */ 512static const s8 513dm646x_queue_tc_mapping[][2] = { 514 /* {event queue no, TC no} */ 515 {0, 0}, 516 {1, 1}, 517 {2, 2}, 518 {3, 3}, 519 {-1, -1}, 520}; 521 522static const s8 523dm646x_queue_priority_mapping[][2] = { 524 /* {event queue no, Priority} */ 525 {0, 4}, 526 {1, 0}, 527 {2, 5}, 528 {3, 1}, 529 {-1, -1}, 530}; 531 532static struct edma_soc_info edma_cc0_info = { 533 .n_channel = 64, 534 .n_region = 6, /* 0-1, 4-7 */ 535 .n_slot = 512, 536 .n_tc = 4, 537 .n_cc = 1, 538 .queue_tc_mapping = dm646x_queue_tc_mapping, 539 .queue_priority_mapping = dm646x_queue_priority_mapping, 540}; 541 542static struct edma_soc_info *dm646x_edma_info[EDMA_MAX_CC] = { 543 &edma_cc0_info, 544}; 545 546static struct resource edma_resources[] = { 547 { 548 .name = "edma_cc0", 549 .start = 0x01c00000, 550 .end = 0x01c00000 + SZ_64K - 1, 551 .flags = IORESOURCE_MEM, 552 }, 553 { 554 .name = "edma_tc0", 555 .start = 0x01c10000, 556 .end = 0x01c10000 + SZ_1K - 1, 557 .flags = IORESOURCE_MEM, 558 }, 559 { 560 .name = "edma_tc1", 561 .start = 0x01c10400, 562 .end = 0x01c10400 + SZ_1K - 1, 563 .flags = IORESOURCE_MEM, 564 }, 565 { 566 .name = "edma_tc2", 567 .start = 0x01c10800, 568 .end = 0x01c10800 + SZ_1K - 1, 569 .flags = IORESOURCE_MEM, 570 }, 571 { 572 .name = "edma_tc3", 573 .start = 0x01c10c00, 574 .end = 0x01c10c00 + SZ_1K - 1, 575 .flags = IORESOURCE_MEM, 576 }, 577 { 578 .name = "edma0", 579 .start = IRQ_CCINT0, 580 .flags = IORESOURCE_IRQ, 581 }, 582 { 583 .name = "edma0_err", 584 .start = IRQ_CCERRINT, 585 .flags = IORESOURCE_IRQ, 586 }, 587 /* not using TC*_ERR */ 588}; 589 590static struct platform_device dm646x_edma_device = { 591 .name = "edma", 592 .id = 0, 593 .dev.platform_data = dm646x_edma_info, 594 .num_resources = ARRAY_SIZE(edma_resources), 595 .resource = edma_resources, 596}; 597 598static struct resource dm646x_mcasp0_resources[] = { 599 { 600 .name = "mcasp0", 601 .start = DAVINCI_DM646X_MCASP0_REG_BASE, 602 .end = DAVINCI_DM646X_MCASP0_REG_BASE + (SZ_1K << 1) - 1, 603 .flags = IORESOURCE_MEM, 604 }, 605 /* first TX, then RX */ 606 { 607 .start = DAVINCI_DM646X_DMA_MCASP0_AXEVT0, 608 .end = DAVINCI_DM646X_DMA_MCASP0_AXEVT0, 609 .flags = IORESOURCE_DMA, 610 }, 611 { 612 .start = DAVINCI_DM646X_DMA_MCASP0_AREVT0, 613 .end = DAVINCI_DM646X_DMA_MCASP0_AREVT0, 614 .flags = IORESOURCE_DMA, 615 }, 616}; 617 618static struct resource dm646x_mcasp1_resources[] = { 619 { 620 .name = "mcasp1", 621 .start = DAVINCI_DM646X_MCASP1_REG_BASE, 622 .end = DAVINCI_DM646X_MCASP1_REG_BASE + (SZ_1K << 1) - 1, 623 .flags = IORESOURCE_MEM, 624 }, 625 /* DIT mode, only TX event */ 626 { 627 .start = DAVINCI_DM646X_DMA_MCASP1_AXEVT1, 628 .end = DAVINCI_DM646X_DMA_MCASP1_AXEVT1, 629 .flags = IORESOURCE_DMA, 630 }, 631 /* DIT mode, dummy entry */ 632 { 633 .start = -1, 634 .end = -1, 635 .flags = IORESOURCE_DMA, 636 }, 637}; 638 639static struct platform_device dm646x_mcasp0_device = { 640 .name = "davinci-mcasp", 641 .id = 0, 642 .num_resources = ARRAY_SIZE(dm646x_mcasp0_resources), 643 .resource = dm646x_mcasp0_resources, 644}; 645 646static struct platform_device dm646x_mcasp1_device = { 647 .name = "davinci-mcasp", 648 .id = 1, 649 .num_resources = ARRAY_SIZE(dm646x_mcasp1_resources), 650 .resource = dm646x_mcasp1_resources, 651}; 652 653static struct platform_device dm646x_dit_device = { 654 .name = "spdif-dit", 655 .id = -1, 656}; 657 658static u64 vpif_dma_mask = DMA_BIT_MASK(32); 659 660static struct resource vpif_resource[] = { 661 { 662 .start = DAVINCI_VPIF_BASE, 663 .end = DAVINCI_VPIF_BASE + 0x03ff, 664 .flags = IORESOURCE_MEM, 665 } 666}; 667 668static struct platform_device vpif_dev = { 669 .name = "vpif", 670 .id = -1, 671 .dev = { 672 .dma_mask = &vpif_dma_mask, 673 .coherent_dma_mask = DMA_BIT_MASK(32), 674 }, 675 .resource = vpif_resource, 676 .num_resources = ARRAY_SIZE(vpif_resource), 677}; 678 679static struct resource vpif_display_resource[] = { 680 { 681 .start = IRQ_DM646X_VP_VERTINT2, 682 .end = IRQ_DM646X_VP_VERTINT2, 683 .flags = IORESOURCE_IRQ, 684 }, 685 { 686 .start = IRQ_DM646X_VP_VERTINT3, 687 .end = IRQ_DM646X_VP_VERTINT3, 688 .flags = IORESOURCE_IRQ, 689 }, 690}; 691 692static struct platform_device vpif_display_dev = { 693 .name = "vpif_display", 694 .id = -1, 695 .dev = { 696 .dma_mask = &vpif_dma_mask, 697 .coherent_dma_mask = DMA_BIT_MASK(32), 698 }, 699 .resource = vpif_display_resource, 700 .num_resources = ARRAY_SIZE(vpif_display_resource), 701}; 702 703static struct resource vpif_capture_resource[] = { 704 { 705 .start = IRQ_DM646X_VP_VERTINT0, 706 .end = IRQ_DM646X_VP_VERTINT0, 707 .flags = IORESOURCE_IRQ, 708 }, 709 { 710 .start = IRQ_DM646X_VP_VERTINT1, 711 .end = IRQ_DM646X_VP_VERTINT1, 712 .flags = IORESOURCE_IRQ, 713 }, 714}; 715 716static struct platform_device vpif_capture_dev = { 717 .name = "vpif_capture", 718 .id = -1, 719 .dev = { 720 .dma_mask = &vpif_dma_mask, 721 .coherent_dma_mask = DMA_BIT_MASK(32), 722 }, 723 .resource = vpif_capture_resource, 724 .num_resources = ARRAY_SIZE(vpif_capture_resource), 725}; 726 727/*----------------------------------------------------------------------*/ 728 729static struct map_desc dm646x_io_desc[] = { 730 { 731 .virtual = IO_VIRT, 732 .pfn = __phys_to_pfn(IO_PHYS), 733 .length = IO_SIZE, 734 .type = MT_DEVICE 735 }, 736 { 737 .virtual = SRAM_VIRT, 738 .pfn = __phys_to_pfn(0x00010000), 739 .length = SZ_32K, 740 .type = MT_MEMORY_NONCACHED, 741 }, 742}; 743 744/* Contents of JTAG ID register used to identify exact cpu type */ 745static struct davinci_id dm646x_ids[] = { 746 { 747 .variant = 0x0, 748 .part_no = 0xb770, 749 .manufacturer = 0x017, 750 .cpu_id = DAVINCI_CPU_ID_DM6467, 751 .name = "dm6467_rev1.x", 752 }, 753 { 754 .variant = 0x1, 755 .part_no = 0xb770, 756 .manufacturer = 0x017, 757 .cpu_id = DAVINCI_CPU_ID_DM6467, 758 .name = "dm6467_rev3.x", 759 }, 760}; 761 762static u32 dm646x_psc_bases[] = { DAVINCI_PWR_SLEEP_CNTRL_BASE }; 763 764/* 765 * T0_BOT: Timer 0, bottom: clockevent source for hrtimers 766 * T0_TOP: Timer 0, top : clocksource for generic timekeeping 767 * T1_BOT: Timer 1, bottom: (used by DSP in TI DSPLink code) 768 * T1_TOP: Timer 1, top : <unused> 769 */ 770static struct davinci_timer_info dm646x_timer_info = { 771 .timers = davinci_timer_instance, 772 .clockevent_id = T0_BOT, 773 .clocksource_id = T0_TOP, 774}; 775 776static struct plat_serial8250_port dm646x_serial_platform_data[] = { 777 { 778 .mapbase = DAVINCI_UART0_BASE, 779 .irq = IRQ_UARTINT0, 780 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | 781 UPF_IOREMAP, 782 .iotype = UPIO_MEM32, 783 .regshift = 2, 784 }, 785 { 786 .mapbase = DAVINCI_UART1_BASE, 787 .irq = IRQ_UARTINT1, 788 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | 789 UPF_IOREMAP, 790 .iotype = UPIO_MEM32, 791 .regshift = 2, 792 }, 793 { 794 .mapbase = DAVINCI_UART2_BASE, 795 .irq = IRQ_DM646X_UARTINT2, 796 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | 797 UPF_IOREMAP, 798 .iotype = UPIO_MEM32, 799 .regshift = 2, 800 }, 801 { 802 .flags = 0 803 }, 804}; 805 806static struct platform_device dm646x_serial_device = { 807 .name = "serial8250", 808 .id = PLAT8250_DEV_PLATFORM, 809 .dev = { 810 .platform_data = dm646x_serial_platform_data, 811 }, 812}; 813 814static struct davinci_soc_info davinci_soc_info_dm646x = { 815 .io_desc = dm646x_io_desc, 816 .io_desc_num = ARRAY_SIZE(dm646x_io_desc), 817 .jtag_id_reg = 0x01c40028, 818 .ids = dm646x_ids, 819 .ids_num = ARRAY_SIZE(dm646x_ids), 820 .cpu_clks = dm646x_clks, 821 .psc_bases = dm646x_psc_bases, 822 .psc_bases_num = ARRAY_SIZE(dm646x_psc_bases), 823 .pinmux_base = DAVINCI_SYSTEM_MODULE_BASE, 824 .pinmux_pins = dm646x_pins, 825 .pinmux_pins_num = ARRAY_SIZE(dm646x_pins), 826 .intc_base = DAVINCI_ARM_INTC_BASE, 827 .intc_type = DAVINCI_INTC_TYPE_AINTC, 828 .intc_irq_prios = dm646x_default_priorities, 829 .intc_irq_num = DAVINCI_N_AINTC_IRQ, 830 .timer_info = &dm646x_timer_info, 831 .gpio_type = GPIO_TYPE_DAVINCI, 832 .gpio_base = DAVINCI_GPIO_BASE, 833 .gpio_num = 43, /* Only 33 usable */ 834 .gpio_irq = IRQ_DM646X_GPIOBNK0, 835 .serial_dev = &dm646x_serial_device, 836 .emac_pdata = &dm646x_emac_pdata, 837 .sram_dma = 0x10010000, 838 .sram_len = SZ_32K, 839 .reset_device = &davinci_wdt_device, 840}; 841 842void __init dm646x_init_mcasp0(struct snd_platform_data *pdata) 843{ 844 dm646x_mcasp0_device.dev.platform_data = pdata; 845 platform_device_register(&dm646x_mcasp0_device); 846} 847 848void __init dm646x_init_mcasp1(struct snd_platform_data *pdata) 849{ 850 dm646x_mcasp1_device.dev.platform_data = pdata; 851 platform_device_register(&dm646x_mcasp1_device); 852 platform_device_register(&dm646x_dit_device); 853} 854 855void dm646x_setup_vpif(struct vpif_display_config *display_config, 856 struct vpif_capture_config *capture_config) 857{ 858 unsigned int value; 859 void __iomem *base = IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE); 860 861 value = __raw_readl(base + VSCLKDIS_OFFSET); 862 value &= ~VSCLKDIS_MASK; 863 __raw_writel(value, base + VSCLKDIS_OFFSET); 864 865 value = __raw_readl(base + VDD3P3V_PWDN_OFFSET); 866 value &= ~VDD3P3V_VID_MASK; 867 __raw_writel(value, base + VDD3P3V_PWDN_OFFSET); 868 869 davinci_cfg_reg(DM646X_STSOMUX_DISABLE); 870 davinci_cfg_reg(DM646X_STSIMUX_DISABLE); 871 davinci_cfg_reg(DM646X_PTSOMUX_DISABLE); 872 davinci_cfg_reg(DM646X_PTSIMUX_DISABLE); 873 874 vpif_display_dev.dev.platform_data = display_config; 875 vpif_capture_dev.dev.platform_data = capture_config; 876 platform_device_register(&vpif_dev); 877 platform_device_register(&vpif_display_dev); 878 platform_device_register(&vpif_capture_dev); 879} 880 881int __init dm646x_init_edma(struct edma_rsv_info *rsv) 882{ 883 edma_cc0_info.rsv = rsv; 884 885 return platform_device_register(&dm646x_edma_device); 886} 887 888void __init dm646x_init(void) 889{ 890 dm646x_board_setup_refclk(&ref_clk); 891 davinci_common_init(&davinci_soc_info_dm646x); 892} 893 894static int __init dm646x_init_devices(void) 895{ 896 if (!cpu_is_davinci_dm646x()) 897 return 0; 898 899 platform_device_register(&dm646x_emac_device); 900 return 0; 901} 902postcore_initcall(dm646x_init_devices); 903