1/* 2 * mach-davinci/devices.c 3 * 4 * DaVinci platform device setup/initialization 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 */ 11 12#include <linux/init.h> 13#include <linux/platform_device.h> 14#include <linux/dma-mapping.h> 15#include <linux/io.h> 16 17#include <mach/hardware.h> 18#include <mach/i2c.h> 19#include <mach/irqs.h> 20#include <mach/cputype.h> 21#include <mach/mux.h> 22#include <mach/edma.h> 23#include <mach/mmc.h> 24#include <mach/time.h> 25 26#include "clock.h" 27 28#define DAVINCI_I2C_BASE 0x01C21000 29#define DAVINCI_ATA_BASE 0x01C66000 30#define DAVINCI_MMCSD0_BASE 0x01E10000 31#define DM355_MMCSD0_BASE 0x01E11000 32#define DM355_MMCSD1_BASE 0x01E00000 33#define DM365_MMCSD0_BASE 0x01D11000 34#define DM365_MMCSD1_BASE 0x01D00000 35 36static struct resource i2c_resources[] = { 37 { 38 .start = DAVINCI_I2C_BASE, 39 .end = DAVINCI_I2C_BASE + 0x40, 40 .flags = IORESOURCE_MEM, 41 }, 42 { 43 .start = IRQ_I2C, 44 .flags = IORESOURCE_IRQ, 45 }, 46}; 47 48static struct platform_device davinci_i2c_device = { 49 .name = "i2c_davinci", 50 .id = 1, 51 .num_resources = ARRAY_SIZE(i2c_resources), 52 .resource = i2c_resources, 53}; 54 55void __init davinci_init_i2c(struct davinci_i2c_platform_data *pdata) 56{ 57 if (cpu_is_davinci_dm644x()) 58 davinci_cfg_reg(DM644X_I2C); 59 60 davinci_i2c_device.dev.platform_data = pdata; 61 (void) platform_device_register(&davinci_i2c_device); 62} 63 64static struct resource ide_resources[] = { 65 { 66 .start = DAVINCI_ATA_BASE, 67 .end = DAVINCI_ATA_BASE + 0x7ff, 68 .flags = IORESOURCE_MEM, 69 }, 70 { 71 .start = IRQ_IDE, 72 .end = IRQ_IDE, 73 .flags = IORESOURCE_IRQ, 74 }, 75}; 76 77static u64 ide_dma_mask = DMA_BIT_MASK(32); 78 79static struct platform_device ide_device = { 80 .name = "palm_bk3710", 81 .id = -1, 82 .resource = ide_resources, 83 .num_resources = ARRAY_SIZE(ide_resources), 84 .dev = { 85 .dma_mask = &ide_dma_mask, 86 .coherent_dma_mask = DMA_BIT_MASK(32), 87 }, 88}; 89 90void __init davinci_init_ide(void) 91{ 92 if (cpu_is_davinci_dm644x()) { 93 davinci_cfg_reg(DM644X_HPIEN_DISABLE); 94 davinci_cfg_reg(DM644X_ATAEN); 95 davinci_cfg_reg(DM644X_HDIREN); 96 } else if (cpu_is_davinci_dm646x()) { 97 /* IRQ_DM646X_IDE is the same as IRQ_IDE */ 98 davinci_cfg_reg(DM646X_ATAEN); 99 } else { 100 WARN_ON(1); 101 return; 102 } 103 104 platform_device_register(&ide_device); 105} 106 107#if defined(CONFIG_MMC_DAVINCI) || defined(CONFIG_MMC_DAVINCI_MODULE) 108 109static u64 mmcsd0_dma_mask = DMA_BIT_MASK(32); 110 111static struct resource mmcsd0_resources[] = { 112 { 113 /* different on dm355 */ 114 .start = DAVINCI_MMCSD0_BASE, 115 .end = DAVINCI_MMCSD0_BASE + SZ_4K - 1, 116 .flags = IORESOURCE_MEM, 117 }, 118 /* IRQs: MMC/SD, then SDIO */ 119 { 120 .start = IRQ_MMCINT, 121 .flags = IORESOURCE_IRQ, 122 }, { 123 /* different on dm355 */ 124 .start = IRQ_SDIOINT, 125 .flags = IORESOURCE_IRQ, 126 }, 127 /* DMA channels: RX, then TX */ 128 { 129 .start = EDMA_CTLR_CHAN(0, DAVINCI_DMA_MMCRXEVT), 130 .flags = IORESOURCE_DMA, 131 }, { 132 .start = EDMA_CTLR_CHAN(0, DAVINCI_DMA_MMCTXEVT), 133 .flags = IORESOURCE_DMA, 134 }, 135}; 136 137static struct platform_device davinci_mmcsd0_device = { 138 .name = "davinci_mmc", 139 .id = 0, 140 .dev = { 141 .dma_mask = &mmcsd0_dma_mask, 142 .coherent_dma_mask = DMA_BIT_MASK(32), 143 }, 144 .num_resources = ARRAY_SIZE(mmcsd0_resources), 145 .resource = mmcsd0_resources, 146}; 147 148static u64 mmcsd1_dma_mask = DMA_BIT_MASK(32); 149 150static struct resource mmcsd1_resources[] = { 151 { 152 .start = DM355_MMCSD1_BASE, 153 .end = DM355_MMCSD1_BASE + SZ_4K - 1, 154 .flags = IORESOURCE_MEM, 155 }, 156 /* IRQs: MMC/SD, then SDIO */ 157 { 158 .start = IRQ_DM355_MMCINT1, 159 .flags = IORESOURCE_IRQ, 160 }, { 161 .start = IRQ_DM355_SDIOINT1, 162 .flags = IORESOURCE_IRQ, 163 }, 164 /* DMA channels: RX, then TX */ 165 { 166 .start = EDMA_CTLR_CHAN(0, 30), /* rx */ 167 .flags = IORESOURCE_DMA, 168 }, { 169 .start = EDMA_CTLR_CHAN(0, 31), /* tx */ 170 .flags = IORESOURCE_DMA, 171 }, 172}; 173 174static struct platform_device davinci_mmcsd1_device = { 175 .name = "davinci_mmc", 176 .id = 1, 177 .dev = { 178 .dma_mask = &mmcsd1_dma_mask, 179 .coherent_dma_mask = DMA_BIT_MASK(32), 180 }, 181 .num_resources = ARRAY_SIZE(mmcsd1_resources), 182 .resource = mmcsd1_resources, 183}; 184 185 186void __init davinci_setup_mmc(int module, struct davinci_mmc_config *config) 187{ 188 struct platform_device *pdev = NULL; 189 190 if (WARN_ON(cpu_is_davinci_dm646x())) 191 return; 192 193 switch (module) { 194 case 1: 195 if (cpu_is_davinci_dm355()) { 196 /* REVISIT we may not need all these pins if e.g. this 197 * is a hard-wired SDIO device... 198 */ 199 davinci_cfg_reg(DM355_SD1_CMD); 200 davinci_cfg_reg(DM355_SD1_CLK); 201 davinci_cfg_reg(DM355_SD1_DATA0); 202 davinci_cfg_reg(DM355_SD1_DATA1); 203 davinci_cfg_reg(DM355_SD1_DATA2); 204 davinci_cfg_reg(DM355_SD1_DATA3); 205 } else if (cpu_is_davinci_dm365()) { 206 void __iomem *pupdctl1 = 207 IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE + 0x7c); 208 209 /* Configure pull down control */ 210 __raw_writel((__raw_readl(pupdctl1) & ~0x400), 211 pupdctl1); 212 213 mmcsd1_resources[0].start = DM365_MMCSD1_BASE; 214 mmcsd1_resources[0].end = DM365_MMCSD1_BASE + 215 SZ_4K - 1; 216 mmcsd1_resources[2].start = IRQ_DM365_SDIOINT1; 217 } else 218 break; 219 220 pdev = &davinci_mmcsd1_device; 221 break; 222 case 0: 223 if (cpu_is_davinci_dm355()) { 224 mmcsd0_resources[0].start = DM355_MMCSD0_BASE; 225 mmcsd0_resources[0].end = DM355_MMCSD0_BASE + SZ_4K - 1; 226 mmcsd0_resources[2].start = IRQ_DM355_SDIOINT0; 227 228 /* expose all 6 MMC0 signals: CLK, CMD, DATA[0..3] */ 229 davinci_cfg_reg(DM355_MMCSD0); 230 231 /* enable RX EDMA */ 232 davinci_cfg_reg(DM355_EVT26_MMC0_RX); 233 } else if (cpu_is_davinci_dm365()) { 234 mmcsd0_resources[0].start = DM365_MMCSD0_BASE; 235 mmcsd0_resources[0].end = DM365_MMCSD0_BASE + 236 SZ_4K - 1; 237 mmcsd0_resources[2].start = IRQ_DM365_SDIOINT0; 238 } else if (cpu_is_davinci_dm644x()) { 239 /* REVISIT: should this be in board-init code? */ 240 void __iomem *base = 241 IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE); 242 243 /* Power-on 3.3V IO cells */ 244 __raw_writel(0, base + DM64XX_VDD3P3V_PWDN); 245 /*Set up the pull regiter for MMC */ 246 davinci_cfg_reg(DM644X_MSTK); 247 } 248 249 pdev = &davinci_mmcsd0_device; 250 break; 251 } 252 253 if (WARN_ON(!pdev)) 254 return; 255 256 pdev->dev.platform_data = config; 257 platform_device_register(pdev); 258} 259 260#else 261 262void __init davinci_setup_mmc(int module, struct davinci_mmc_config *config) 263{ 264} 265 266#endif 267 268/*-------------------------------------------------------------------------*/ 269 270static struct resource wdt_resources[] = { 271 { 272 .start = DAVINCI_WDOG_BASE, 273 .end = DAVINCI_WDOG_BASE + SZ_1K - 1, 274 .flags = IORESOURCE_MEM, 275 }, 276}; 277 278struct platform_device davinci_wdt_device = { 279 .name = "watchdog", 280 .id = -1, 281 .num_resources = ARRAY_SIZE(wdt_resources), 282 .resource = wdt_resources, 283}; 284 285static void davinci_init_wdt(void) 286{ 287 platform_device_register(&davinci_wdt_device); 288} 289 290/*-------------------------------------------------------------------------*/ 291 292struct davinci_timer_instance davinci_timer_instance[2] = { 293 { 294 .base = DAVINCI_TIMER0_BASE, 295 .bottom_irq = IRQ_TINT0_TINT12, 296 .top_irq = IRQ_TINT0_TINT34, 297 }, 298 { 299 .base = DAVINCI_TIMER1_BASE, 300 .bottom_irq = IRQ_TINT1_TINT12, 301 .top_irq = IRQ_TINT1_TINT34, 302 }, 303}; 304 305/*-------------------------------------------------------------------------*/ 306 307static int __init davinci_init_devices(void) 308{ 309 /* please keep these calls, and their implementations above, 310 * in alphabetical order so they're easier to sort through. 311 */ 312 davinci_init_wdt(); 313 314 return 0; 315} 316arch_initcall(davinci_init_devices); 317