1/***************************************************************************** 2* Copyright 2003 - 2008 Broadcom Corporation. All rights reserved. 3* 4* Unless you and Broadcom execute a separate written software license 5* agreement governing use of this software, this software is licensed to you 6* under the terms of the GNU General Public License version 2, available at 7* http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). 8* 9* Notwithstanding the above, under no circumstances may you combine this 10* software in any way with any other Broadcom software provided under a 11* license other than the GPL, without Broadcom's express prior written 12* consent. 13*****************************************************************************/ 14 15 16#ifndef CSP_HW_CFG_H 17#define CSP_HW_CFG_H 18 19/* ---- Include Files ---------------------------------------------------- */ 20 21#include <cfg_global.h> 22#include <mach/csp/cap_inline.h> 23 24#if defined(__KERNEL__) 25#include <mach/memory_settings.h> 26#else 27#include <hw_cfg.h> 28#endif 29 30/* Some items that can be defined externally, but will be set to default values */ 31/* if they are not defined. */ 32/* HW_CFG_PLL_SPREAD_SPECTRUM_DISABLE Default undefined and SS is enabled. */ 33/* HW_CFG_SDRAM_CAS_LATENCY 5 Default 5, Values [3..6] */ 34/* HW_CFG_SDRAM_CHIP_SELECT_CNT 1 Default 1, Vaules [1..2] */ 35/* HW_CFG_SDRAM_SPEED_GRADE 667 Default 667, Values [400,533,667,800] */ 36/* HW_CFG_SDRAM_WIDTH_BITS 16 Default 16, Vaules [8,16] */ 37/* HW_CFG_SDRAM_ADDR_BRC Default undefined and Row-Bank-Col (RBC) addressing used. Define to use Bank-Row-Col (BRC). */ 38/* HW_CFG_SDRAM_CLK_ASYNC Default undefined and DDR clock is synchronous with AXI BUS clock. Define for ASYNC mode. */ 39 40#if defined(CFG_GLOBAL_CHIP) 41 #if (CFG_GLOBAL_CHIP == FPGA11107) 42 #define HW_CFG_BUS_CLK_HZ 5000000 43 #define HW_CFG_DDR_CTLR_CLK_HZ 10000000 44 #define HW_CFG_DDR_PHY_OMIT 45 #define HW_CFG_UART_CLK_HZ 7500000 46 #else 47 #define HW_CFG_PLL_VCO_HZ 2000000000 48 #define HW_CFG_PLL2_VCO_HZ 1800000000 49 #define HW_CFG_ARM_CLK_HZ CAP_HW_CFG_ARM_CLK_HZ 50 #define HW_CFG_BUS_CLK_HZ 166666666 51 #define HW_CFG_DDR_CTLR_CLK_HZ 333333333 52 #define HW_CFG_DDR_PHY_CLK_HZ (2 * HW_CFG_DDR_CTLR_CLK_HZ) 53 #define HW_CFG_UART_CLK_HZ 142857142 54 #define HW_CFG_VPM_CLK_HZ CAP_HW_CFG_VPM_CLK_HZ 55 #endif 56#else 57 #define HW_CFG_PLL_VCO_HZ 1800000000 58 #define HW_CFG_PLL2_VCO_HZ 1800000000 59 #define HW_CFG_ARM_CLK_HZ 450000000 60 #define HW_CFG_BUS_CLK_HZ 150000000 61 #define HW_CFG_DDR_CTLR_CLK_HZ 300000000 62 #define HW_CFG_DDR_PHY_CLK_HZ (2 * HW_CFG_DDR_CTLR_CLK_HZ) 63 #define HW_CFG_UART_CLK_HZ 150000000 64 #define HW_CFG_VPM_CLK_HZ 300000000 65#endif 66 67/* ---- Public Constants and Types --------------------------------------- */ 68/* ---- Public Variable Externs ------------------------------------------ */ 69/* ---- Public Function Prototypes --------------------------------------- */ 70 71 72#endif /* CSP_HW_CFG_H */ 73