1/* 2 * arch/arm/mach-at91/include/mach/at91cap9_ddrsdr.h 3 * 4 * (C) 2008 Andrew Victor 5 * 6 * DDR/SDR Controller (DDRSDRC) - System peripherals registers. 7 * Based on AT91CAP9 datasheet revision B. 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License as published by 11 * the Free Software Foundation; either version 2 of the License, or 12 * (at your option) any later version. 13 */ 14 15#ifndef AT91CAP9_DDRSDR_H 16#define AT91CAP9_DDRSDR_H 17 18#define AT91_DDRSDRC_MR 0x00 /* Mode Register */ 19#define AT91_DDRSDRC_MODE (0xf << 0) /* Command Mode */ 20#define AT91_DDRSDRC_MODE_NORMAL 0 21#define AT91_DDRSDRC_MODE_NOP 1 22#define AT91_DDRSDRC_MODE_PRECHARGE 2 23#define AT91_DDRSDRC_MODE_LMR 3 24#define AT91_DDRSDRC_MODE_REFRESH 4 25#define AT91_DDRSDRC_MODE_EXT_LMR 5 26#define AT91_DDRSDRC_MODE_DEEP 6 27 28#define AT91_DDRSDRC_RTR 0x04 /* Refresh Timer Register */ 29#define AT91_DDRSDRC_COUNT (0xfff << 0) /* Refresh Timer Counter */ 30 31#define AT91_DDRSDRC_CR 0x08 /* Configuration Register */ 32#define AT91_DDRSDRC_NC (3 << 0) /* Number of Column Bits */ 33#define AT91_DDRSDRC_NC_SDR8 (0 << 0) 34#define AT91_DDRSDRC_NC_SDR9 (1 << 0) 35#define AT91_DDRSDRC_NC_SDR10 (2 << 0) 36#define AT91_DDRSDRC_NC_SDR11 (3 << 0) 37#define AT91_DDRSDRC_NC_DDR9 (0 << 0) 38#define AT91_DDRSDRC_NC_DDR10 (1 << 0) 39#define AT91_DDRSDRC_NC_DDR11 (2 << 0) 40#define AT91_DDRSDRC_NC_DDR12 (3 << 0) 41#define AT91_DDRSDRC_NR (3 << 2) /* Number of Row Bits */ 42#define AT91_DDRSDRC_NR_11 (0 << 2) 43#define AT91_DDRSDRC_NR_12 (1 << 2) 44#define AT91_DDRSDRC_NR_13 (2 << 2) 45#define AT91_DDRSDRC_CAS (7 << 4) /* CAS Latency */ 46#define AT91_DDRSDRC_CAS_2 (2 << 4) 47#define AT91_DDRSDRC_CAS_3 (3 << 4) 48#define AT91_DDRSDRC_CAS_25 (6 << 4) 49#define AT91_DDRSDRC_DLL (1 << 7) /* Reset DLL */ 50#define AT91_DDRSDRC_DICDS (1 << 8) /* Output impedance control */ 51 52#define AT91_DDRSDRC_T0PR 0x0C /* Timing 0 Register */ 53#define AT91_DDRSDRC_TRAS (0xf << 0) /* Active to Precharge delay */ 54#define AT91_DDRSDRC_TRCD (0xf << 4) /* Row to Column delay */ 55#define AT91_DDRSDRC_TWR (0xf << 8) /* Write recovery delay */ 56#define AT91_DDRSDRC_TRC (0xf << 12) /* Row cycle delay */ 57#define AT91_DDRSDRC_TRP (0xf << 16) /* Row precharge delay */ 58#define AT91_DDRSDRC_TRRD (0xf << 20) /* Active BankA to BankB */ 59#define AT91_DDRSDRC_TWTR (1 << 24) /* Internal Write to Read delay */ 60#define AT91_DDRSDRC_TMRD (0xf << 28) /* Load mode to active/refresh delay */ 61 62#define AT91_DDRSDRC_T1PR 0x10 /* Timing 1 Register */ 63#define AT91_DDRSDRC_TRFC (0x1f << 0) /* Row Cycle Delay */ 64#define AT91_DDRSDRC_TXSNR (0xff << 8) /* Exit self-refresh to non-read */ 65#define AT91_DDRSDRC_TXSRD (0xff << 16) /* Exit self-refresh to read */ 66#define AT91_DDRSDRC_TXP (0xf << 24) /* Exit power-down delay */ 67 68#define AT91_DDRSDRC_LPR 0x18 /* Low Power Register */ 69#define AT91_DDRSDRC_LPCB (3 << 0) /* Low-power Configurations */ 70#define AT91_DDRSDRC_LPCB_DISABLE 0 71#define AT91_DDRSDRC_LPCB_SELF_REFRESH 1 72#define AT91_DDRSDRC_LPCB_POWER_DOWN 2 73#define AT91_DDRSDRC_LPCB_DEEP_POWER_DOWN 3 74#define AT91_DDRSDRC_CLKFR (1 << 2) /* Clock Frozen */ 75#define AT91_DDRSDRC_PASR (7 << 4) /* Partial Array Self Refresh */ 76#define AT91_DDRSDRC_TCSR (3 << 8) /* Temperature Compensated Self Refresh */ 77#define AT91_DDRSDRC_DS (3 << 10) /* Drive Strength */ 78#define AT91_DDRSDRC_TIMEOUT (3 << 12) /* Time to define when Low Power Mode is enabled */ 79#define AT91_DDRSDRC_TIMEOUT_0_CLK_CYCLES (0 << 12) 80#define AT91_DDRSDRC_TIMEOUT_64_CLK_CYCLES (1 << 12) 81#define AT91_DDRSDRC_TIMEOUT_128_CLK_CYCLES (2 << 12) 82 83#define AT91_DDRSDRC_MDR 0x1C /* Memory Device Register */ 84#define AT91_DDRSDRC_MD (3 << 0) /* Memory Device Type */ 85#define AT91_DDRSDRC_MD_SDR 0 86#define AT91_DDRSDRC_MD_LOW_POWER_SDR 1 87#define AT91_DDRSDRC_MD_DDR 2 88#define AT91_DDRSDRC_MD_LOW_POWER_DDR 3 89 90#define AT91_DDRSDRC_DLLR 0x20 /* DLL Information Register */ 91#define AT91_DDRSDRC_MDINC (1 << 0) /* Master Delay increment */ 92#define AT91_DDRSDRC_MDDEC (1 << 1) /* Master Delay decrement */ 93#define AT91_DDRSDRC_MDOVF (1 << 2) /* Master Delay Overflow */ 94#define AT91_DDRSDRC_SDCOVF (1 << 3) /* Slave Delay Correction Overflow */ 95#define AT91_DDRSDRC_SDCUDF (1 << 4) /* Slave Delay Correction Underflow */ 96#define AT91_DDRSDRC_SDERF (1 << 5) /* Slave Delay Correction error */ 97#define AT91_DDRSDRC_MDVAL (0xff << 8) /* Master Delay value */ 98#define AT91_DDRSDRC_SDVAL (0xff << 16) /* Slave Delay value */ 99#define AT91_DDRSDRC_SDCVAL (0xff << 24) /* Slave Delay Correction value */ 100 101/* Register access macros */ 102#define at91_ramc_read(num, reg) \ 103 at91_sys_read(AT91_DDRSDRC##num + reg) 104#define at91_ramc_write(num, reg, value) \ 105 at91_sys_write(AT91_DDRSDRC##num + reg, value) 106 107 108#endif 109