1/* 2 * linux/arch/arm/mach-at91/gpio.c 3 * 4 * Copyright (C) 2005 HP Labs 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 */ 11 12#include <linux/clk.h> 13#include <linux/errno.h> 14#include <linux/interrupt.h> 15#include <linux/irq.h> 16#include <linux/debugfs.h> 17#include <linux/seq_file.h> 18#include <linux/kernel.h> 19#include <linux/list.h> 20#include <linux/module.h> 21#include <linux/io.h> 22 23#include <mach/hardware.h> 24#include <mach/at91_pio.h> 25#include <mach/gpio.h> 26 27#include <asm/gpio.h> 28 29#include "generic.h" 30 31struct at91_gpio_chip { 32 struct gpio_chip chip; 33 struct at91_gpio_chip *next; /* Bank sharing same clock */ 34 struct at91_gpio_bank *bank; /* Bank definition */ 35 void __iomem *regbase; /* Base of register bank */ 36}; 37 38#define to_at91_gpio_chip(c) container_of(c, struct at91_gpio_chip, chip) 39 40static void at91_gpiolib_dbg_show(struct seq_file *s, struct gpio_chip *chip); 41static void at91_gpiolib_set(struct gpio_chip *chip, unsigned offset, int val); 42static int at91_gpiolib_get(struct gpio_chip *chip, unsigned offset); 43static int at91_gpiolib_direction_output(struct gpio_chip *chip, 44 unsigned offset, int val); 45static int at91_gpiolib_direction_input(struct gpio_chip *chip, 46 unsigned offset); 47 48#define AT91_GPIO_CHIP(name, base_gpio, nr_gpio) \ 49 { \ 50 .chip = { \ 51 .label = name, \ 52 .direction_input = at91_gpiolib_direction_input, \ 53 .direction_output = at91_gpiolib_direction_output, \ 54 .get = at91_gpiolib_get, \ 55 .set = at91_gpiolib_set, \ 56 .dbg_show = at91_gpiolib_dbg_show, \ 57 .base = base_gpio, \ 58 .ngpio = nr_gpio, \ 59 }, \ 60 } 61 62static struct at91_gpio_chip gpio_chip[] = { 63 AT91_GPIO_CHIP("A", 0x00 + PIN_BASE, 32), 64 AT91_GPIO_CHIP("B", 0x20 + PIN_BASE, 32), 65 AT91_GPIO_CHIP("C", 0x40 + PIN_BASE, 32), 66 AT91_GPIO_CHIP("D", 0x60 + PIN_BASE, 32), 67 AT91_GPIO_CHIP("E", 0x80 + PIN_BASE, 32), 68}; 69 70static int gpio_banks; 71 72static inline void __iomem *pin_to_controller(unsigned pin) 73{ 74 pin -= PIN_BASE; 75 pin /= 32; 76 if (likely(pin < gpio_banks)) 77 return gpio_chip[pin].regbase; 78 79 return NULL; 80} 81 82static inline unsigned pin_to_mask(unsigned pin) 83{ 84 pin -= PIN_BASE; 85 return 1 << (pin % 32); 86} 87 88 89/*--------------------------------------------------------------------------*/ 90 91/* Not all hardware capabilities are exposed through these calls; they 92 * only encapsulate the most common features and modes. (So if you 93 * want to change signals in groups, do it directly.) 94 * 95 * Bootloaders will usually handle some of the pin multiplexing setup. 96 * The intent is certainly that by the time Linux is fully booted, all 97 * pins should have been fully initialized. These setup calls should 98 * only be used by board setup routines, or possibly in driver probe(). 99 * 100 * For bootloaders doing all that setup, these calls could be inlined 101 * as NOPs so Linux won't duplicate any setup code 102 */ 103 104 105/* 106 * mux the pin to the "GPIO" peripheral role. 107 */ 108int __init_or_module at91_set_GPIO_periph(unsigned pin, int use_pullup) 109{ 110 void __iomem *pio = pin_to_controller(pin); 111 unsigned mask = pin_to_mask(pin); 112 113 if (!pio) 114 return -EINVAL; 115 __raw_writel(mask, pio + PIO_IDR); 116 __raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR)); 117 __raw_writel(mask, pio + PIO_PER); 118 return 0; 119} 120EXPORT_SYMBOL(at91_set_GPIO_periph); 121 122 123/* 124 * mux the pin to the "A" internal peripheral role. 125 */ 126int __init_or_module at91_set_A_periph(unsigned pin, int use_pullup) 127{ 128 void __iomem *pio = pin_to_controller(pin); 129 unsigned mask = pin_to_mask(pin); 130 131 if (!pio) 132 return -EINVAL; 133 134 __raw_writel(mask, pio + PIO_IDR); 135 __raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR)); 136 __raw_writel(mask, pio + PIO_ASR); 137 __raw_writel(mask, pio + PIO_PDR); 138 return 0; 139} 140EXPORT_SYMBOL(at91_set_A_periph); 141 142 143/* 144 * mux the pin to the "B" internal peripheral role. 145 */ 146int __init_or_module at91_set_B_periph(unsigned pin, int use_pullup) 147{ 148 void __iomem *pio = pin_to_controller(pin); 149 unsigned mask = pin_to_mask(pin); 150 151 if (!pio) 152 return -EINVAL; 153 154 __raw_writel(mask, pio + PIO_IDR); 155 __raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR)); 156 __raw_writel(mask, pio + PIO_BSR); 157 __raw_writel(mask, pio + PIO_PDR); 158 return 0; 159} 160EXPORT_SYMBOL(at91_set_B_periph); 161 162 163/* 164 * mux the pin to the gpio controller (instead of "A" or "B" peripheral), and 165 * configure it for an input. 166 */ 167int __init_or_module at91_set_gpio_input(unsigned pin, int use_pullup) 168{ 169 void __iomem *pio = pin_to_controller(pin); 170 unsigned mask = pin_to_mask(pin); 171 172 if (!pio) 173 return -EINVAL; 174 175 __raw_writel(mask, pio + PIO_IDR); 176 __raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR)); 177 __raw_writel(mask, pio + PIO_ODR); 178 __raw_writel(mask, pio + PIO_PER); 179 return 0; 180} 181EXPORT_SYMBOL(at91_set_gpio_input); 182 183 184/* 185 * mux the pin to the gpio controller (instead of "A" or "B" peripheral), 186 * and configure it for an output. 187 */ 188int __init_or_module at91_set_gpio_output(unsigned pin, int value) 189{ 190 void __iomem *pio = pin_to_controller(pin); 191 unsigned mask = pin_to_mask(pin); 192 193 if (!pio) 194 return -EINVAL; 195 196 __raw_writel(mask, pio + PIO_IDR); 197 __raw_writel(mask, pio + PIO_PUDR); 198 __raw_writel(mask, pio + (value ? PIO_SODR : PIO_CODR)); 199 __raw_writel(mask, pio + PIO_OER); 200 __raw_writel(mask, pio + PIO_PER); 201 return 0; 202} 203EXPORT_SYMBOL(at91_set_gpio_output); 204 205 206/* 207 * enable/disable the glitch filter; mostly used with IRQ handling. 208 */ 209int __init_or_module at91_set_deglitch(unsigned pin, int is_on) 210{ 211 void __iomem *pio = pin_to_controller(pin); 212 unsigned mask = pin_to_mask(pin); 213 214 if (!pio) 215 return -EINVAL; 216 __raw_writel(mask, pio + (is_on ? PIO_IFER : PIO_IFDR)); 217 return 0; 218} 219EXPORT_SYMBOL(at91_set_deglitch); 220 221/* 222 * enable/disable the multi-driver; This is only valid for output and 223 * allows the output pin to run as an open collector output. 224 */ 225int __init_or_module at91_set_multi_drive(unsigned pin, int is_on) 226{ 227 void __iomem *pio = pin_to_controller(pin); 228 unsigned mask = pin_to_mask(pin); 229 230 if (!pio) 231 return -EINVAL; 232 233 __raw_writel(mask, pio + (is_on ? PIO_MDER : PIO_MDDR)); 234 return 0; 235} 236EXPORT_SYMBOL(at91_set_multi_drive); 237 238/* 239 * assuming the pin is muxed as a gpio output, set its value. 240 */ 241int at91_set_gpio_value(unsigned pin, int value) 242{ 243 void __iomem *pio = pin_to_controller(pin); 244 unsigned mask = pin_to_mask(pin); 245 246 if (!pio) 247 return -EINVAL; 248 __raw_writel(mask, pio + (value ? PIO_SODR : PIO_CODR)); 249 return 0; 250} 251EXPORT_SYMBOL(at91_set_gpio_value); 252 253 254/* 255 * read the pin's value (works even if it's not muxed as a gpio). 256 */ 257int at91_get_gpio_value(unsigned pin) 258{ 259 void __iomem *pio = pin_to_controller(pin); 260 unsigned mask = pin_to_mask(pin); 261 u32 pdsr; 262 263 if (!pio) 264 return -EINVAL; 265 pdsr = __raw_readl(pio + PIO_PDSR); 266 return (pdsr & mask) != 0; 267} 268EXPORT_SYMBOL(at91_get_gpio_value); 269 270/*--------------------------------------------------------------------------*/ 271 272#ifdef CONFIG_PM 273 274static u32 wakeups[MAX_GPIO_BANKS]; 275static u32 backups[MAX_GPIO_BANKS]; 276 277static int gpio_irq_set_wake(unsigned pin, unsigned state) 278{ 279 unsigned mask = pin_to_mask(pin); 280 unsigned bank = (pin - PIN_BASE) / 32; 281 282 if (unlikely(bank >= MAX_GPIO_BANKS)) 283 return -EINVAL; 284 285 if (state) 286 wakeups[bank] |= mask; 287 else 288 wakeups[bank] &= ~mask; 289 290 set_irq_wake(gpio_chip[bank].bank->id, state); 291 292 return 0; 293} 294 295void at91_gpio_suspend(void) 296{ 297 int i; 298 299 for (i = 0; i < gpio_banks; i++) { 300 void __iomem *pio = gpio_chip[i].regbase; 301 302 backups[i] = __raw_readl(pio + PIO_IMR); 303 __raw_writel(backups[i], pio + PIO_IDR); 304 __raw_writel(wakeups[i], pio + PIO_IER); 305 306 if (!wakeups[i]) 307 clk_disable(gpio_chip[i].bank->clock); 308 else { 309#ifdef CONFIG_PM_DEBUG 310 printk(KERN_DEBUG "GPIO-%c may wake for %08x\n", 'A'+i, wakeups[i]); 311#endif 312 } 313 } 314} 315 316void at91_gpio_resume(void) 317{ 318 int i; 319 320 for (i = 0; i < gpio_banks; i++) { 321 void __iomem *pio = gpio_chip[i].regbase; 322 323 if (!wakeups[i]) 324 clk_enable(gpio_chip[i].bank->clock); 325 326 __raw_writel(wakeups[i], pio + PIO_IDR); 327 __raw_writel(backups[i], pio + PIO_IER); 328 } 329} 330 331#else 332#define gpio_irq_set_wake NULL 333#endif 334 335 336/* Several AIC controller irqs are dispatched through this GPIO handler. 337 * To use any AT91_PIN_* as an externally triggered IRQ, first call 338 * at91_set_gpio_input() then maybe enable its glitch filter. 339 * Then just request_irq() with the pin ID; it works like any ARM IRQ 340 * handler, though it always triggers on rising and falling edges. 341 * 342 * Alternatively, certain pins may be used directly as IRQ0..IRQ6 after 343 * configuring them with at91_set_a_periph() or at91_set_b_periph(). 344 * IRQ0..IRQ6 should be configurable, e.g. level vs edge triggering. 345 */ 346 347static void gpio_irq_mask(unsigned pin) 348{ 349 void __iomem *pio = pin_to_controller(pin); 350 unsigned mask = pin_to_mask(pin); 351 352 if (pio) 353 __raw_writel(mask, pio + PIO_IDR); 354} 355 356static void gpio_irq_unmask(unsigned pin) 357{ 358 void __iomem *pio = pin_to_controller(pin); 359 unsigned mask = pin_to_mask(pin); 360 361 if (pio) 362 __raw_writel(mask, pio + PIO_IER); 363} 364 365static int gpio_irq_type(unsigned pin, unsigned type) 366{ 367 switch (type) { 368 case IRQ_TYPE_NONE: 369 case IRQ_TYPE_EDGE_BOTH: 370 return 0; 371 default: 372 return -EINVAL; 373 } 374} 375 376static struct irq_chip gpio_irqchip = { 377 .name = "GPIO", 378 .mask = gpio_irq_mask, 379 .unmask = gpio_irq_unmask, 380 .set_type = gpio_irq_type, 381 .set_wake = gpio_irq_set_wake, 382}; 383 384static void gpio_irq_handler(unsigned irq, struct irq_desc *desc) 385{ 386 unsigned pin; 387 struct irq_desc *gpio; 388 struct at91_gpio_chip *at91_gpio; 389 void __iomem *pio; 390 u32 isr; 391 392 at91_gpio = get_irq_chip_data(irq); 393 pio = at91_gpio->regbase; 394 395 /* temporarily mask (level sensitive) parent IRQ */ 396 desc->chip->ack(irq); 397 for (;;) { 398 /* Reading ISR acks pending (edge triggered) GPIO interrupts. 399 * When there none are pending, we're finished unless we need 400 * to process multiple banks (like ID_PIOCDE on sam9263). 401 */ 402 isr = __raw_readl(pio + PIO_ISR) & __raw_readl(pio + PIO_IMR); 403 if (!isr) { 404 if (!at91_gpio->next) 405 break; 406 at91_gpio = at91_gpio->next; 407 pio = at91_gpio->regbase; 408 continue; 409 } 410 411 pin = at91_gpio->chip.base; 412 gpio = &irq_desc[pin]; 413 414 while (isr) { 415 if (isr & 1) { 416 if (unlikely(gpio->depth)) { 417 /* 418 * The core ARM interrupt handler lazily disables IRQs so 419 * another IRQ must be generated before it actually gets 420 * here to be disabled on the GPIO controller. 421 */ 422 gpio_irq_mask(pin); 423 } 424 else 425 generic_handle_irq(pin); 426 } 427 pin++; 428 gpio++; 429 isr >>= 1; 430 } 431 } 432 desc->chip->unmask(irq); 433 /* now it may re-trigger */ 434} 435 436/*--------------------------------------------------------------------------*/ 437 438#ifdef CONFIG_DEBUG_FS 439 440static int at91_gpio_show(struct seq_file *s, void *unused) 441{ 442 int bank, j; 443 444 /* print heading */ 445 seq_printf(s, "Pin\t"); 446 for (bank = 0; bank < gpio_banks; bank++) { 447 seq_printf(s, "PIO%c\t", 'A' + bank); 448 }; 449 seq_printf(s, "\n\n"); 450 451 /* print pin status */ 452 for (j = 0; j < 32; j++) { 453 seq_printf(s, "%i:\t", j); 454 455 for (bank = 0; bank < gpio_banks; bank++) { 456 unsigned pin = PIN_BASE + (32 * bank) + j; 457 void __iomem *pio = pin_to_controller(pin); 458 unsigned mask = pin_to_mask(pin); 459 460 if (__raw_readl(pio + PIO_PSR) & mask) 461 seq_printf(s, "GPIO:%s", __raw_readl(pio + PIO_PDSR) & mask ? "1" : "0"); 462 else 463 seq_printf(s, "%s", __raw_readl(pio + PIO_ABSR) & mask ? "B" : "A"); 464 465 seq_printf(s, "\t"); 466 } 467 468 seq_printf(s, "\n"); 469 } 470 471 return 0; 472} 473 474static int at91_gpio_open(struct inode *inode, struct file *file) 475{ 476 return single_open(file, at91_gpio_show, NULL); 477} 478 479static const struct file_operations at91_gpio_operations = { 480 .open = at91_gpio_open, 481 .read = seq_read, 482 .llseek = seq_lseek, 483 .release = single_release, 484}; 485 486static int __init at91_gpio_debugfs_init(void) 487{ 488 /* /sys/kernel/debug/at91_gpio */ 489 (void) debugfs_create_file("at91_gpio", S_IFREG | S_IRUGO, NULL, NULL, &at91_gpio_operations); 490 return 0; 491} 492postcore_initcall(at91_gpio_debugfs_init); 493 494#endif 495 496/*--------------------------------------------------------------------------*/ 497 498/* 499 * This lock class tells lockdep that GPIO irqs are in a different 500 * category than their parents, so it won't report false recursion. 501 */ 502static struct lock_class_key gpio_lock_class; 503 504/* 505 * Called from the processor-specific init to enable GPIO interrupt support. 506 */ 507void __init at91_gpio_irq_setup(void) 508{ 509 unsigned pioc, pin; 510 struct at91_gpio_chip *this, *prev; 511 512 for (pioc = 0, pin = PIN_BASE, this = gpio_chip, prev = NULL; 513 pioc++ < gpio_banks; 514 prev = this, this++) { 515 unsigned id = this->bank->id; 516 unsigned i; 517 518 __raw_writel(~0, this->regbase + PIO_IDR); 519 520 for (i = 0, pin = this->chip.base; i < 32; i++, pin++) { 521 lockdep_set_class(&irq_desc[pin].lock, &gpio_lock_class); 522 523 /* 524 * Can use the "simple" and not "edge" handler since it's 525 * shorter, and the AIC handles interrupts sanely. 526 */ 527 set_irq_chip(pin, &gpio_irqchip); 528 set_irq_handler(pin, handle_simple_irq); 529 set_irq_flags(pin, IRQF_VALID); 530 } 531 532 /* The toplevel handler handles one bank of GPIOs, except 533 * AT91SAM9263_ID_PIOCDE handles three... PIOC is first in 534 * the list, so we only set up that handler. 535 */ 536 if (prev && prev->next == this) 537 continue; 538 539 set_irq_chip_data(id, this); 540 set_irq_chained_handler(id, gpio_irq_handler); 541 } 542 pr_info("AT91: %d gpio irqs in %d banks\n", pin - PIN_BASE, gpio_banks); 543} 544 545/* gpiolib support */ 546static int at91_gpiolib_direction_input(struct gpio_chip *chip, 547 unsigned offset) 548{ 549 struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip); 550 void __iomem *pio = at91_gpio->regbase; 551 unsigned mask = 1 << offset; 552 553 __raw_writel(mask, pio + PIO_ODR); 554 return 0; 555} 556 557static int at91_gpiolib_direction_output(struct gpio_chip *chip, 558 unsigned offset, int val) 559{ 560 struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip); 561 void __iomem *pio = at91_gpio->regbase; 562 unsigned mask = 1 << offset; 563 564 __raw_writel(mask, pio + (val ? PIO_SODR : PIO_CODR)); 565 __raw_writel(mask, pio + PIO_OER); 566 return 0; 567} 568 569static int at91_gpiolib_get(struct gpio_chip *chip, unsigned offset) 570{ 571 struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip); 572 void __iomem *pio = at91_gpio->regbase; 573 unsigned mask = 1 << offset; 574 u32 pdsr; 575 576 pdsr = __raw_readl(pio + PIO_PDSR); 577 return (pdsr & mask) != 0; 578} 579 580static void at91_gpiolib_set(struct gpio_chip *chip, unsigned offset, int val) 581{ 582 struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip); 583 void __iomem *pio = at91_gpio->regbase; 584 unsigned mask = 1 << offset; 585 586 __raw_writel(mask, pio + (val ? PIO_SODR : PIO_CODR)); 587} 588 589static void at91_gpiolib_dbg_show(struct seq_file *s, struct gpio_chip *chip) 590{ 591 int i; 592 593 for (i = 0; i < chip->ngpio; i++) { 594 unsigned pin = chip->base + i; 595 void __iomem *pio = pin_to_controller(pin); 596 unsigned mask = pin_to_mask(pin); 597 const char *gpio_label; 598 599 gpio_label = gpiochip_is_requested(chip, i); 600 if (gpio_label) { 601 seq_printf(s, "[%s] GPIO%s%d: ", 602 gpio_label, chip->label, i); 603 if (__raw_readl(pio + PIO_PSR) & mask) 604 seq_printf(s, "[gpio] %s\n", 605 at91_get_gpio_value(pin) ? 606 "set" : "clear"); 607 else 608 seq_printf(s, "[periph %s]\n", 609 __raw_readl(pio + PIO_ABSR) & 610 mask ? "B" : "A"); 611 } 612 } 613} 614 615/* 616 * Called from the processor-specific init to enable GPIO pin support. 617 */ 618void __init at91_gpio_init(struct at91_gpio_bank *data, int nr_banks) 619{ 620 unsigned i; 621 struct at91_gpio_chip *at91_gpio, *last = NULL; 622 623 BUG_ON(nr_banks > MAX_GPIO_BANKS); 624 625 gpio_banks = nr_banks; 626 627 for (i = 0; i < nr_banks; i++) { 628 at91_gpio = &gpio_chip[i]; 629 630 at91_gpio->bank = &data[i]; 631 at91_gpio->chip.base = PIN_BASE + i * 32; 632 at91_gpio->regbase = at91_gpio->bank->offset + 633 (void __iomem *)AT91_VA_BASE_SYS; 634 635 /* enable PIO controller's clock */ 636 clk_enable(at91_gpio->bank->clock); 637 638 /* AT91SAM9263_ID_PIOCDE groups PIOC, PIOD, PIOE */ 639 if (last && last->bank->id == at91_gpio->bank->id) 640 last->next = at91_gpio; 641 last = at91_gpio; 642 643 gpiochip_add(&at91_gpio->chip); 644 } 645} 646