1/* 2 * linux/arch/alpha/kernel/sys_ruffian.c 3 * 4 * Copyright (C) 1995 David A Rusling 5 * Copyright (C) 1996 Jay A Estabrook 6 * Copyright (C) 1998, 1999, 2000 Richard Henderson 7 * 8 * Code supporting the RUFFIAN. 9 */ 10 11#include <linux/kernel.h> 12#include <linux/types.h> 13#include <linux/mm.h> 14#include <linux/sched.h> 15#include <linux/pci.h> 16#include <linux/ioport.h> 17#include <linux/timex.h> 18#include <linux/init.h> 19 20#include <asm/ptrace.h> 21#include <asm/system.h> 22#include <asm/dma.h> 23#include <asm/irq.h> 24#include <asm/mmu_context.h> 25#include <asm/io.h> 26#include <asm/pgtable.h> 27#include <asm/core_cia.h> 28#include <asm/tlbflush.h> 29#include <asm/8253pit.h> 30 31#include "proto.h" 32#include "irq_impl.h" 33#include "pci_impl.h" 34#include "machvec_impl.h" 35 36 37static void __init 38ruffian_init_irq(void) 39{ 40 /* Invert 6&7 for i82371 */ 41 *(vulp)PYXIS_INT_HILO = 0x000000c0UL; mb(); 42 *(vulp)PYXIS_INT_CNFG = 0x00002064UL; mb(); /* all clear */ 43 44 outb(0x11,0xA0); 45 outb(0x08,0xA1); 46 outb(0x02,0xA1); 47 outb(0x01,0xA1); 48 outb(0xFF,0xA1); 49 50 outb(0x11,0x20); 51 outb(0x00,0x21); 52 outb(0x04,0x21); 53 outb(0x01,0x21); 54 outb(0xFF,0x21); 55 56 /* Finish writing the 82C59A PIC Operation Control Words */ 57 outb(0x20,0xA0); 58 outb(0x20,0x20); 59 60 init_i8259a_irqs(); 61 62 /* Not interested in the bogus interrupts (0,3,6), 63 NMI (1), HALT (2), flash (5), or 21142 (8). */ 64 init_pyxis_irqs(0x16f0000); 65 66 common_init_isa_dma(); 67} 68 69#define RUFFIAN_LATCH DIV_ROUND_CLOSEST(PIT_TICK_RATE, HZ) 70 71static void __init 72ruffian_init_rtc(void) 73{ 74 /* Ruffian does not have the RTC connected to the CPU timer 75 interrupt. Instead, it uses the PIT connected to IRQ 0. */ 76 77 /* Setup interval timer. */ 78 outb(0x34, 0x43); /* binary, mode 2, LSB/MSB, ch 0 */ 79 outb(RUFFIAN_LATCH & 0xff, 0x40); /* LSB */ 80 outb(RUFFIAN_LATCH >> 8, 0x40); /* MSB */ 81 82 outb(0xb6, 0x43); /* pit counter 2: speaker */ 83 outb(0x31, 0x42); 84 outb(0x13, 0x42); 85 86 setup_irq(0, &timer_irqaction); 87} 88 89static void 90ruffian_kill_arch (int mode) 91{ 92 cia_kill_arch(mode); 93} 94 95/* 96 * Interrupt routing: 97 * 98 * Primary bus 99 * IdSel INTA INTB INTC INTD 100 * 21052 13 - - - - 101 * SIO 14 23 - - - 102 * 21143 15 44 - - - 103 * Slot 0 17 43 42 41 40 104 * 105 * Secondary bus 106 * IdSel INTA INTB INTC INTD 107 * Slot 0 8 (18) 19 18 17 16 108 * Slot 1 9 (19) 31 30 29 28 109 * Slot 2 10 (20) 27 26 25 24 110 * Slot 3 11 (21) 39 38 37 36 111 * Slot 4 12 (22) 35 34 33 32 112 * 53c875 13 (23) 20 - - - 113 * 114 */ 115 116static int __init 117ruffian_map_irq(struct pci_dev *dev, u8 slot, u8 pin) 118{ 119 static char irq_tab[11][5] __initdata = { 120 /*INT INTA INTB INTC INTD */ 121 {-1, -1, -1, -1, -1}, /* IdSel 13, 21052 */ 122 {-1, -1, -1, -1, -1}, /* IdSel 14, SIO */ 123 {44, 44, 44, 44, 44}, /* IdSel 15, 21143 */ 124 {-1, -1, -1, -1, -1}, /* IdSel 16, none */ 125 {43, 43, 42, 41, 40}, /* IdSel 17, 64-bit slot */ 126 /* the next 6 are actually on PCI bus 1, across the bridge */ 127 {19, 19, 18, 17, 16}, /* IdSel 8, slot 0 */ 128 {31, 31, 30, 29, 28}, /* IdSel 9, slot 1 */ 129 {27, 27, 26, 25, 24}, /* IdSel 10, slot 2 */ 130 {39, 39, 38, 37, 36}, /* IdSel 11, slot 3 */ 131 {35, 35, 34, 33, 32}, /* IdSel 12, slot 4 */ 132 {20, 20, 20, 20, 20}, /* IdSel 13, 53c875 */ 133 }; 134 const long min_idsel = 13, max_idsel = 23, irqs_per_slot = 5; 135 return COMMON_TABLE_LOOKUP; 136} 137 138static u8 __init 139ruffian_swizzle(struct pci_dev *dev, u8 *pinp) 140{ 141 int slot, pin = *pinp; 142 143 if (dev->bus->number == 0) { 144 slot = PCI_SLOT(dev->devfn); 145 } 146 /* Check for the built-in bridge. */ 147 else if (PCI_SLOT(dev->bus->self->devfn) == 13) { 148 slot = PCI_SLOT(dev->devfn) + 10; 149 } 150 else 151 { 152 /* Must be a card-based bridge. */ 153 do { 154 if (PCI_SLOT(dev->bus->self->devfn) == 13) { 155 slot = PCI_SLOT(dev->devfn) + 10; 156 break; 157 } 158 pin = pci_swizzle_interrupt_pin(dev, pin); 159 160 /* Move up the chain of bridges. */ 161 dev = dev->bus->self; 162 /* Slot of the next bridge. */ 163 slot = PCI_SLOT(dev->devfn); 164 } while (dev->bus->self); 165 } 166 *pinp = pin; 167 return slot; 168} 169 170#ifdef BUILDING_FOR_MILO 171/* 172 * The DeskStation Ruffian motherboard firmware does not place 173 * the memory size in the PALimpure area. Therefore, we use 174 * the Bank Configuration Registers in PYXIS to obtain the size. 175 */ 176static unsigned long __init 177ruffian_get_bank_size(unsigned long offset) 178{ 179 unsigned long bank_addr, bank, ret = 0; 180 181 /* Valid offsets are: 0x800, 0x840 and 0x880 182 since Ruffian only uses three banks. */ 183 bank_addr = (unsigned long)PYXIS_MCR + offset; 184 bank = *(vulp)bank_addr; 185 186 /* Check BANK_ENABLE */ 187 if (bank & 0x01) { 188 static unsigned long size[] __initdata = { 189 0x40000000UL, /* 0x00, 1G */ 190 0x20000000UL, /* 0x02, 512M */ 191 0x10000000UL, /* 0x04, 256M */ 192 0x08000000UL, /* 0x06, 128M */ 193 0x04000000UL, /* 0x08, 64M */ 194 0x02000000UL, /* 0x0a, 32M */ 195 0x01000000UL, /* 0x0c, 16M */ 196 0x00800000UL, /* 0x0e, 8M */ 197 0x80000000UL, /* 0x10, 2G */ 198 }; 199 200 bank = (bank & 0x1e) >> 1; 201 if (bank < ARRAY_SIZE(size)) 202 ret = size[bank]; 203 } 204 205 return ret; 206} 207#endif /* BUILDING_FOR_MILO */ 208 209/* 210 * The System Vector 211 */ 212 213struct alpha_machine_vector ruffian_mv __initmv = { 214 .vector_name = "Ruffian", 215 DO_EV5_MMU, 216 DO_DEFAULT_RTC, 217 DO_PYXIS_IO, 218 .machine_check = cia_machine_check, 219 .max_isa_dma_address = ALPHA_RUFFIAN_MAX_ISA_DMA_ADDRESS, 220 .min_io_address = DEFAULT_IO_BASE, 221 .min_mem_address = DEFAULT_MEM_BASE, 222 .pci_dac_offset = PYXIS_DAC_OFFSET, 223 224 .nr_irqs = 48, 225 .device_interrupt = pyxis_device_interrupt, 226 227 .init_arch = pyxis_init_arch, 228 .init_irq = ruffian_init_irq, 229 .init_rtc = ruffian_init_rtc, 230 .init_pci = cia_init_pci, 231 .kill_arch = ruffian_kill_arch, 232 .pci_map_irq = ruffian_map_irq, 233 .pci_swizzle = ruffian_swizzle, 234}; 235ALIAS_MV(ruffian) 236