1README on the SDRAM Controller for the LH7a40X 2============================================== 3 4The standard configuration for the SDRAM controller generates a sparse 5memory array. The precise layout is determined by the SDRAM chips. A 6default kernel configuration assembles the discontiguous memory 7regions into separate memory nodes via the NUMA (Non-Uniform Memory 8Architecture) facilities. In this default configuration, the kernel 9is forgiving about the precise layout. As long as it is given an 10accurate picture of available memory by the bootloader the kernel will 11execute correctly. 12 13The SDRC supports a mode where some of the chip select lines are 14swapped in order to make SDRAM look like a synchronous ROM. Setting 15this bit means that the RAM will present as a contiguous array. Some 16programmers prefer this to the discontiguous layout. Be aware that 17may be a penalty for this feature where some some configurations of 18memory are significantly reduced; i.e. 64MiB of RAM appears as only 32 19MiB. 20 21There are a couple of configuration options to override the default 22behavior. When the SROMLL bit is set and memory appears as a 23contiguous array, there is no reason to support NUMA. 24CONFIG_LH7A40X_CONTIGMEM disables NUMA support. When physical memory 25is discontiguous, the memory tables are organized such that there are 26two banks per nodes with a small gap between them. This layout wastes 27some kernel memory for page tables representing non-existent memory. 28CONFIG_LH7A40X_ONE_BANK_PER_NODE optimizes the node tables such that 29there are no gaps. These options control the low level organization 30of the memory management tables in ways that may prevent the kernel 31from booting or may cause the kernel to allocated excessively large 32page tables. Be warned. Only change these options if you know what 33you are doing. The default behavior is a reasonable compromise that 34will suit all users. 35 36-- 37 38A typical 32MiB system with the default configuration options will 39find physical memory managed as follows. 40 41 node 0: 0xc0000000 4MiB 42 0xc1000000 4MiB 43 node 1: 0xc4000000 4MiB 44 0xc5000000 4MiB 45 node 2: 0xc8000000 4MiB 46 0xc9000000 4MiB 47 node 3: 0xcc000000 4MiB 48 0xcd000000 4MiB 49 50Setting CONFIG_LH7A40X_ONE_BANK_PER_NODE will put each bank into a 51separate node. 52