1/*	$NetBSD: t_atomic_and.c,v 1.1 2019/02/17 12:24:17 isaki Exp $	*/
2
3/*
4 * Copyright (C) 2019 Tetsuya Isaki. All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 *    notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 *    notice, this list of conditions and the following disclaimer in the
13 *    documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
20 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
21 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
22 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
23 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 */
27
28#include <sys/cdefs.h>
29__RCSID("$NetBSD: t_atomic_and.c,v 1.1 2019/02/17 12:24:17 isaki Exp $");
30
31#include <atf-c.h>
32#include <inttypes.h>
33#include <sys/atomic.h>
34
35/*
36 * These tests don't examine the atomicity.
37 */
38
39#define DST    (0x1122334455667788UL)
40#define SRC    (0xf0f0f0f0f0f0f0f0UL)
41#define EXPECT (0x1020304050607080UL)
42
43/*
44 * atomic_and_*()
45 */
46#define atf_and(NAME, TYPE, FMT) \
47ATF_TC(NAME); \
48ATF_TC_HEAD(NAME, tc) \
49{ \
50	atf_tc_set_md_var(tc, "descr", #NAME); \
51} \
52ATF_TC_BODY(NAME, tc) \
53{ \
54	volatile TYPE val; \
55	TYPE src; \
56	TYPE exp; \
57	val = (TYPE)DST; \
58	src = (TYPE)SRC; \
59	exp = (TYPE)EXPECT; \
60	NAME(&val, src); \
61	ATF_REQUIRE_MSG(val == exp, \
62	    "val expects 0x%" FMT " but 0x%" FMT, exp, val); \
63}
64
65atf_and(atomic_and_32,    uint32_t,      PRIx32);
66atf_and(atomic_and_uint,  unsigned int,  "x");
67atf_and(atomic_and_ulong, unsigned long, "lx");
68#if defined(__HAVE_ATOMIC64_OPS)
69atf_and(atomic_and_64,    uint64_t,      PRIx64);
70#endif
71
72/*
73 * atomic_and_*_nv()
74 */
75#define atf_and_nv(NAME, TYPE, FMT) \
76ATF_TC(NAME); \
77ATF_TC_HEAD(NAME, tc) \
78{ \
79	atf_tc_set_md_var(tc, "descr", #NAME); \
80} \
81ATF_TC_BODY(NAME, tc) \
82{ \
83	volatile TYPE val; \
84	TYPE src; \
85	TYPE res; \
86	TYPE exp; \
87	val = (TYPE)DST; \
88	src = (TYPE)SRC; \
89	exp = (TYPE)EXPECT; \
90	res = NAME(&val, src); \
91	ATF_REQUIRE_MSG(val == exp, \
92	    "val expects 0x%" FMT " but 0x%" FMT, exp, val); \
93	ATF_REQUIRE_MSG(res == exp, \
94	    "res expects 0x%" FMT " but 0x%" FMT, exp, res); \
95}
96
97atf_and_nv(atomic_and_32_nv,    uint32_t,      PRIx32);
98atf_and_nv(atomic_and_uint_nv,  unsigned int,  "x");
99atf_and_nv(atomic_and_ulong_nv, unsigned long, "lx");
100#if defined(__HAVE_ATOMIC64_OPS)
101atf_and_nv(atomic_and_64_nv,    uint64_t,      PRIx64);
102#endif
103
104ATF_TP_ADD_TCS(tp)
105{
106	ATF_TP_ADD_TC(tp, atomic_and_32);
107	ATF_TP_ADD_TC(tp, atomic_and_uint);
108	ATF_TP_ADD_TC(tp, atomic_and_ulong);
109#if defined(__HAVE_ATOMIC64_OPS)
110	ATF_TP_ADD_TC(tp, atomic_and_64);
111#endif
112
113	ATF_TP_ADD_TC(tp, atomic_and_32_nv);
114	ATF_TP_ADD_TC(tp, atomic_and_uint_nv);
115	ATF_TP_ADD_TC(tp, atomic_and_ulong_nv);
116#if defined(__HAVE_ATOMIC64_OPS)
117	ATF_TP_ADD_TC(tp, atomic_and_64_nv);
118#endif
119
120	return atf_no_error();
121}
122