altr,rst-mgr-a10.h revision 1.1.1.1
1/* $NetBSD: altr,rst-mgr-a10.h,v 1.1.1.1 2017/06/15 20:14:23 jmcneill Exp $ */ 2 3/* 4 * Copyright (c) 2014, Steffen Trumtrar <s.trumtrar@pengutronix.de> 5 * 6 * This software is licensed under the terms of the GNU General Public 7 * License version 2, as published by the Free Software Foundation, and 8 * may be copied, distributed, and modified under those terms. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 */ 15 16#ifndef _DT_BINDINGS_RESET_ALTR_RST_MGR_A10_H 17#define _DT_BINDINGS_RESET_ALTR_RST_MGR_A10_H 18 19/* MPUMODRST */ 20#define CPU0_RESET 0 21#define CPU1_RESET 1 22#define WDS_RESET 2 23#define SCUPER_RESET 3 24 25/* PER0MODRST */ 26#define EMAC0_RESET 32 27#define EMAC1_RESET 33 28#define EMAC2_RESET 34 29#define USB0_RESET 35 30#define USB1_RESET 36 31#define NAND_RESET 37 32#define QSPI_RESET 38 33#define SDMMC_RESET 39 34#define EMAC0_OCP_RESET 40 35#define EMAC1_OCP_RESET 41 36#define EMAC2_OCP_RESET 42 37#define USB0_OCP_RESET 43 38#define USB1_OCP_RESET 44 39#define NAND_OCP_RESET 45 40#define QSPI_OCP_RESET 46 41#define SDMMC_OCP_RESET 47 42#define DMA_RESET 48 43#define SPIM0_RESET 49 44#define SPIM1_RESET 50 45#define SPIS0_RESET 51 46#define SPIS1_RESET 52 47#define DMA_OCP_RESET 53 48#define EMAC_PTP_RESET 54 49/* 55 is empty*/ 50#define DMAIF0_RESET 56 51#define DMAIF1_RESET 57 52#define DMAIF2_RESET 58 53#define DMAIF3_RESET 59 54#define DMAIF4_RESET 60 55#define DMAIF5_RESET 61 56#define DMAIF6_RESET 62 57#define DMAIF7_RESET 63 58 59/* PER1MODRST */ 60#define L4WD0_RESET 64 61#define L4WD1_RESET 65 62#define L4SYSTIMER0_RESET 66 63#define L4SYSTIMER1_RESET 67 64#define SPTIMER0_RESET 68 65#define SPTIMER1_RESET 69 66/* 70-71 is reserved */ 67#define I2C0_RESET 72 68#define I2C1_RESET 73 69#define I2C2_RESET 74 70#define I2C3_RESET 75 71#define I2C4_RESET 76 72/* 77-79 is reserved */ 73#define UART0_RESET 80 74#define UART1_RESET 81 75/* 82-87 is reserved */ 76#define GPIO0_RESET 88 77#define GPIO1_RESET 89 78#define GPIO2_RESET 90 79 80/* BRGMODRST */ 81#define HPS2FPGA_RESET 96 82#define LWHPS2FPGA_RESET 97 83#define FPGA2HPS_RESET 98 84#define F2SSDRAM0_RESET 99 85#define F2SSDRAM1_RESET 100 86#define F2SSDRAM2_RESET 101 87#define DDRSCH_RESET 102 88 89/* SYSMODRST*/ 90#define ROM_RESET 128 91#define OCRAM_RESET 129 92/* 130 is reserved */ 93#define FPGAMGR_RESET 131 94#define S2F_RESET 132 95#define SYSDBG_RESET 133 96#define OCRAM_OCP_RESET 134 97 98/* COLDMODRST */ 99#define CLKMGRCOLD_RESET 160 100/* 161-162 is reserved */ 101#define S2FCOLD_RESET 163 102#define TIMESTAMPCOLD_RESET 164 103#define TAPCOLD_RESET 165 104#define HMCCOLD_RESET 166 105#define IOMGRCOLD_RESET 167 106 107/* NRSTMODRST */ 108#define NRSTPINOE_RESET 192 109 110/* DBGMODRST */ 111#define DBG_RESET 224 112#endif 113