1/* $NetBSD: altr,rst-mgr-a10.h,v 1.1.1.2 2020/01/03 14:33:06 skrll Exp $ */ 2 3/* SPDX-License-Identifier: GPL-2.0-only */ 4/* 5 * Copyright (c) 2014, Steffen Trumtrar <s.trumtrar@pengutronix.de> 6 */ 7 8#ifndef _DT_BINDINGS_RESET_ALTR_RST_MGR_A10_H 9#define _DT_BINDINGS_RESET_ALTR_RST_MGR_A10_H 10 11/* MPUMODRST */ 12#define CPU0_RESET 0 13#define CPU1_RESET 1 14#define WDS_RESET 2 15#define SCUPER_RESET 3 16 17/* PER0MODRST */ 18#define EMAC0_RESET 32 19#define EMAC1_RESET 33 20#define EMAC2_RESET 34 21#define USB0_RESET 35 22#define USB1_RESET 36 23#define NAND_RESET 37 24#define QSPI_RESET 38 25#define SDMMC_RESET 39 26#define EMAC0_OCP_RESET 40 27#define EMAC1_OCP_RESET 41 28#define EMAC2_OCP_RESET 42 29#define USB0_OCP_RESET 43 30#define USB1_OCP_RESET 44 31#define NAND_OCP_RESET 45 32#define QSPI_OCP_RESET 46 33#define SDMMC_OCP_RESET 47 34#define DMA_RESET 48 35#define SPIM0_RESET 49 36#define SPIM1_RESET 50 37#define SPIS0_RESET 51 38#define SPIS1_RESET 52 39#define DMA_OCP_RESET 53 40#define EMAC_PTP_RESET 54 41/* 55 is empty*/ 42#define DMAIF0_RESET 56 43#define DMAIF1_RESET 57 44#define DMAIF2_RESET 58 45#define DMAIF3_RESET 59 46#define DMAIF4_RESET 60 47#define DMAIF5_RESET 61 48#define DMAIF6_RESET 62 49#define DMAIF7_RESET 63 50 51/* PER1MODRST */ 52#define L4WD0_RESET 64 53#define L4WD1_RESET 65 54#define L4SYSTIMER0_RESET 66 55#define L4SYSTIMER1_RESET 67 56#define SPTIMER0_RESET 68 57#define SPTIMER1_RESET 69 58/* 70-71 is reserved */ 59#define I2C0_RESET 72 60#define I2C1_RESET 73 61#define I2C2_RESET 74 62#define I2C3_RESET 75 63#define I2C4_RESET 76 64/* 77-79 is reserved */ 65#define UART0_RESET 80 66#define UART1_RESET 81 67/* 82-87 is reserved */ 68#define GPIO0_RESET 88 69#define GPIO1_RESET 89 70#define GPIO2_RESET 90 71 72/* BRGMODRST */ 73#define HPS2FPGA_RESET 96 74#define LWHPS2FPGA_RESET 97 75#define FPGA2HPS_RESET 98 76#define F2SSDRAM0_RESET 99 77#define F2SSDRAM1_RESET 100 78#define F2SSDRAM2_RESET 101 79#define DDRSCH_RESET 102 80 81/* SYSMODRST*/ 82#define ROM_RESET 128 83#define OCRAM_RESET 129 84/* 130 is reserved */ 85#define FPGAMGR_RESET 131 86#define S2F_RESET 132 87#define SYSDBG_RESET 133 88#define OCRAM_OCP_RESET 134 89 90/* COLDMODRST */ 91#define CLKMGRCOLD_RESET 160 92/* 161-162 is reserved */ 93#define S2FCOLD_RESET 163 94#define TIMESTAMPCOLD_RESET 164 95#define TAPCOLD_RESET 165 96#define HMCCOLD_RESET 166 97#define IOMGRCOLD_RESET 167 98 99/* NRSTMODRST */ 100#define NRSTPINOE_RESET 192 101 102/* DBGMODRST */ 103#define DBG_RESET 224 104#endif 105